Litt
Geoffrey Litt, London GB
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20140310819 | METHOD AND APPARATUS FOR ACCESSING MEDIA - A system controls access to a group of media items. A client device is operable by a user. A media server is coupled to at least one media data source, wherein the at least one media data source stores one or more media items for supply, by the media server, to the client device over a network. An authorization server is coupled to an authorization data source. The authorization data source stores data identifying a group of media items of fixed group size N that are accessible by the user, each media item in said group having a different associated availability parameter value indicating a number of time periods M within which access to the media item is available, wherein the authorization server is arranged to authorize the media server to supply a media item to the client device if said media item belongs to the group of media items. | 10-16-2014 |
Michael Litt, Toronto CA
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20110019787 | Method and Apparatus Synchronizing Integrated Circuit Clocks - Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device. | 01-27-2011 |
20120303995 | METHOD AND APPARATUS SYNCHRONIZING INTEGRATED CIRCUIT CLOCKS - Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device. | 11-29-2012 |
Michael J. Litt, Toronto CA
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20130290767 | COMMAND PROTOCOL FOR ADJUSTMENT OF WRITE TIMING DELAY - Apparatuses are provided for adjusting the write timing. For instance, the apparatus can include an address/control bus, a write clock data recovery (WCDR) signal bus, and a timing adjustment module. The address/control bus can be configured to concurrently enable a WCDR mode of operation and an active mode of operation. The WCDR signal bus can be configured to transmit WCDR data to a memory device during the WCDR mode of operation. And the timing adjustment module can be configured to adjust a timing based on a phase shift in the WCDR data. | 10-31-2013 |
Michael John Litt, Toronto CA
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20110208989 | Command Protocol for Adjustment of Write Timing Delay - A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal. | 08-25-2011 |