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Lisi
Anthony D. Lisi, Hopewell Junction, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110108989 | PROCESS FOR REVERSING TONE OF PATTERNS ON INTEGERATED CIRCUIT AND STRUCTURAL PROCESS FOR NANOSCALE FABRICATION - A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric. | 05-12-2011 |
| 20110121457 | Process for Reversing Tone of Patterns on Integrated Circuit and Structural Process for Nanoscale Production - A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric. | 05-26-2011 |
| 20110171582 | Three Dimensional Integration With Through Silicon Vias Having Multiple Diameters - A method is disclosed which includes patterning a photoresist layer on a substrate of a structure, removing a first portion of the photoresist layer to expose a first area of the substrate, etching the first area to form a cavity having a first depth, removing a second portion of the photoresist to expose an additional area of the substrate, and etching the cavity to expose a first conductor in the structure and the additional area to expose a second conductor in the structure. | 07-14-2011 |
Anthony D. Lisi, Poughkeepsie, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090200636 | SUB-LITHOGRAPHIC DIMENSIONED AIR GAP FORMATION AND RELATED STRUCTURE - Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer. | 08-13-2009 |
| 20090283912 | DAMASCENE WIRING FABRICATION METHODS INCORPORATING DIELECTRIC CAP ETCH PROCESS WITH HARD MASK RETENTION - Methods for fabricating metal wiring layers of a semiconductor device are provided where damascene interconnect structures are formed in a BEOL process that incorporates a dielectric cap-open-first process to achieve hard mask retention and to control the gouging of a buffer oxide layer to prevent exposure of underlying features protected by the buffer oxide layer. | 11-19-2009 |
| 20110168671 | PROCESS CONTROL USING SIGNAL REPRESENTATIVE OF A THROTTLE VALVE POSITION - In accordance with an embodiment of the invention, a step in a fabrication process can be conducted so as to determine when the process has reached an end point. End point detection can be performed by detecting when a operating process condition changes. For example, in one embodiment, a step in a fabrication process (e.g., an etching step) can be conducted in a chamber by varying a position of a throttle valve connected to the chamber so as to maintain a desired pressure within the chamber. In such method, it can be determined when the etching step has reached an end point by detecting when a signal representative of the throttle valve position changes in a particular way which matches an expected signature. In another embodiment, a step in a fabrication process can be conducted in a chamber by maintaining a desired flow within the chamber, such as by controlling a throttle valve, and allowing the pressure within the chamber to vary. In such method, it can be determined when the step has reached an end point by detecting when a signal representative of the pressure changes. In a particular embodiment in which end point detection is based on change in pressure, the throttle valve can be maintained at a particular position when conducting the step in the fabrication process. | 07-14-2011 |
| 20110221062 | METHODS FOR FABRICATION OF AN AIR GAP-CONTAINING INTERCONNECT STRUCTURE - Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures. | 09-15-2011 |
| 20110260326 | STRUCTURES AND METHODS FOR AIR GAP INTEGRATION - Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps of different depths are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures. | 10-27-2011 |
| 20110272810 | STRUCTURE AND METHOD FOR AIR GAP INTERCONNECT INTEGRATION - Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures. | 11-10-2011 |
Anthony D. Lisi, Armonk, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110020753 | Method for reversing tone of patterns on integrated circuit and patterning sub-lithography trenches - A method for reversing the tone of a lithographic image on a substrate comprises depositing a modifiable material on a substrate; applying a photolithographic material on the modifiable material: defining a removable patterned area in the photolithopgraphic material by photolithograpic means; removing the patterned area to produce an exposed region in the modifiable material that substantially conforms to the patterned area; producing a reacted modifiable material by increasing the etch resistance of the modifable material substantially throughout the exposed region so that the etch resistance of the exposed region comprises a region that substantially conforms to the exposed region; and removing the photoresist and the modifiable material to leave the reacted modifiable material and substrate. | 01-27-2011 |
Anthony David Lisi, Poughkeepsie, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090081873 | Methods of Patterning Insulating Layers Using Etching Techniques that Compensate for Etch Rate Variations - Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates. | 03-26-2009 |
Antonella Lisi, Roma IT
| Patent application number | Description | Published |
|---|---|---|
| 20100203620 | APPARATUS FOR CULTURING EUCARYOTIC AND/OR PROCARYOTIC CELLS - An apparatus for culturing eucaryotic and/or procaryotic cells comprising an incubator ( | 08-12-2010 |
| 20110262415 | ERYTHROCYTE-BASED DELIVERY SYSTEM, METHOD OF PREPARATION AND USES THEREOF - The invention relates to a cell-based drug delivery system comprising magneto nanoparticles, erythrocytes and a fusion-protein, its preparation and uses thereof in particular as a delivery system for biologically active compounds. | 10-27-2011 |
Carlo Lisi, Milano IT
| Patent application number | Description | Published |
|---|---|---|
| 20080259683 | METHOD AND CIRCUIT FOR PROGRAMMING A MEMORY CELL, IN PARTICULAR OF THE NOR FLASH TYPE - A method programs a memory cell comprising: an initial phase in which a continuous voltage is applied to a drain terminal of said memory cell and a suitable programming voltage signal is applied to a gate terminal thereof; a regulation phase in which a constant voltage value is applied to said gate terminal and a voltage value of said drain terminal is regulated so as to be maintained at a fixed value until a threshold voltage value of said memory cell is set at a desired threshold voltage level; and a disable phase that stops said programming and is triggered as soon as a programming current value of said memory cell goes below a reference current value, said reference current value corresponding to the attainment by the threshold voltage value of said memory cell of the desired threshold voltage value. A programming circuit is suitable for implementing this method. | 10-23-2008 |
| 20080266946 | METHOD OF MANAGING A MULTILEVEL MEMORY DEVICE AND RELATED DEVICE - A memory has an array of k-level cells, organized into pages of words, each storing a string of bits. The memory device includes a coding circuit input with strings of N bits, and generates corresponding k-level strings. A program circuit is input with the k-level strings to stores in groups of c cells with k levels. A read circuit reads data stored in groups of c cells with k levels and generates k-level strings. A read decoding circuit is input with k-level strings read from groups of c cells with k levels to generate strings of N bits. The words of each page are grouped in groups of words, each word including groups of c cells with k levels, and at least one remaining bit of the word being stored, with corresponding remaining bits of other words of the page, in a group of c cells with k levels. | 10-30-2008 |
Daniel J. Lisi, Eastpointe, MI US
| Patent application number | Description | Published |
|---|---|---|
| 20080248370 | REMOVAL OF NON-CONDUCTIVE HYDROPHILIC COATINGS FROM LANDS OF FUEL CELL BIPOLAR PLATES - A bipolar plate for a fuel cell is provided including a plate having an active surface with a plurality of flow channels formed therein. The plurality of flow channels have a hydrophilic coating deposited thereon and define a plurality of lands disposed therebetween. The plurality of lands is substantially free of the hydrophilic coating. Furthermore, a thickness of the hydrophilic coating is substantially constant along a length of the active surface and an edge of the hydrophilic coating adjacent the plurality of lands is substantially continuous. A method for preparing the bipolar plate is also provided. | 10-09-2008 |
| 20090176142 | CORROSION RESISTANT METAL COMPOSITE FOR ELECTROCHEMICAL DEVICES AND METHODS OF PRODUCING THE SAME - A metal composite for use in electrochemical devices is disclosed. The metal composite comprises a stainless steel interior component and a deposited nitrided metal exterior layer, wherein the nitrided exterior layer has lower electric contact resistance and greater corrosion resistance than the stainless steel interior component. A bipolar plate made of such metal composite and methods of producing the metal composite and bipolar plate are also disclosed. | 07-09-2009 |
| 20110254198 | FUEL CELLS COMPRISING MOLDABLE GASKETS, AND METHODS OF MAKING - Devices comprising an electrochemical conversion assembly comprise a plurality of electrochemical conversion cells, and a plurality of electrically conductive bipolar plates, wherein the electrochemical conversion cells are disposed between the adjacent bipolar plates. The electrochemical conversion assembly further comprises a plurality of conversion assembly gaskets, wherein the respective conversion assembly gaskets are molded onto corresponding ones of the plurality of bipolar plates. The conversion assembly gaskets comprise a mixture including polyvinylidene fluoride (PVDF). | 10-20-2011 |
Donald Lisi, Orange, FL US
| Patent application number | Description | Published |
|---|---|---|
| 20100179890 | TOOL INVENTORY MANAGEMENT SYSTEM - An inventory management system and method for operating said system, wherein the system comprises an enclosure for containing a plurality of inventory items; a locking mechanism for preventing unauthorized access of the enclosure; and a computing system for controlling the locking mechanism and recording a transaction. The computing system further comprises a processor, a data storage unit, and a graphical user interface. The computing system logs information regarding the specific item, the location of use, and the date and time of the transaction. In a preferred embodiment, the inventory items are tools. The present disclosure discloses methods for operating the inventory management system, including methods for assigning a desired item to an authorized user; returning an item from a user to whom the item has been assigned; transferring an item from a first user to a second user; and taking inventory. | 07-15-2010 |
Mario Lisi, Kitchener CA
| Patent application number | Description | Published |
|---|---|---|
| 20090184721 | METHOD AND SYSTEM FOR TRACKING SCATTERING PARAMETER TEST SYSTEM CALIBRATION - Embodiments describe methods of correcting S-parameter measurements for a DUT. The method includes coupling at least one tracking module associated with a set of electrical standards to a S-parameter measurement device to form a test system. An initial calibration for the test system is then determined. This may include measuring the S-parameters of the electrical standards, generating a calibration along a calibration plane, generating a calibration along a correction plane and determining at least one error adapter from the calibrations. The DUT is coupled to the test system and the S-parameters of the DUT are measured. Changes in the initial calibration are tracked using the tracking modules. Tracking may include measuring the S-parameters of the electrical standards, generating a correction plane calibration and generating a corrected calibration plane calibration from the correction plane calibration and the error adapter(s). The measured S-parameters are corrected using the tracked changes. | 07-23-2009 |
Renzo Lisi, Carmignano (po) IT
| Patent application number | Description | Published |
|---|---|---|
| 20110167623 | METHOD FOR ASSEMBLING THE ROTOR OF AN ELECTRIC MACHINE - Method for assembling the rotor (R) of an electric machine including a rotor (R) solid with a shaft ( | 07-14-2011 |
| 20110204736 | ELECTRIC ROTARY MACHINE - Electric machine comprising a rotor (R) with a shaft ( | 08-25-2011 |
Rocco Lisi, San Nicola La Strada Caserta IT
| Patent application number | Description | Published |
|---|---|---|
| 20120028602 | COMPUTER-IMPLEMENTED METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR TELECOMMUNICATIONS RATING - The present application relates to a computer-implemented method, system, and computer program product for telecommunications rating. The computer-implemented method for telecommunications rating may comprise: receiving an event from a source system for a service, wherein the event is generated by a user; transforming the event into a normalized event by determining event characteristics comprising determining a guiding point identifier to identify a guiding point associated with the user; by using the guiding point identifier, retrieving from the guiding point a list of products operable to guide the normalized event; rating the normalized event by calculating and aggregating costs according to the list of products; and posting the costs by updating at least one balance associated with the user, the guiding point, and/or the service. | 02-02-2012 |