Patent application number | Description | Published |
20090047798 | METHOD OF FORMING HIGH DIELECTRIC CONSTANT FILMS USING A PLURALITY OF OXIDATION SOURCES - A method is provided for depositing a high dielectric constant (high-k) film for integrated circuits (ICs) by atomic layer deposition (ALD) or chemical vapor deposition (CVD). The method includes exposing a substrate to one or more metal precursors and plurality of oxidation sources to deposit a high-k film with a desired thickness and tailored properties. The plurality of oxidation sources contain a first oxidation source containing H | 02-19-2009 |
20120040522 | METHOD FOR INTEGRATING MULTIPLE THRESHOLD VOLTAGE DEVICES FOR CMOS - A method to achieve multiple threshold voltage (Vt) devices on the same semiconductor chip is disclosed. The method provides different threshold voltage devices using threshold voltage adjusting materials and a subsequent drive in anneal instead of directly doping the channel. As such, the method of the present disclosure avoids short channel penalties. Additionally, no ground plane/back gates are utilized in the present application thereby the method of the present disclosure can be easily integrated into current complementary metal oxide semiconductor (CMOS) processing technology. | 02-16-2012 |
20120126295 | BORDERLESS CONTACT FOR REPLACEMENT GATE EMPLOYING SELECTIVE DEPOSITION - A self-aligned gate cap dielectric can be employed to form a self-aligned contact to a diffusion region, while preventing electrical short with a gate conductor due to overlay variations. In one embodiment, an electroplatable or electrolessly platable metal is selectively deposited on conductive materials in a gate electrode, while the metal is not deposited on dielectric surfaces. The metal portion on top of the gate electrode is converted into a gate cap dielectric including the metal and oxygen. In another embodiment, a self-assembling monolayer is formed on dielectric surfaces, while exposing metallic top surfaces of a gate electrode. A gate cap dielectric including a dielectric oxide is formed on areas not covered by the self-assembling monolayer. The gate cap dielectric functions as an etch-stop structure during formation of a via hole, so that electrical shorting between a contact via structure formed therein and the gate electrode is avoided. | 05-24-2012 |
20120305940 | Defect Free Si:C Epitaxial Growth - A method and structure are disclosed for a defect free Si:C source/drain in an NFET device. A wafer is accepted with a primary surface of {100} crystallographic orientation. A recess is formed in the wafer in such manner that the bottom surface and the four sidewall surfaces of the recess are all having {100} crystallographic orientations. A Si:C material is eptaxially grown in the recess, and due to the crystallographic orientations the defect density next to each of the four sidewall surfaces is essentially the same as next to the bottom surface. The epitaxially filled recess is used in the source/drain fabrication of an NFET device. The NFET device is oriented along the <100> crystallographic direction, and has the device channel under a tensile strain due to the defect free Si:C in the source/drain. | 12-06-2012 |
20140054717 | INTEGRATION OF MULTIPLE THRESHOLD VOLTAGE DEVICES FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR USING FULL METAL GATE - A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited over the substrate, and a first full metal gate stack is deposited over the gate dielectric. The first full metal gate stack is removed over the first region to produce a resulting structure. Over the resulting structure, a second full metal gate stack is deposited, in contact with the gate dielectric over the first region. The first and second full metal gate stacks are encapsulated. | 02-27-2014 |
20140084382 | DUAL METAL FILL AND DUAL THRESHOLD VOLTAGE FOR REPLACEMENT GATE METAL DEVICES - A structure and method for forming a dual metal fill and dual threshold voltage for replacement gate metal devices is disclosed. A selective deposition process involving titanium and aluminum is used to allow formation of two adjacent transistors with different fill metals and different workfunction metals, enabling different threshold voltages in the adjacent transistors. | 03-27-2014 |
20140162447 | FINFET HYBRID FULL METAL GATE WITH BORDERLESS CONTACTS - A method for fabricating a field effect transistor device includes patterning a fin on substrate, patterning a gate stack over a portion of the fin and a portion of an insulator layer arranged on the substrate, forming a protective barrier over the gate stack, a portion of the fin and a portion of the insulator layer, the protective barrier enveloping the gate stack, depositing a second insulator layer over portions of the fin and the protective barrier, performing a first etching process to selectively remove portions of the second insulator layer to define cavities that expose portions of source and drain regions of the fin without appreciably removing the protective barrier, and depositing a conductive material in the cavities. | 06-12-2014 |
20150311109 | CHANNEL SiGe DEVICES WITH MULTIPLE THRESHOLD VOLTAGES ON HYBRID ORIENTED SUBSTRATES, AND METHODS OF MANUFACTURING SAME - Multiple threshold voltage devices on hybrid oriented substrates, and methods of manufacturing same are disclosed. A method for manufacturing a semiconductor device comprises performing a single epitaxy step on a hybrid orientation substrate including a first region having a first crystallographic orientation and a second region having a second crystallographic orientation different from the first crystallographic orientation, wherein the single epitaxy step forms a first layer disposed on the first region and a second layer disposed on the second region, the first layer has the first crystallographic orientation and a first composition, and the second layer has the second crystal orientation and a second composition different from the first composition. | 10-29-2015 |