| Patent application number | Description | Published |
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| 20090182964 | DYNAMIC ADDRESS TRANSLATION WITH FORMAT CONTROL - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If the format control field is enabled, a frame address of a large block of data in main storage is obtained from the translation table entry. The large block of data is a block of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a desired block of data within the large block of data in main storage. The desired large block of data addressed by the translated address is then accessed. | 07-16-2009 |
| 20090182966 | DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAGEMENT - What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field. | 07-16-2009 |
| 20090182971 | DYNAMIC ADDRESS TRANSLATION WITH FETCH PROTECTION - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being executed. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field. | 07-16-2009 |
| 20090182972 | DYNAMIC ADDRESS TRANSLATION WITH FORMAT CONTROL - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory. | 07-16-2009 |
| 20090187724 | DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAGEMENT - What is disclosed is a set key and clear frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which identifies a first and second general register. Obtained from the first general register is a frame size field indicating whether a storage frame is one of a small block or a large block of data. Obtained from the second general register is an operand address of a storage frame upon which the instruction is to be performed. If the storage frame is a small block, the instruction is performed only on the small block. If the indicated storage frame is a large block of data, an operand address of an initial first block of data within the large block of data is obtained from the second general register. The frame management instruction is performed on all blocks starting from the initial first block. | 07-23-2009 |
| 20090187728 | DYNAMIC ADDRESS TRANSLATION WITH CHANGE RECORDING OVERRIDE - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. A segment table entry obtained from a segment table contains a format control field. If the format control field is enabled, a segment-frame absolute address of a large block of data in main storage is obtained from the segment table entry. Each 4K byte block of data within the large block has an associated storage key. Store operations associated with the virtual address are performed to the desired block of data. If the change recording override field is disabled, the change bit of the storage key associated with the desired 4K byte block is set to 1. An indication is then provided that the desired 4K byte block has been modified. | 07-23-2009 |
| 20090187732 | DYNAMIC ADDRESS TRANSLATION WITH DAT PROTECTION - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of any one of a region first table, a region second table, a region third table, or a segment table are obtained. Based on the obtained initial origin address, a segment table entry is obtained which contains a format control and DAT protection fields. If the format control field is enabled, obtaining from the translation table entry a segment-frame absolute address of a large block of data in main storage. The segment-frame absolute address is combined with a page index portion and a byte index portion of the virtual address to form a translated address of the desired block of data. If the DAT protection field is not enabled, fetches and stores are permitted to the desired block of data addressed by the translated virtual address. | 07-23-2009 |
| 20090193214 | DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAGEMENT - What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained containing an opcode for a frame management instruction identifying a first and second general register. Clear frame information is obtained from the first general register having a frame size field indicating whether a storage frame is a small or large block of data. The second general register contains an operand address of a storage frame. If the storage frame is a small block, all bytes of the small block of data are set to zero. If the storage frame is a large block of data, an operand address of an initial first block of data within the large block is obtained from the second general register. All data of all blocks within the large block are cleared starting from the initial first block. | 07-30-2009 |
| 20090216928 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A NEW QUIESCE STATE - A system, method and computer program product for providing a new quiesce state. The method includes receiving a quiesce request at a system controller from an initiating processor. The quiesce request is sent to a plurality of processors. Notification is received at the system controller that the processors have finished purging their translation look aside buffers (TLBs). A fast quiesce reset command is received at the system controller from the initiating processor once updates to the system resources are complete. It is indicated to the processors that the block translation restriction can be dropped in response to receiving the fast quiesce reset command, thereby allowing the processors to continue processing without block translation restrictions. | 08-27-2009 |
| 20090216929 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A PROGRAMMABLE QUIESCE FILTERING REGISTER - A system, method and computer program product for providing a programmable quiesce filtering register. The method includes receiving a quiesce interruption request at the processor. The processor is executing in a mode. A filtering zone associated with the mode is identified. It is determined if the quiesce interruption request can be filtered by the processor. The determining is responsive to the filtering zone and to contents of a programmable filtering register for indicating exceptions to filtering performed by the receiving processor. The quiesce interruption request is filtered in response to determining that the request can be filtered. | 08-27-2009 |
| 20090216963 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A SHARED MEMORY TRANSLATION FACILITY - A system, method and computer program product for providing a shared memory translation facility. The method includes receiving a request for access to a memory address from a requestor at a configuration, the receiving at a shared memory translation mechanism. It is determined if the memory address refers to a shared memory object (SMO), the SMO accessible by a plurality of configurations. In response to determining that the memory address refers to the SMO, it is determined if the configuration has access to the SMO. In response to determining that the configuration has access to the SMO, the requestor is provided a system absolute address for the SMO and access to the SMO. In this manner direct interchange of data between the plurality of configurations is allowed. | 08-27-2009 |
| 20090216992 | DYNAMIC ADDRESS TRANSLATION WITH TRANSLATION EXCEPTION QUALIFIER - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame. | 08-27-2009 |
| 20090216995 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING QUIESCE FILTERING FOR SHARED MEMORY - A system, method and computer program product for providing quiesce filtering for shared memory. The method includes receiving a shared-memory quiesce request at a processor. The request includes a donor zone. The processor includes translation look aside buffer one (TLB | 08-27-2009 |
| 20090217264 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PROVIDING FILTERING OF GUEST2 QUIESCE REQUESTS - A method, system and computer program product for providing filtering of level two guest (G2) quiesce requests. The method includes receiving a G2 quiesce interruption request at a processor currently or previously executing a G2 running under a level two hypervisor in a logical partition. The G2 includes a current zone and G2 virtual machine (VM) identifier. The quiesce interruption request specifies an initiating zone and an initiating G2 VM identifier. It is determined if the G2 quiesce interruption request can be filtered by the processor. The determining is responsive to the current G2 VM identifier, the current zone, the initiating zone and the initiating G2 VM identifier. The G2 quiesce interruption request is filtered at the processor in response to determining that the G2 quiesce interruption request can be filtered. Thus, filtering between G2 virtual machines running in the logical partition is provided. | 08-27-2009 |
| 20090217269 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING MULTIPLE QUIESCE STATE MACHINES - A system, method and computer program product for providing multiple quiesce state machines. The system includes a first controller including logic for processing a first quiesce request. The system also includes a second controller including logic for processing a second quiesce request. All or a portion of the processing of the second quiesce request overlaps in time with the processing of the first quiesce request. Thus, multiple quiesce requests may be active in the system at the same time. | 08-27-2009 |
| 20090240908 | FILTERING PROCESSOR REQUESTS BASED ON IDENTIFIERS - Processing within a computing environment is facilitated by filtering requests of the computing environment. A processing unit that receives a request determines whether it is to perform the request. This determination is made by, for instance, comparing an identifier of the request with an identifier of the processing unit making the determination. If there is a mismatch, then the request is blocked. Other processing within the computing environment is also facilitated by selectively using buffer entries. The selection criteria is based, for instance, on identifier information. | 09-24-2009 |
| 20110119466 | Clearing Selected Storage Translation Buffer Entries Bases On Table Origin Address - An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of storage. The buffer entries related to segment table entries or region table entries or ASCE addresses. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof. | 05-19-2011 |
