Patent application number | Description | Published |
20110098157 | SYSTEMS, METHODS AND APPARATUS FOR CALIBRATING DIFFERENTIAL AIR PRESSURE DEVICES - Methods, apparatus, and systems for calibrating differential air pressure systems are described. The methods, apparatus, and systems may be adapted for physical training of an individual, e.g. as a training tool to improve performance or as a physical therapy tool for rehabilitation or strengthening. The differential air pressure systems comprise a chamber for receiving at least a portion of a user's body. In one embodiment, a method for calibrating a differential air pressure system for predicting effective body weight of a user versus system pressure is described. In certain variations, the methods, apparatus and systems may comprise adjusting pressure in the system until one or more force values are reached. The methods described herein may comprise determining a relationship between body weight force and pressure, allowing the user to set a pressure or a parameter correlated with pressure to achieve a desired effective body weight. | 04-28-2011 |
20110098615 | SYSTEMS, METHODS AND APPARATUS FOR DIFFERENTIAL AIR PRESSURE DEVICES - Described herein are various embodiments of differential air pressure systems and components for differential air pressure systems. The air pressure systems comprise a chamber for receiving at least a portion of a user's body. Pressure in the chamber can be changed to adjust force on the user's body. Described herein are various methods and related structures for sealing a user into a pressurizable chamber. Also described herein are various methods and related structures for changing the shape and/or height of the chamber. Described herein are various types and configurations of chambers and support structures for chambers. Also described herein are various methods and related systems for treating various conditions using the differential air pressure systems, including but not limited to obesity, cardiac disease, multiple sclerosis, cerebral palsy, or Down Syndrome. | 04-28-2011 |
20120277643 | SYSTEMS, METHODS AND APPARATUS FOR CALIBRATING DIFFERENTIAL AIR PRESSURE DEVICES - Methods, apparatus, and systems for calibrating differential air pressure systems are described. The methods, apparatus, and systems may be adapted for physical training of an individual, e.g. as a training tool to improve performance or as a physical therapy tool for rehabilitation or strengthening. The differential air pressure systems comprise a chamber for receiving at least a portion of a user's body. In one embodiment, a method for calibrating a differential air pressure system for predicting effective body weight of a user versus system pressure is described. In certain variations, the methods, apparatus and systems may comprise adjusting pressure in the system until one or more force values are reached. The methods described herein may comprise determining a relationship between body weight force and pressure, allowing the user to set a pressure or a parameter correlated with pressure to achieve a desired effective body weight. | 11-01-2012 |
20140025113 | COMPOSITE SPINAL FACET IMPLANT WITH TEXTURED SURFACES - Implementations described and claimed herein provide a distal leading portion of a composite spinal implant for implantation in a spinal facet joint. In one implementation, the distal leading portion includes a distal leading end, a proximal trailing end, a first face, and a second face. The distal leading end has a distal surface generally opposite a proximal surface of the proximal trailing end. The first face has a first surface that is generally parallel with a second surface of the second face. The first and second faces extend between the distal leading end and the proximal trailing end, such that the first and second surfaces slope upwardly from the distal lead end to the proximal trailing end along a length of extending proximally. The first and second surfaces having one or more textured features adapted to provide friction with the spinal facet joint. | 01-23-2014 |
20140100657 | SPINAL FACET CAGE IMPLANT - Implementations described and claimed herein provide a spinal facet cage implant for implantation in a spinal facet joint. In one implementation, the implant includes a distal leading end, a proximal trailing end, a first face, and a second face. The distal leading end has a distal surface generally opposite a proximal surface of the proximal trailing end. The first face has a first surface that is generally parallel with a second surface of the second face. The first and second faces extend between the distal leading end and the proximal trailing end. The first and second surfaces having one or more textured features adapted to provide friction with the spinal facet joint. One or more windows are defined in the first and/or second surfaces, and one or more side windows are defined in the first and/or second side surfaces. | 04-10-2014 |
Patent application number | Description | Published |
20100191241 | Vertebral joint implants and delivery tools - A spinal joint distraction system for treating a facet joint including articular surfaces having a contour is disclosed and may include a delivery device including a generally tubular structure adapted to engage a facet joint, an implant adapted to be delivered through the delivery device and into the facet joint, the implant comprising two members arranged in opposed position, and an implant distractor comprising a generally elongate member adapted to advance between the two members of the implant causing separation of the members and distraction of the facet joint, wherein the implant is adapted to conform to the shape of the implant distractor and/or the articular surfaces of the facet upon being delivered to the facet joint. Several embodiments of a system, several embodiments of an implant, and several methods are disclosed including a method for interbody fusion. | 07-29-2010 |
20110087255 | SYSTEMS AND METHODS FOR TREATMENT OF COMPRESSED NERVES - Disclosed herein is a system for releasing a ligament. In one embodiment, the system includes a proximal handle, a tubular body, and a flexible body. The tubular body includes a proximal end and a distal end. The handle is coupled to the proximal end. The flexible body extends through the tubular body and includes a tissue cutting portion. The flexible body is longitudinally displaceable relative to the tubular body to move the tissue cutting portion between a non-deployed state and a deployed state. | 04-14-2011 |
20110306996 | SYSTEMS AND METHODS FOR TREATMENT OF COMPRESSED NERVES - Disclosed herein is a system for releasing a ligament. In one embodiment, the system includes a proximal handle, a tubular body, and a flexible body. The tubular body includes a proximal end and a distal end. The handle is coupled to the proximal end. The flexible body extends through the tubular body and includes a tissue cutting portion. The flexible body or tubular body is longitudinally displaceable to move the tissue cutting portion between a non-deployed state and a deployed state. | 12-15-2011 |
20130012994 | VERTEBRAL JOINT IMPLANTS AND DELIVERY TOOLS - A spinal joint distraction system for treating a facet joint including articular surfaces having a contour is disclosed and may include a delivery device including a generally tubular structure adapted to engage a facet joint, an implant adapted to be delivered through the delivery device and into the facet joint, the implant comprising two members arranged in opposed position, and an implant distractor comprising a generally elongate member adapted to advance between the two members of the implant causing separation of the members and distraction of the facet joint, wherein the implant is adapted to conform to the shape of the implant distractor and/or the articular surfaces of the facet upon being delivered to the facet joint. Several embodiments of a system, several embodiments of an implant, and several methods are disclosed including a method for interbody fusion. | 01-10-2013 |
20130013070 | VERTEBRAL JOINT IMPLANTS AND DELIVERY TOOLS - A spinal joint distraction system for treating a facet joint including articular surfaces having a contour is disclosed and may include a delivery device including a generally tubular structure adapted to engage a facet joint, an implant adapted to be delivered through the delivery device and into the facet joint, the implant comprising two members arranged in opposed position, and an implant distractor comprising a generally elongate member adapted to advance between the two members of the implant causing separation of the members and distraction of the facet joint, wherein the implant is adapted to conform to the shape of the implant distractor and/or the articular surfaces of the facet upon being delivered to the facet joint. Several embodiments of a system, several embodiments of an implant, and several methods are disclosed including a method for interbody fusion. | 01-10-2013 |
20130018474 | VERTEBRAL JOINT IMPLANTS AND DELIVERY TOOLS - A spinal joint distraction system for treating a facet joint including articular surfaces having a contour is disclosed and may include a delivery device including a generally tubular structure adapted to engage a facet joint, an implant adapted to be delivered through the delivery device and into the facet joint, the implant comprising two members arranged in opposed position, and an implant distractor comprising a generally elongate member adapted to advance between the two members of the implant causing separation of the members and distraction of the facet joint, wherein the implant is adapted to conform to the shape of the implant distractor and/or the articular surfaces of the facet upon being delivered to the facet joint. Several embodiments of a system, several embodiments of an implant, and several methods are disclosed including a method for interbody fusion. | 01-17-2013 |
20130023995 | VERTEBRAL JOINT IMPLANTS AND DELIVERY TOOLS - A spinal joint distraction system for treating a facet joint including articular surfaces having a contour is disclosed and may include a delivery device including a generally tubular structure adapted to engage a facet joint, an implant adapted to be delivered through the delivery device and into the facet joint, the implant comprising two members arranged in opposed position, and an implant distractor comprising a generally elongate member adapted to advance between the two members of the implant causing separation of the members and distraction of the facet joint, wherein the implant is adapted to conform to the shape of the implant distractor and/or the articular surfaces of the facet upon being delivered to the facet joint. Several embodiments of a system, several embodiments of an implant, and several methods are disclosed including a method for interbody fusion. | 01-24-2013 |
20130023996 | VERTEBRAL JOINT IMPLANTS AND DELIVERY TOOLS - A spinal joint distraction system for treating a facet joint including articular surfaces having a contour is disclosed and may include a delivery device including a generally tubular structure adapted to engage a facet joint, an implant adapted to be delivered through the delivery device and into the facet joint, the implant comprising two members arranged in opposed position, and an implant distractor comprising a generally elongate member adapted to advance between the two members of the implant causing separation of the members and distraction of the facet joint, wherein the implant is adapted to conform to the shape of the implant distractor and/or the articular surfaces of the facet upon being delivered to the facet joint. Several embodiments of a system, several embodiments of an implant, and several methods are disclosed including a method for interbody fusion. | 01-24-2013 |
20130030440 | VERTEBRAL JOINT IMPLANTS AND DELIVERY TOOLS - A spinal joint distraction system for treating a facet joint including articular surfaces having a contour is disclosed and may include a delivery device including a generally tubular structure adapted to engage a facet joint, an implant adapted to be delivered through the delivery device and into the facet joint, the implant comprising two members arranged in opposed position, and an implant distractor comprising a generally elongate member adapted to advance between the two members of the implant causing separation of the members and distraction of the facet joint, wherein the implant is adapted to conform to the shape of the implant distractor and/or the articular surfaces of the facet upon being delivered to the facet joint. Several embodiments of a system, several embodiments of an implant, and several methods are disclosed including a method for interbody fusion. | 01-31-2013 |
20130030532 | VERTEBRAL JOINT IMPLANTS AND DELIVERY TOOLS - A spinal joint distraction system for treating a facet joint including articular surfaces having a contour is disclosed and may include a delivery device including a generally tubular structure adapted to engage a facet joint, an implant adapted to be delivered through the delivery device and into the facet joint, the implant comprising two members arranged in opposed position, and an implant distractor comprising a generally elongate member adapted to advance between the two members of the implant causing separation of the members and distraction of the facet joint, wherein the implant is adapted to conform to the shape of the implant distractor and/or the articular surfaces of the facet upon being delivered to the facet joint. Several embodiments of a system, several embodiments of an implant, and several methods are disclosed including a method for interbody fusion. | 01-31-2013 |
20130110146 | SYSTEMS AND METHODS FOR TREATMENT OF COMPRESSED NERVES | 05-02-2013 |
20130131454 | SYSTEMS AND METHODS FOR TREATMENT OF COMPRESSED NERVES - Disclosed herein is a system for releasing a ligament. In one embodiment, the system includes a proximal handle, a tubular body, and a flexible body. The tubular body includes a proximal end and a distal end. The handle is coupled to the proximal end. The flexible body extends through the tubular body and includes a tissue cutting portion. The flexible body or tubular body is longitudinally displaceable to move the tissue cutting portion between a non-deployed state and a deployed state. | 05-23-2013 |
20140249558 | SYSTEMS AND METHODS FOR TREATMENT OF COMPRESSED NERVES - Disclosed herein is a system for releasing a ligament. In one embodiment, the system includes a proximal handle, a tubular body, and a flexible body. The tubular body includes a proximal end and a distal end. The handle is coupled to the proximal end. The flexible body extends through the tubular body and includes a tissue cutting portion. The flexible body is longitudinally displaceable relative to the tubular body to move the tissue cutting portion between a non-deployed state and a deployed state. | 09-04-2014 |
20150073461 | SYSTEMS AND METHODS FOR TREATMENT OF COMPRESSED NERVES - Disclosed herein is a system for releasing a ligament. In one embodiment, the system includes a proximal handle, a tubular body, and a flexible body. The tubular body includes a proximal end and a distal end. The handle is coupled to the proximal end. The flexible body extends through the tubular body and includes a tissue cutting portion. The flexible body or tubular body is longitudinally displaceable to move the tissue cutting portion between a non-deployed state and a deployed state. | 03-12-2015 |
Patent application number | Description | Published |
20080258291 | Semiconductor Packaging With Internal Wiring Bus - A packaged semiconductor includes inner bond fingers, at least first and second semiconductor dies, and an interposer. The packaged semiconductor further includes wiring between the first and second semiconductor dies and the inner bond fingers, wiring between the interposer and the inner bond fingers, and wiring between the interposer and the first and second semiconductor dies. The wiring between the interposer and the first and second semiconductor dies thereby reduces the count of inner bond fingers needed for the wiring between the first and second semiconductor dies and the inner bond fingers. The interposer further provides indirect access to the inner bond fingers when the inner bond fingers are inaccessible by the first and second semiconductor dies. | 10-23-2008 |
20090269891 | THERMAL ENHANCED PACKAGE - A method of manufacturing an integrated circuit package. The method includes attaching a first surface of a semiconductor die to a thermally and/or electrically conductive substrate, forming a plurality of die connectors on a second surface of the semiconductor die, and encapsulating the semiconductor die and the plurality of die connectors in an encapsulant material. The method also includes removing a portion of the encapsulant material to expose one or more of the plurality of die connectors, thereby forming a routing surface. The method further includes forming a plurality of conductive traces on the routing surface. Each of the plurality of conductive traces is characterized by a first portion in electrical communication with one of the plurality of die connectors and a second portion in electrical communication with a package connector. | 10-29-2009 |
20100283143 | Die Exposed Chip Package - This disclosure describes a chip package. In one embodiment, a semiconductor chip package includes a thermal dissipater placed on top of an integrated-circuit die, the thermal dissipater having a same or similar coefficient of thermal expansion as that of the integrated-circuit die. | 11-11-2010 |
20110049710 | INTERCONNECT LAYOUTS FOR ELECTRONIC ASSEMBLIES - Embodiments of the present disclosure provide an apparatus including an electronic device and a substrate to receive the electronic device, the electronic device being electrically coupled to the substrate using a plurality of interconnect structures, the interconnect structures being arranged on the electronic device based at least in part on a layout of the substrate. Other embodiments may be described and/or claimed. | 03-03-2011 |
20110121444 | EMBEDDED CHIP PACKAGES - Embodiments of the present disclosure provide configurations for a semiconductor package and associated methods of fabricating the semiconductor package. A method of fabricating a semiconductor package includes attaching a semiconductor die to a first substrate, attaching a second substrate to the first substrate, wherein the semiconductor die is embedded in between the first substrate and the second substrate, and forming an electrically insulative structure to substantially encapsulate the semiconductor die, wherein forming the electrically insulative structure is performed subsequent to the second substrate being attached to the first substrate. Additional embodiments may be described and/or claimed. | 05-26-2011 |
20110169163 | ATTACHING PASSIVE COMPONENTS TO A SEMICONDUCTOR PACKAGE - Embodiments of the present disclosure provide a method comprising forming an electrically conductive structure on a surface of a semiconductor die, attaching the semiconductor die to a substrate, forming a molding compound to encapsulate the semiconductor die, forming an opening in the molding compound, the opening to at least partially expose the electrically conductive structure, and electrically coupling a passive component to the electrically conductive structure through the opening in the molding compound. Other embodiments may be described and/or claimed. | 07-14-2011 |
20110175218 | PACKAGE ASSEMBLY HAVING A SEMICONDUCTOR SUBSTRATE - Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed. | 07-21-2011 |
20110180913 | METHOD OF STACKING FLIP-CHIP ON WIRE-BONDED CHIP - Some of the embodiments of the present disclosure provide apparatuses, systems, and methods for stacking chips. A first chip may be mounted on a substrate, wherein an active surface of the first chip faces away from the substrate, and wherein the first chip includes a plurality of bump pads located on the active surface of the first chip, and a wire may bond a first bump pad of the plurality of bump pads to the substrate. An intermediate layer may be disposed on at least a portion of the active surface of the first chip, and a via within the intermediate layer may extend to a second bump pad of the plurality of bump pads. A second chip may be disposed on the intermediate layer, wherein an active surface of the second chip faces towards the substrate, and wherein the second chip includes a third bump pad (i) located on the active surface of the second chip and (ii) aligned with the via formed in the intermediate layer. A corresponding bump may be disposed on one or more of (i) the second bump pad located on the active surface of the first chip and (ii) the third bump pad located on the active surface of the second chip, and within the via, wherein the corresponding bump electrically connects the second bump pad with the third bump pad. Other embodiments are also described and claimed. | 07-28-2011 |
20110186960 | TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES - Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed. | 08-04-2011 |
20110186992 | RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES - Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed. | 08-04-2011 |
20110186998 | RECESSED SEMICONDUCTOR SUBSTRATES - Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed. | 08-04-2011 |
20110298117 | PAD CONFIGURATIONS FOR AN ELECTRONIC PACKAGE ASSEMBLY - Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die. Other embodiments may be described and/or claimed. | 12-08-2011 |
20120196407 | SINGLE LAYER BGA SUBSTRATE PROCESS - Embodiments of the present disclosure provide semiconductor packaging techniques that form a substrate using metal and insulating materials. The substrate includes a first surface that is bonded to a semiconductor device and a second surface that is bonded to a printed circuit board. The substrate is formed using several techniques that minimize the amount of mask levels used to form the substrate. For example, a metal substrate is patterned to form a three dimensional pattern on the surface. A dielectric material is deposited on the three dimensional pattern. Using several patterning and polishing embodiments described herein, the metal/dielectric substrate is patterned and polished to form a substantially flush surface that is bonded to the semiconductor device. In one embodiment, the top surface of the metal/dielectric substrate is patterned to expose the underlying metal substrate and the bottom surface of the metal substrate is polished to be substantially flush with the dielectric material. | 08-02-2012 |
20130011964 | THERMAL ENHANCED PACKAGE - A method of manufacturing an integrated circuit package. The method includes attaching a first surface of a semiconductor die to a thermally and/or electrically conductive substrate, forming a plurality of die connectors on a second surface of the semiconductor die, and encapsulating the semiconductor die and the plurality of die connectors in an encapsulant material. The method also includes removing a portion of the encapsulant material to expose one or more of the plurality of die connectors, thereby forming a routing surface. The method further includes forming a plurality of conductive traces on the routing surface. Each of the plurality of conductive traces is characterized by a first portion in electrical communication with one of the plurality of die connectors and a second portion in electrical communication with a package connector. | 01-10-2013 |
20130043587 | PACKAGE-ON-PACKAGE STRUCTURES - Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls. | 02-21-2013 |
20130045573 | CHIP ON LEADS - Described herein are microelectronic packages including a plurality of bonding fingers and multiple integrated circuit chips, at least one integrated circuit chip being mounted onto the bonding fingers. According to various embodiments of the present invention, mounting the integrated circuit chip onto the bonding fingers may reduce the pin-out count by allowing multiple integrated circuit chips to be interconnected within the same microelectronic package. Other embodiments may be described and claimed. | 02-21-2013 |
20130147025 | METHOD OF STACKING FLIP-CHIP ON WIRE-BONDED CHIP - A first chip is mounted on a substrate and includes a plurality of bump pads located on an active surface of the first chip. A wire bonds a first bump pad to the substrate. An intermediate layer is disposed on a portion of the active surface of the first chip, and a via within the intermediate layer extends to a second bump pad. A second chip is disposed on the intermediate layer, and wherein the second chip includes a third bump pad located on an active surface of the second chip and aligned with the via formed in the intermediate layer. A corresponding bump is disposed on one or more of the second bump pad and the third bump pad, and within the via, wherein the corresponding bump electrically connects the second bump pad with the third bump pad. | 06-13-2013 |
20130193572 | BALL GRID ARRAY PACKAGE SUBSTRATE WITH THROUGH HOLES AND METHOD OF FORMING SAME - In accordance with an embodiment, there is provided a substrate of a ball grid array package that includes a first layer including reinforcement fibers. The reinforcement fibers reinforce the first layer such that the first layer has a higher tensile strength relative to a layer in the ball grid array package that is free of reinforcement fibers. In an embodiment, the substrate comprises a second layer disposed adjacent to the first layer with the second layer being free of reinforcement fibers. In an embodiment, the substrate also includes a through hole penetrating each of the first layer and the second layer. The through hole penetrates each of the first layer and the second layer based on each of the first layer and the second layer having been drilled in accordance with a mechanical drilling process. | 08-01-2013 |
20140069703 | DUAL ROW QUAD FLAT NO-LEAD SEMICONDUCTOR PACKAGE - Some of the embodiments of the present disclosure provide a Quad Flat No-Lead package comprising: an outer row of outer peripheral leads disposed on an outer periphery of a bottom surface of the Quad Flat No-Lead package; and an inner row of inner peripheral leads disposed on an inner periphery of the bottom surface of the Quad Flat No-Lead package, wherein each of the inner peripheral leads has a substantially rectangular shape, and wherein the substantially rectangular shape has two rounded corners adjacent to the outer row of outer peripheral leads. | 03-13-2014 |
20140124961 | TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES - Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed. | 05-08-2014 |
20140151880 | PACKAGE-ON-PACKAGE STRUCTURES - Embodiments of the present disclosure provide a package on package arrangement comprising a first package including a substrate layer including a top side, and a bottom side that is opposite to the top side, wherein the top side of the substrate layer defines a substantially flat surface, and a first die coupled to the bottom side of the substrate layer. The arrangement also comprises a second package including a plurality of rows of solder balls and at least one of one or both of an active component or a passive component. The second package is attached, via the plurality of rows of solder balls, to the substantially flat surface of the top side of the substrate layer of the first package. The active component and/or a passive component is attached to the substantially flat surface of the top side of the substrate layer of the first package. | 06-05-2014 |
20140206152 | SINGLE LAYER BGA SUBSTRATE PROCESS - The present disclosure provides semiconductor packaging techniques that form a substrate using metal and insulating materials. The substrate includes a first surface that is bonded to a semiconductor device and a second surface that is bonded to a printed circuit board. The substrate is formed using several techniques that minimize the amount of mask levels used to form the substrate. For example, a metal substrate is patterned to form a three dimensional pattern on the surface. A dielectric material is deposited on the three dimensional pattern. Using several patterning and polishing embodiments described herein, the metal/dielectric substrate is patterned and polished to form a substantially flush surface that is bonded to the semiconductor device. In one embodiment, the top surface of the metal/dielectric substrate is patterned to expose the underlying metal substrate and the bottom surface of the metal substrate is polished to be substantially flush with the dielectric material. | 07-24-2014 |
20150035160 | PAD CONFIGURATIONS FOR AN ELECTRONIC PACKAGE ASSEMBLY - Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die. | 02-05-2015 |
20150200114 | ATTACHING PASSIVE COMPONENTS TO A SEMICONDUCTOR PACKAGE - Embodiments of the present disclosure provide a method comprising forming an electrically conductive structure on a surface of a semiconductor die, attaching the semiconductor die to a substrate, forming a molding compound to encapsulate the semiconductor die, forming an opening in the molding compound, the opening to at least partially expose the electrically conductive structure, and electrically coupling a passive component to the electrically conductive structure through the opening in the molding compound. Other embodiments may be described and/or claimed. | 07-16-2015 |
20150221577 | PACKAGE ASSEMBLY HAVING A SEMICONDUCTOR SUBSTRATE - Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed. | 08-06-2015 |
20150257281 | METHOD FOR FORMING A VIA STRUCTURE USING A DOUBLE-SIDE LASER PROCESS - Embodiments include a multi-layer apparatus comprising a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer, wherein one or more of the dielectric layers include metal layers. The multi-layer apparatus further comprises a first via coupling a first metal layer and a second metal layer, a second via coupling the second metal layer and a fourth metal layer, a third via coupling the first metal layer and the second metal layer, and a fourth via coupling the third metal layer and the fourth metal layer. The first via is contiguous with the second via and the third via is contiguous with the fourth via. At least some of the vias have different depths relative to one another. | 09-10-2015 |
20150279806 | RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES - Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed. | 10-01-2015 |