Patent application number | Description | Published |
20090046170 | DIGITAL VIDEO CAMERA NON-INTEGER-RATIO BAYER DOMAIN SCALER - An apparatus having a buffer and a circuit is disclosed. The buffer may be configured to receive a digital image. The digital image generally has (i) a Bayer color representation and (ii) two initial dimensions in a horizontal direction and a vertical direction respectively. The circuit may be configured to generate a resample image in a signal by down-sampling the digital image in the Bayer color representation such that (i) the resample image has two resample dimensions, (ii) at least one of the resample dimensions is smaller than a respective at least one of the initial dimensions and (iii) the respective at least one initial dimension is a non-integer multiple of the at least one resample dimension. | 02-19-2009 |
20100061449 | PROGRAMMABLE QUANTIZATION DEAD ZONE AND THRESHOLD FOR STANDARD-BASED H.264 AND/OR VC1 VIDEO ENCODING - A video encoder including an encoder circuit, a quantizer circuit and a control circuit. The encoder circuit may be configured to generate a plurality of coefficient values and motion vectors in response to a video stream, a first control signal, a second control signal, and a number of quantized values. The control circuit may be configured to (i) generate the first control signal, the second control signal, and a quantizer index signal and (ii) set two or more quantization dead zones and two or more offsets to different values, where the quantization dead zones and the offsets are independently programmable. The quantizer circuit may be configured to generate the number of quantized values in response to the coefficient values, the quantizer index signal, the two or more quantization dead zones and the two or more offsets. A first coefficient value may be quantized using a first quantization dead zone and a first offset. A second coefficient value may be quantized using a second quantization dead zone and a second offset. The first and second quantization dead zones generally have different values. The first and second offsets generally have different values. Quantization calculations determining each quantized value take into account respective quantization dead zones and offsets. | 03-11-2010 |
20100086059 | COMPRESSED VIDEO FORMAT WITH PARTIAL PICTURE REPRESENTATION - An encoder comprising a first circuit and a second circuit. The first circuit may be configured to (i) generate a cropped video signal in response to separating a video signal and (ii) generate overscan information describing a shape of an overscan region. The video signal conveys an image having a picture region containing image information and the overscan region. The cropped video signal conveys the picture region. The second circuit may be configured to generate a digital video bit-stream in response to compressing said cropped video signal. The overscan region is absent from the digital video bit-stream as transmitted from the encoder. | 04-08-2010 |
20100157103 | HIGH RESOLUTION ZOOM: A NOVEL DIGITAL ZOOM FOR DIGITAL VIDEO CAMERA - A camera system and a method for zooming the camera system is disclosed. The method generally includes the steps of (A) generating an electronic image by sensing an optical image received by the camera, the sensing including electronic cropping to a window size to establish an initial resolution for the electronic image, (B) generating a final image by decimating the electronic image by a decimation factor to a final resolution smaller than the initial resolution and (C) changing a zoom factor for the final image by adjusting both of the decimation factor and the window size. | 06-24-2010 |
20110069206 | HIGH RESOLUTION ZOOM: A NOVEL DIGITAL ZOOM FOR DIGITAL VIDEO CAMERA - A camera system and a method for zooming the camera system is disclosed. The method generally includes the steps of (A) generating an electronic image by sensing an optical image received by the camera, the sensing including electronic cropping to a window size to establish an initial resolution for the electronic image, (B) generating a final image by decimating the electronic image by a decimation factor to a final resolution smaller than the initial resolution and (C) changing a zoom factor for the final image by adjusting both of the decimation factor and the window size. | 03-24-2011 |
20110096231 | METHOD FOR VIDEO DEINTERLACING AND FORMAT CONVERSION - A method for deinterlacing a picture is disclosed. The method generally includes the steps of (A) generating a plurality of primary scores by searching along a plurality of primary angles for an edge in the picture proximate a location interlaced with a field of the picture, (B) generating a plurality of neighbor scores by searching for the edge along a plurality of neighbor angles proximate a particular angle of the primary angles corresponding to a particular score of the primary scores having a best value and (C) identifying a best score from a group of scores consisting of the particular score and the neighbor scores to generate an interpolated sample at the location. | 04-28-2011 |
20110211756 | DIGITAL VIDEO CAMERA NON-INTEGER-RATIO BAYER DOMAIN SCALER - An apparatus having a buffer and a circuit is disclosed. The buffer may be configured to receive a digital image. The digital image generally has (i) a Bayer color representation and (ii) two initial dimensions in a horizontal direction and a vertical direction respectively. The circuit may be configured to generate a resample image in a signal by down-sampling the digital image in the Bayer color representation such that (i) the resample image has two resample dimensions, (ii) at least one of the resample dimensions is smaller than a respective at least one of the initial dimensions and (iii) the respective at least one initial dimension is a non-integer multiple of the at least one resample dimension. | 09-01-2011 |
20110310968 | METHOD AND APPARATUS FOR DETERMINING A SECOND PICTURE FOR TEMPORAL DIRECT-MODE BLOCK PREDICTION - A method for determining a first and a second reference picture used for inter-prediction of a macroblock, comprising the steps of (A) finding a co-located picture and block, (B) determining a reference index, (C) mapping the reference index to a lowest valued reference index in a current reference list and (D) using the reference index to determine the second reference picture. | 12-22-2011 |
Patent application number | Description | Published |
20090125748 | Methods for the Support of JTAG for Source Synchronous Interfaces - Exemplary embodiments of the present invention comprise a method for the support of a JTAG interface for the testing of connectivity between integrated circuits. The method comprises delivering output from a JTAG register to a primary register, delivering a JTAG control signal to the primary register and a clock signal gating control logic, delivering output from the primary register and a secondary register to a multiplexer, delivering clock signal output from the clock signal gating control logic to the multiplexer, wherein the clock signal is delivered is a constant and known value, and delivering the output from the multiplexer to an I/O driver. | 05-14-2009 |
20090125767 | Methods for the Support of JTAG for Source Synchronous Interfaces - Exemplary embodiments of the present invention comprise a method for the support of a JTAG interface for the testing of connectivity between integrated circuits. The method comprises delivering output from a JTAG register to a primary register, delivering a JTAG control signal to the primary register and a clock signal gating control logic, delivering output from the primary register and a secondary register to a multiplexer, delivering clock signal output from the clock signal gating control logic to the multiplexer, wherein the clock signal is delivered is a constant and known value, and delivering the output from the multiplexer to an I/O driver. | 05-14-2009 |
20090154269 | MANAGING REDUNDANT MEMORY IN A VOLTAGE ISLAND - An approach that manages redundant memory in a voltage island is described. In one embodiment there is a design structure embodied in a machine readable medium used in a design process of a semiconductor device. In this embodiment, the design structure includes one or more voltage islands representing a power cycled region. Each of the one or more voltage islands comprises at least one memory using redundancy and a repair register associated with each memory using redundancy. One or more non-power cycled regions are located about the one or more voltage islands. Each of the one or more non-power cycled regions comprises at least one memory using redundancy and a repair register associated with each memory using redundancy. A redundancy initialization component is coupled to the one or more voltage islands and the one or more non-power cycled regions. The redundancy initialization component is configured to initialize each memory using redundancy and associated repair register with repair data. The redundancy initialization component is configured to initialize a memory using redundancy and associated repair register with repair data independent of, or in conjunction with, the initialization of other memories using redundancy and associated repair registers. | 06-18-2009 |
20110047521 | DEVELOPMENT TOOL FOR COMPARING NETLISTS - System, method, and program product analyze netlists for related electrical circuit designs by comparing predefined physical characteristics between the netlists. A baseline reference score is generated for one of the netlists and a normalized score is generated for the other netlist. The baseline reference score and the normalized score are used to generate a similarity score that is displayed on a display monitor. Preferably, the similarity score is displayed as a percentage. | 02-24-2011 |
Patent application number | Description | Published |
20110207600 | Method of Making Heteropoly Acid Compound Catalysts - The invention is for a method for making a heteropoly acid compound catalyst from compounds containing molybdenum, vanadium, phosphorus, cesium, copper, bismuth, antimony and boron in which molybdenum, vanadium, phosphorus, cesium, copper, bismuth and boron are at their highest oxidation states and antimony has a 3+ oxidation state. The catalyst contains oxides of molybdenum, vanadium, phosphorus, cesium, copper, bismuth, antimony, boron and, optionally, other metals. The catalyst has the formula: | 08-25-2011 |