Patent application number | Description | Published |
20120313186 | POLYSILICON GATE WITH NITROGEN DOPED HIGH-K DIELECTRIC AND SILICON DIOXIDE - A polysilicon gate structure includes a substrate, a silicon dioxide layer disposed over the substrate, a nitrogen-doped high-k dielectric layer disposed over the silicon dioxide layer, and a polysilicon gate disposed over the nitrogen-doped high-k dielectric layer. | 12-13-2012 |
20130002263 | RELIABILITY ASSESSMENT OF CAPACITOR DEVICE - A method of reliability testing of a semiconductor device is described. The embodiment, includes providing a capacitor including an insulating layer interposing two conductive layers. A plurality of voltages are provided to the capacitor including providing a first voltage and a second voltage greater than the first voltage. A leakage associated with the capacitor is measured while applying the second voltage. In an embodiment, the leakage measured while applying the second voltage indicates that a failure of the insulating layer of the capacitor has occurred. In an embodiment, the capacitor is an inter-digitated metal-oxide-metal (MOM) capacitor. The reliability testing may be correlated to TDDB test results. The reliability testing may be performed at a wafer-level. | 01-03-2013 |
20130020717 | INTEGRATED CIRCUIT HAVING A STRESSOR AND METHOD OF FORMING THE SAME - An embodiment of the disclosure includes a method of forming a semiconductor structure. A substrate has a region adjacent to a shallow trench isolation (STI) structure in the substrate. A patterned mask layer is formed over the substrate. The patterned mask layer covers the STI structure and a portion of the region, and leaves a remaining portion of the region exposed. A distance between an edge of the remaining portion and an edge of the STI structure is substantially longer than 1 nm. The remaining portion of the region is etched thereby forms a recess in the substrate. A stressor is epitaxially grown in the recess. A conductive plug contacting the stressor is formed. | 01-24-2013 |
20130024833 | Reducing Metal Pits Through Optical Proximity Correction - A method includes retrieving first layouts of an integrated circuit from a non-transitory computer-readable medium. The first layouts include a via pattern in a via layer, and a metal line pattern in a metal layer immediately over the via layer. The metal line pattern has an enclosure to the via pattern. The enclosure is increased to a second enclosure to generate second layouts of the integrated circuit. | 01-24-2013 |
20130043590 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING - The present application discloses a method of manufacturing a semiconductor structure. According to at least one embodiment, a first etch stop layer is formed over a conductive feature and a substrate, and the conductive feature is positioned over the substrate. A second etch stop layer is formed over the first etch stop layer. A first etch is performed to form an opening in the second etch stop layer, and the opening exposes a portion of the first etch stop layer. A second etch is performed to extend the opening downwardly by removing a portion of the exposed first etch stop layer, and the extended opening exposes a portion of the conductive feature. | 02-21-2013 |
20130049781 | Semiconductor Devices with Self-heating Structures, Methods of Manufacture Thereof, and Testing Methods - Semiconductor devices with self-heating structures, methods of manufacture thereof, and testing methods are disclosed. In one embodiment, a semiconductor device includes a workpiece, an active electrical structure disposed over the workpiece, and at least one self-heating structure disposed proximate the active electrical structure. | 02-28-2013 |
20130069162 | OPTICAL PROXIMITY CORRECTION FOR ACTIVE REGION DESIGN LAYOUT - The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature. | 03-21-2013 |
20130071995 | Method of Manufacturing a Semiconductor Device - A method of manufacturing a semiconductor device is disclosed. The exemplary method includes providing a substrate having a source region and a drain region. The method further includes forming a first recess in the substrate within the source region and a second recess in the substrate within the drain region. The first recess has a first plurality of surfaces and the second recess has a second plurality of surfaces. The method also includes epi-growing a semiconductor material in the first and second recesses and, thereafter, forming shallow isolation (STI) features in the substrate. | 03-21-2013 |
20130075725 | ENHANCED WAFER TEST LINE STRUCTURE - A semiconductor wafer has a die area and a scribe area. A first dummy pad is formed in a first test line area of the scribe area and filled with a first material as part of a first metal layer. A first interlayer dielectric is formed over the first metal layer. A first interconnect pattern is formed in the die area and above the first interlayer dielectric, and a first trench pattern is formed in the first test line area of the scribe area and above the interlayer dielectric. The first interconnect pattern and the first trench pattern are filled with a second metal layer, and the first trench pattern is aligned above the first dummy pad. An enhanced test line structure including the first trench pattern and the first dummy pad is formed and probed in a back end of line (BEOL) process. | 03-28-2013 |
20130087857 | NITROGEN PASSIVATION OF SOURCE AND DRAIN RECESSES - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. In an example, the method includes providing a substrate; forming a gate structure over the substrate; removing portions of the substrate to form a first recess and a second recess in the substrate, such that the gate structure interposes the first recess and the second recess; forming a nitrogen passivation layer in the substrate, such that the first recess and the second recess are defined by nitrogen passivated surfaces of the substrate; and forming doped source and drain features over the nitrogen passivated surfaces of the first recess and the second recess, the doped source and drain features filling the first and second recesses. | 04-11-2013 |
20130087885 | Metal-Oxide-Metal Capacitor Apparatus - A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger are in parallel and separated by a low k dielectric material. A via-hole region is employed to enclose the metal-oxide-metal capacitor so as to remove the moisture stored in the low k dielectric material. | 04-11-2013 |
20130093047 | Metal-Oxide-Metal Capacitor Structure - A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger are in parallel and separated by a low k dielectric material. A guard ring is employed to enclose the metal-oxide-metal capacitor so as to prevent moisture from penetrating into the low k dielectric material. | 04-18-2013 |
20130111419 | METHOD AND SYSTEM FOR MODIFYING DOPED REGION DESIGN LAYOUT DURING MASK PREPARATION TO TUNE DEVICE PERFORMANCE | 05-02-2013 |
20130157467 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method of patterning a material layer of a semiconductor device is disclosed, the method including treating a material layer above a semiconductor substrate with plasma oxygen; depositing a layer of photoresist over a first surface of the material layer after the treating of the material layer; patterning the layer of photoresist, thereby forming a patterned photoresist, exposing portions of the material layer; etching the exposed portions of at least the material layer to form at least one contact via in the material layer extending to a source or drain region of a device at a surface of the substrate; and removing the patterned photoresist from the first surface of the material layer. | 06-20-2013 |
20130200442 | SALICIDE FORMATION USING A CAP LAYER - A semiconductor device having a source feature and a drain feature formed in a substrate. The semiconductor device having a gate stack over a portion of the source feature and over a portion of the drain feature. The semiconductor device further having a first cap layer formed over substantially the entire source feature not covered by the gate stack, and a second cap layer formed over substantially the entire drain feature not covered by the gate stack. A method of forming a semiconductor device including forming a source feature and drain feature in a substrate. The method further includes forming a gate stack over a portion of the source feature and over a portion of the drain feature. The method further includes depositing a first cap layer over substantially the entire source feature not covered by the gate stack and a second cap layer over substantially the entire drain feature not covered by the gate stack. | 08-08-2013 |
20130207166 | Methods and Apparatus for Doped SiGe Source/Drain Stressor Deposition - A semiconductor device system, structure and method of manufacture of a source/drain with SiGe stressor material to address effects due to dopant out-diffusion are disclosed. In an embodiment, a semiconductor substrate is provided with a gate structure, and recesses for source and drain are formed on opposing sides of the gate structure. Doped stressors are embedded into the recessed source and drain regions, and a plurality of layers of undoped stressor, lightly doped stressor, highly doped stressor, and a cap layer are formed in an in-situ epitaxial process. In another embodiment the doped stressor material is boron doped epitaxial SiGe. In an alternative embodiment an additional layer of undoped stressor material is formed. | 08-15-2013 |
20130234217 | MOS Devices Having Non-Uniform Stressor Doping - A device includes a semiconductor substrate, a gate stack over the semiconductor substrate, and a stressor region having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor region includes a first stressor region having a first p-type impurity concentration, a second stressor region over the first stressor region, wherein the second stressor region has a second p-type impurity concentration, and a third stressor region over the second stressor region. The third stressor region has a third p-type impurity concentration. The second p-type impurity concentration is lower than the first and the third p-type impurity concentrations. | 09-12-2013 |
20130240502 | RAPID THERMAL ANNEAL SYSTEM AND PROCESS - A rapid thermal anneal system and method for processing a semiconductor substrate. The system includes a chamber configured for holding a semiconductor substrate, a heating lamp array, and a process controller operably connected to the lamp array for controlling a heating cycle of the substrate. The lamp array includes a plurality of lamps positioned to heat the substrate. The controller is operable to energize or de-energize each lamp on an individual basis, and further to simultaneously energize one or more localized groups or clusters of lamps each having at least two adjacent lamps arranged for heating geographically localized regions of the substrate having special heating needs. The system is further operable to energize all lamps in the array simultaneously. The system and method provides the capability to perform customized substrate annealing. | 09-19-2013 |
20130267069 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is disclosed. The exemplary method includes providing a substrate having a source region and a drain region. The method further includes forming a first recess in the substrate within the source region and a second recess in the substrate within the drain region. The first recess has a first plurality of surfaces and the second recess has a second plurality of surfaces. The method also includes epi-growing a semiconductor material in the first and second recesses and, thereafter, forming shallow isolation (STI) features in the substrate. | 10-10-2013 |
20130285194 | OPTICAL PROXIMITY CORRECTION FOR ACTIVE REGION DESIGN LAYOUT - The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature. | 10-31-2013 |
20130299987 | SEMICONDUCTOR STRUCTURE HAVING ETCH STOP LAYER - A semiconductor structure includes a substrate, a conductive feature over the substrate, a conductive plug structure contacting a portion of an upper surface of the conductive feature, a first etch stop layer over another portion of the upper surface of the conductive feature, and a second etch stop layer over the first etch stop layer. The first etch stop layer is a doped etch stop layer. The first etch stop layer is to function as an etch stop layer during a predetermined etching process for etching the second etch stop layer. | 11-14-2013 |
20130323859 | SYSTEM AND METHOD OF MONITORING AND CONTROLLING ATOMIC LAYER DEPOSITION OF TUNGSTEN - A method of semiconductor processing comprises providing a semiconductor wafer in a processing chamber; feeding at least one tungsten-containing precursor in a gas state into the processing chamber for atomic layer deposition (ALD) of tungsten; feeding at least one reducing chemical in a gas state into the processing chamber; and monitoring a concentration of at least one gaseous byproduct in the chamber; and providing a signal indicating concentration of the at least one gaseous byproduct in the chamber. The byproduct is produced by a reaction between the at least one tungsten-containing precursor and the at least one reducing chemical during the ALD. | 12-05-2013 |
20130328127 | SiGe SRAM BUTTED CONTACT RESISTANCE IMPROVEMENT - The present disclosure relates to a device and method for fabricating a semiconductor memory device arrangement comprising a butted a contact arrangement configured to couple two transistors, wherein an active area of a first transistor is coupled to an active gate of a second transistor. The active gate of the second transistor is formed from a gate material which comprises a dummy gate of the first transistor, and is configured to straddle a boundary between the active area of the first transistor and an isolation layer formed about the first transistor. The butted a contact arrangement results in a decreased contact resistance for the butted contact as compared to previous methods. | 12-12-2013 |
20140001597 | Voids in Interconnect Structures and Methods for Forming the Same | 01-02-2014 |
20140053869 | Maranagoni Dry with Low Spin Speed for Charging Release - A method of cleaning and drying a semiconductor wafer including inserting a semiconductor wafer into a chamber of a cleaning tool, spinning the semiconductor wafer in a range of about 300 revolutions per minute to about 1600 revolutions per minute, and simultaneously spraying the semiconductor wafer with de-ionized water and a mixture of isopropyl alcohol and nitrogen. | 02-27-2014 |
20140054716 | SRAM Cells with Dummy Insertions - A device includes a first pull-up transistor, a second pull-up transistor, and a dummy gate electrode between the first and the second pull-up transistors. The first and the second pull-up transistors are included in a first Static Random Access Memory (SRAM) cell. | 02-27-2014 |
20140117512 | SURFACE PROFILE FOR SEMICONDUCTOR REGION - One or more techniques or systems for controlling a profile of a surface of a semiconductor region are provided herein. In some embodiments, an etching to deposition (E/D) ratio is set to be less than one to form the region within the semiconductor. For example, when the E/D ratio is less than one, an etching rate is less than a deposition rate of the E/D ratio, thus ‘growing’ the region. In some embodiments, the E/D ratio is subsequently set to be greater than one. For example, when the E/D ratio is greater than one, the etching rate is greater than the deposition rate of the E/D ratio, thus ‘etching’ the region. In this manner, a smooth surface profile is provided for the region, at least because setting the E/D ratio to be greater than one enables etch back of at least a portion of the grown region. | 05-01-2014 |
20140175556 | SEMICONDUCTOR DEVICE HAVING V-SHAPED REGION - Among other things, a semiconductor device or transistor and a method for forming the semiconductor device are provided for herein. The semiconductor device comprises one or more v-shaped recesses in which stressed monocrystalline semiconductor material, such as silicon germanium, is grown, to form at least one of a source or a drain of the semiconductor device. The one or more v-shaped recesses are etched into a substrate in-situ. The semiconductor device comprises at least one of a source or a drain having a height-to-length ratio exceeding at least 1.6 when poly spacing between a first part of the semiconductor device (e.g., first transistor) and a second part of the semiconductor device (e.g., second transistor) is less than about 60 nm. | 06-26-2014 |
20140264440 | V-SHAPED SIGE RECESS VOLUME TRIM FOR IMPROVED DEVICE PERFORMANCE AND LAYOUT DEPENDENCE - Some embodiments of the present disclosure relates to a method and a device to achieve a strained channel. A volume of a source or drain recess is controlled by a performing an etch of a substrate to produce a recess. An anisotropic etch stop layer is then formed by doping a bottom surface of the recess with a boron-containing dopant, which distorts the crystalline structure of the bottom surface. An anisotropic etch of the recess is then performed. The anisotropic etch stop layer resists anisotropic etching such that the recess comprises a substantially flat bottom surface after the anisotropic etch. The source or drain recess is then filled with a stress-inducing material to produce a strained channel. | 09-18-2014 |
20140264931 | Stress Tuning for Reducing Wafer Warpage - An integrated circuit structure includes a substrate, a plurality of low-k dielectric layers over the substrate, a first dielectric layer over the plurality of low-k dielectric layers, and a metal line in the first dielectric layer. A stress tuning dielectric layer is over the first dielectric layer, wherein the stress tuning dielectric layer includes a first opening and a second opening. The metal line extends into the first opening. The second opening has a bottom substantially level with a top surface of the first dielectric layer. A second dielectric layer is over the first dielectric layer. | 09-18-2014 |
20140295630 | SiGe SRAM BUTTED CONTACT RESISTANCE IMPROVEMENT - The present disclosure relates to a method for fabricating a butted a contact arrangement configured to couple two transistors, wherein an active region of a first transistor is coupled to a gate of a second transistor. The gate of the second transistor is formed from a gate material which comprises a dummy gate of the first transistor, and is configured to straddle a boundary between the active region of the first transistor and an isolation layer formed about the first transistor. The butted a contact arrangement results in a decreased contact resistance for the butted contact as compared to previous methods. | 10-02-2014 |
20150041857 | SEMICONDUCTOR STRUCTURE HAVING STRESSOR - A semiconductor structure includes a substrate, a shallow trench isolation (STI) structure embedded in the substrate, a stressor embedded in the substrate, and a conductive plug over and electrically coupled with the stressor. A same-material region is sandwiched by the STI structure and an entire sidewall of the stressor, and the same-material region is a continuous portion of the substrate. | 02-12-2015 |