Lim, Penang
Bok Sim Lim, Penang MY
Patent application number | Description | Published |
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20090321928 | FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY - In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed. | 12-31-2009 |
20100120199 | Stacked package-on-package semiconductor device and methods of fabricating thereof - Methods for fabricating a semiconductor package are provided, by coupling a plurality of first interconnects and a semiconductor die to a first surface of a substrate, and depositing a mold material on the first surface by compression molding to fully encapsulate the die and to partially encapsulate the first interconnects. | 05-13-2010 |
20120319276 | FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY - In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed. | 12-20-2012 |
20150076692 | FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY - In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed. | 03-19-2015 |
Cheng See Lim, Penang MY
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20160099021 | MULTI-SPEED PROGRAMMABLE BATCH SCRUBBER SYSTEM - Systems and methods for a multi-speed programmable batch scrubber are illustrated. The disclosed system includes a brush configured to scrub a disk at a plurality of speeds during cleaning of the disk, a combing system configured to support the disk during cleaning, a cleaning solution dispenser, and a first deionized water dispenser configured to dispense water on the brush during cleaning. The disk is cleaned in a plurality of predetermined cleaning steps, each step including predetermined parameter values such as the brush RPM, the step duration, the dispensing state of the cleaning solution dispenser, and the dispensing state of the deionized water dispenser. | 04-07-2016 |
Chong-Teik Lim, Penang MY
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20140103959 | Architectural Floorplan for a Structured ASIC Manufactured on a 28 NM CMOS Process Lithographic Node or Smaller - A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer. | 04-17-2014 |
Chooi Pei Lim, Penang MY
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20080258772 | CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES - Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location. | 10-23-2008 |
20140077839 | CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES - Clock, distribution circuitry for a structured ASIC device includes a deterministic portion, and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served, from that predetermined, location. | 03-20-2014 |
20140189456 | 3D BUILT-IN SELF-TEST SCHEME FOR 3D ASSEMBLY DEFECT DETECTION - Techniques and mechanisms are provided for an improved built in self-test (BIST) mechanism for 3D assembly defect detection. According to an embodiment of the present disclosure, the described mechanisms and techniques can function to detect defects in interconnects which vertically connect different layers of a 3D device, as well as to detect defects on a 2D layer of a 3D integrated circuit. Additionally, according to an embodiment of the present disclosure, techniques and mechanisms are provided for determining not only the presence of a defect in a given set of interfaces of an integrated circuit, but the particular interface at which a defect may exist. | 07-03-2014 |
David Chong Sook Lim, Penang MY
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20110078899 | MULTI-CHIP MODULE FOR BATTERY POWER CONTROL - A multi-chip module suitable for use in a battery protection circuit. The multi-chip module includes an integrated circuit chip, a first power transistor, a second power transistor, a first connection structure electrically coupling the integrated circuit chip to the first power transistor, a second connection structure electrically coupling the integrated circuit chip to the second power transistor, and a leadframe structure comprising a first lead, a second lead, a third lead and a fourth lead, wherein the integrated circuit chip, the first power transistor, and the second power transistor are mounted on the leadframe structure. A molding material covers at least part of the integrated circuit chip, the first power transistor, the second power transistor, the first connection structure, and the second connection structure. | 04-07-2011 |
Kevin Len Li Lim, Penang MY
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20150301630 | SELECTIVE FRAME RATE SWITCHING - A method for selectively switching a frame rate of a mouse includes: setting a plurality of acceleration thresholds respectively corresponding to a plurality of frame rates at which the mouse is operated; operating the mouse at a first frame rate of the plurality of frame rates; determining a velocity of the mouse according to a difference between a first frame captured by the mouse at the first frame rate and a second frame following the first frame captured by the mouse at the first frame rate; determining an acceleration of the mouse between the first captured frame and second captured frame according to the velocity of the first frame, the velocity of the second frame, and the frame rate; comparing the acceleration with the plurality of thresholds; and directly switching the frame rate of the mouse to a frame rate which corresponds to the determined threshold. | 10-22-2015 |
20160054816 | NAVIGATION DEVICE WITH ADJUSTABLE SAMPLE PERIOD - There is provided a navigation device including an image sensor and a processing unit. The image sensor is configured to capture reflected light of a work surface with a low-speed period to generate image frames, wherein the image sensor captures a pair of image frames in each low-speed period. The processing unit is configured to calculate acceleration according to the pair of image frames to accordingly identify whether to adjust the low-speed period to a high-speed period. | 02-25-2016 |
Khai Loke Lim, Penang MY
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20150245467 | APPARATUS AND METHOD OF MINIATURIZING THE SIZE OF A PRINTED CIRCUIT BOARD - A printed circuit board includes at least one plated-through hole via drilled into at least one of a first layer on a first side of the printed circuit board and a second layer on a second side of the printed circuit board. The printed circuit board also includes a core section laminated between the first layer and the second layer, wherein a length of the core section is shorter than a length of the first layer and a length of the second layer. The printed circuit board further includes an open slot configured to house a connection tab of an electronic product connected to the printed circuit board, wherein the open slot is formed adjacent to the core section and between sections of the first layer and the second layer that are longer than the core section. | 08-27-2015 |
Lay Cheng Jessie Lim, Penang MY
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20130002609 | OPTICAL NAVIGATION UTILIZING SPEED BASED ALGORITHM SELECTION - Embodiments of method and systems are disclosed. An embodiment of a method for optical navigation involves generating light at a light source, directing the light to a navigation surface, detecting light reflected from the navigation surface toward a sensor array, and generating movement information, which is indicative of movement of the navigation surface relative to the sensor array, in response to the detected light. Generating the movement information involves determining the speed of the movement, comparing the speed of the movement to a movement threshold, selecting a processing algorithm from a plurality of processing algorithms in response to the comparison, and processing the movement information according to the selected processing algorithm. In an embodiment, the processing algorithms include an adaptive navigation algorithm and a sensor resolution adjustment algorithm. | 01-03-2013 |
Lay Yeap Lim, Penang MY
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20080258272 | ETCHED LEADFRAME STRUCTURE - A leadframe structure is disclosed. The leadframe structure includes a first leadframe structure portion with a first thin portion and a first thick portion, where the first thin portion is defined in part by a first recess. It also includes a second leadframe structure portion with a second thin portion and a second thick portion, where the second thin portion is defined in part by a second recess. The first thin portion faces the second recess, and the second thin portion faces the first recess. | 10-23-2008 |
20100136750 | Etched Leadframe Structure - A leadframe structure is disclosed. The leadframe structure includes a first leadframe structure portion with a first thin portion and a first thick portion, where the first thin portion is defined in part by a first recess. It also includes a second leadframe structure portion with a second thin portion and a second thick portion, where the second thin portion is defined in part by a second recess. The first thin portion faces the second recess, and the second thin portion faces the first recess. | 06-03-2010 |
20100258925 | SEMICONDUCTOR DIE PACKAGE AND METHOD FOR MAKING THE SAME - Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die. | 10-14-2010 |
20120181675 | SEMICONDUCTOR DIE PACKAGE AND METHOD FOR MAKING THE SAME - Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die. | 07-19-2012 |
20140167238 | SEMICONDUCTOR DIE PACKAGE AND METHOD FOR MAKING THE SAME - Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die. | 06-19-2014 |
Seong Choon Lim, Penang MY
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20090032829 | LED Light Source with Increased Thermal Conductivity - A light source and method for making the same are disclosed. The light source includes a substrate, a plurality of dies and a transparent layer of encapsulant. The substrate includes an insulating layer having top and bottom surfaces, the top surface having a first metal patterned layer thereon, and the bottom surface having a second metal patterned layer thereon. The first metal patterned layer has a plurality of die mounting areas thereon, and the second metal patterned layer includes a first contact layer that underlies the die mounting area, the die mounting area and the first contact layer being connected by metal lined vias at each of the die mounting areas. The transparent encapsulant covers the plurality of dies and is bonded to the first metal patterned layer and the top surface of the insulating layer. | 02-05-2009 |
20090115926 | DISPLAY AND METHOD OF MAKING - Displays and methods of manufacturing displays are disclosed herein. An embodiment of a method of manufacturing a display comprises manufacturing a circuit board; forming a hole in a material; attaching the circuit board to the material, wherein the hole forms a cavity upon attachment of the circuit board to the material; and connecting a light source to the circuit board, the light source being located within the cavity. | 05-07-2009 |
20090117324 | ELECTRONIC SUBSTRATE HAVING CAVITIES AND METHOD OF MAKING - Electronic substrates having cavities located therein and methods of making the substrates are disclosed herein. An embodiment of a method of making the substrate comprises manufacturing a circuit board. An adhesive film is attached to the circuit board, wherein the adhesive film has a first side facing the circuit board and a second side located opposite the first side, and wherein the second side is adhesive. At least one cavity is formed in a material. The material is adhered to the second side of the adhesive film. | 05-07-2009 |
20120236531 | LOW HEIGHT DISPLAY USING MULTILAYER PRINTED CIRCUIT BOARD WITH A LAMINATED PANEL AS HOUSING - A multi-segment display is disclosed. Specifically, a low height LED-based display is disclosed that includes a number of segments. The segment construction may include a Printed Circuit Board (PCB) layer, a first substrate, and a second substrate that are laminated or otherwise connected to one another. The first and second substrates may include windows which allow light generated by a light source mounted on the PCB to exit the display and one or more of the windows may be filled with an encapsulant. | 09-20-2012 |
20130050982 | Method And Apparatus For A Light Source - A light-emitting device having a light source die mounted within an aperture is disclosed. The aperture is covered by a die attach pad on one side. The light source die is mounted on a die attach pad within the aperture. In one embodiment, an optical coupling layer can be formed within an aperture encapsulating a light source die. A wavelength converting layer can be formed on the substrate above the optical coupling layer. The wavelength converting layer can comprise a high density layer and a low density layer. The high density layer can comprise wavelength-converting material precipitated on one side of the wavelength converting layer. The low density layer can comprise the wavelength-converting material in particle form suspended within the wavelength converting layer. In one embodiment, the wavelength converting layer may be confined within the aperture of the substrate. | 02-28-2013 |
20140252399 | ELECTRONIC PACKAGING SUBSTRATE WITH ETCHING INDENTATION AS DIE ATTACHMENT ANCHOR AND METHOD OF MANUFACTURING THE SAME - An electronics package is disclosed. The electronics package is disclosed as including a substrate core, a metal layer established on top of the substrate core, the metal layer being etched so as to include a die attachment anchor and at least one gap that separates a die bonding pad from at least one of a trace and wire bonding pad, for example. The die attachment anchor is established on top of the die bonding pad and has a depth that does not extend all the way through the die bonding pad. | 09-11-2014 |
Sheou Hooi Lim, Penang MY
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20090025882 | DIE MOLDING FOR FLIP CHIP MOLDED MATRIX ARRAY PACKAGE USING UV CURABLE TAPE - An embodiment of the present invention is a technique to package flip chip molded matrix array package. An ultraviolet (UV) curable tape is laminated on die backside of a strip of array of flip chips. The UV curable tape has an adhesive strength. The strip of flip chip arrays is molded with a mold film. The molded strip of flip chip array is irradiated using UV radiation. In another embodiment, a double functional tape is mounted to backside of a wafer. The double functional tape includes a binding tape and a ultraviolet (UV) curable tape having an adhesive strength. The wafer is singulated into die. The die is attached to a substrate strip to form a strip of array of flip chips. The strip is molded with a mold film. The molded strip is irradiated using UV radiation. | 01-29-2009 |
Siew Ping Lim, Penang MY
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20150151088 | CATHETER ASSEMBLY WITH REUSABLE VALVE - A catheter assembly includes a catheter hub having an elastomeric septum that divides the catheter hub into a distal chamber and a proximal chamber. The septum also includes at least one slit that is closed and sealed when the septum is in an at-rest state. A septum activator is proximal the septum. When an external force pushes the activator against the septum, the activator deforms the septum so as to break the seal and create a flow path through the septum. A portion of the septum activator can be collapsible when subjected to the outside force. When the outside force is removed, the collapsible portion springs back to its at-rest shape, helping to pull the activator out of deforming engagement with the septum so that the septum can reseal. The activator can also be spring-biased away from engagement with the septum so that when the outside force is removed, the spring urges the activator out of engagement with the septum. With the activator removed, the septum slit can reseal. | 06-04-2015 |
Sih Fei Lim, Penang MY
Patent application number | Description | Published |
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20090321928 | FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY - In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed. | 12-31-2009 |
Sook Choo Lim, Penang MY
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20140145584 | HEMISPHERICAL REMOTER PHOSPHOR AND METHODS OF FORMING THE SAME - An illumination device is disclosed. The illumination device includes a light source and a remoter phosphor configured to alter the color of light emitted by the light source. The remoter phosphor is provided with a substantially hemispherical shape that substantially corresponds to a radiation pattern of the light source, which helps to reduce or eliminate the occurrence of the yellow ring phenomenon, among other things. Methods of manufacturing an illumination device are also disclosed. | 05-29-2014 |
Soon Chieh Lim, Penang MY
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20080263381 | DYNAMIC PHASE ALIGNMENT - A clock signal may be aligned with a data signal by delaying the signals relative to each other until an edge of one signal aligns with an edge of the other signal, and then causing an inversion of the clock signal. A further variation may limit the relative delay period to one-half clock cycle and may use a double inversion of the clock signal. | 10-23-2008 |
Su Ann Lim, Penang MY
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20080306703 | Automatic Placement of Measurement Gates - A method and apparatus is provided for setting time positions of measurement gates on a signal under test. Signal transition data is calculated by a processor for multiple signal transitions. Measurement gate start and end positions are set relative to the multiple signal transitions based on the received signal transition data. | 12-11-2008 |
20150177315 | DYNAMICALLY DETERMINING MEASUREMENT UNCERTAINTY (MU) OF MEASUREMENT DEVICES - A method is provided for dynamically determining measurement uncertainty (MU) of a measurement device for measuring a signal output by a device under test (DUT). The method includes storing characterized test data in a nonvolatile memory in the measurement device, the characterized test data being specific to the measurement device for a plurality of sources of uncertainty; receiving a parameter value of the DUT; measuring the signal output by the DUT and received by the measurement device; and calculating the measurement uncertainty of the measurement device for measuring the received signal using the stored characterized test data and the received parameter value of the DUT. | 06-25-2015 |
Szu Shing Lim, Penang MY
Patent application number | Description | Published |
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20090025882 | DIE MOLDING FOR FLIP CHIP MOLDED MATRIX ARRAY PACKAGE USING UV CURABLE TAPE - An embodiment of the present invention is a technique to package flip chip molded matrix array package. An ultraviolet (UV) curable tape is laminated on die backside of a strip of array of flip chips. The UV curable tape has an adhesive strength. The strip of flip chip arrays is molded with a mold film. The molded strip of flip chip array is irradiated using UV radiation. In another embodiment, a double functional tape is mounted to backside of a wafer. The double functional tape includes a binding tape and a ultraviolet (UV) curable tape having an adhesive strength. The wafer is singulated into die. The die is attached to a substrate strip to form a strip of array of flip chips. The strip is molded with a mold film. The molded strip is irradiated using UV radiation. | 01-29-2009 |
Tang Hyok Lim, Penang MY
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20150194168 | METHODS AND SYSTEMS OF ADJUSTING TILT USING MAGNETIC ERASE WIDTH FEEDBACK - Systems and methods are provided for manufacturing magneto-resistive devices utilized in magneto-resistive read elements by depositing a plurality of rows of magnetic transducers on a wafer. The wafer may then be diced/cut into bars of active device regions for incorporation into a magnetic recording head. Sampling of a subset of bars from one or more bar sections of the wafer may be processed to obtain feedback associated with magnetic erase width (MEW). An air bearing surface (ABS) tilt angle based on the MEW feedback may then be applied to the one or more bar sections of the water during subsequent processing to optimize the magnetic performance of each resulting magneto-resistive device. | 07-09-2015 |
Teng Hun Lim, Penang MY
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20080260262 | SYSTEM AND METHOD FOR OPTICALLY MEASURING A PARAMETER OF AN OBJECT - A system and method for optically measuring a parameter of an object uses a first segment of the object captured as a first frame of image data using a first imaging region of an image sensor array and a second segment of the object as a second frame of image data using a second imaging region of the image sensor array, which is larger than the first imaging region, to determine a displaced distance of the object relative to the image sensor array. | 10-23-2008 |
Timothy Kheng Kool Lim, Penang MY
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20130285882 | MECHANISM FOR FACILITATING A TABLET BLOCK OF A NUMBER OF TABLET COMPUTING DEVICES - A mechanism is described for facilitating a tablet block of a number of tablet computing devices. A method of embodiments of the invention includes monitoring a connection between a plurality of tablet computers. The monitoring includes detecting user inputs relating to one or more software applications running on the plurality of tablet computers, the user inputs being made via one or more of the plurality of tablet computers. The method may further include dynamically adjusting, in real-time, parameters of the connection based on the user inputs, and displaying changing contents of the one or more software applications, via a shared display screen provided by two or more of the plurality of tablet computers, based on the adjustment of the parameters. The contents are changed in response to an adjustment made to a parameter. | 10-31-2013 |
Wen Jenn Lim, Penang MY
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20150173663 | VASCULAR ACCESS BLOOD COLLECTION DEVICES AND RELATED METHODS - The present disclosure is directed to a needle assembly for drawing blood. The needle assembly can be a standalone or part of an over-the-needle medical device, such as an intravenous catheter. A blood collection device is attached directly or indirectly to the needle hub of the needle assembly and/or to a catheter hub, such as through a Y-site or adaptor connected to a tubing that is connected to the catheter hub. The needle is configured to access the vascular system to draw blood, which then passes to the blood collection device via the needle lumen, which has a tip having a discontinuity opening, an opening with a movable stem, or a shaft element with a lumen. | 06-25-2015 |
Wooi Kip Lim, Penang MY
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20150042566 | BIPOLAR JUNCTION TRANSISTOR PIXEL CIRCUIT, DRIVING METHOD THEREOF, AND IMAGE SENSOR - A bipolar junction transistor (BJT) pixel circuit, an image sensor and a driving method thereof are provided. The BJT pixel circuit includes a BJT, a photodetector, a feedback amplifier circuit, a shutter circuit, and a current generating unit. The photodetector generates a first base current to a base of the BJT responsive to a light incident on the photodetector. The feedback amplifier circuit is operative to increase an emitter voltage of the BJT according to the light intensity. The shutter circuit controls an exposure time of the photodetector according to a shutter signal. The current generating unit generates the second pulsed base current responsive to a trigger signal causing a base voltage of the BJT to drop while the feedback amplifier circuit operates to increase the emitter voltage of the BJT so as to build-up the base-emitter voltage to a predetermined voltage level when a light source turns on. | 02-12-2015 |