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Lim, Icheon-Si
Chang Sik Lim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100031938 | EXHAUST GAS RECIRCULATION VALVE FOR VEHICLE - The present invention relates to an exhaust gas recirculation (EGR) valve for a vehicle. The EGR valve includes a valve housing connected to an exhaust line for discharging exhaust gas therethrough, having a flow line with an inside area divided for taking and re-circulating a portion of the exhaust gas to a suction manifold, a driving unit on one side of the valve housing, and a valve unit mounted in a flow line of the valve housing for receiving driving force from the driving unit directly to control flows of the exhaust gas flowing through the flow line at the same time individually, thereby making stable control of the exhaust gas flowing through the EGR valve, preventing damage caused by the high temperature exhaust gas, and preventing the exhaust gas from leaking to an outside of the EGR valve. | 02-11-2010 |
| 20100124488 | ACTUATOR IN TURBOCHARGER OF VEHICLE AND METHOD FOR CONTROLLING THE SAME - Actuator in a turbocharger of a vehicle and method for controlling the same is disclosed, in which a position of a vane is followed up in controlling a PWM signal to be applied to a motor according to time for preventing an overcurrent from flowing to the motor connected to the vane of the turbocharger. | 05-20-2010 |
Hee Youl Lim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090170034 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises: forming a first photoresist pattern in a double patterning technology (DPT) for overcoming a resolution limit of an exposer; and forming a second photoresist pattern. The method further comprises forming a hard mask film and an anti-reflective film to prevent an intermixing phenomenon generated when the second photoresist pattern is formed. As a result, yield and reliability of the process can be improved. | 07-02-2009 |
Kwan-Yong Lim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090146246 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The present invention relates to a semiconductor device and a method of manufacture thereof, being capable of improving the high integration by increasing a cell region while securing the reliability of device and the process margin through forming a cell region and a core region with the stacking structure. | 06-11-2009 |
| 20090236656 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A semiconductor device having a substrate; a plurality of pillar structures, wherein each pillar structure includes an active pillar disposed over the substrate; a gate electrode surrounding an outer wall of the active pillar; an interlayer dielectric (ILD) layer insulating adjacent pillar structures; a gate contact penetrating the ILD layer and configured to connect to a sidewall of the gate electrode; and a word line connected to the gate contact. | 09-24-2009 |
Kyu Nam Lim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120005397 | SENSE AMPLIFIER AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - A sense amplifier is configured to transfer data on a first data I/O line to a second data I/O line or to transfer data on the second data I/O line to the first data I/O line. The first data I/O line is substantially continuously coupled to the second data I/O line during an active operation. | 01-05-2012 |
Sang Oh Lim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090285351 | COUNTER OF SEMICONDUCTOR DEVICE - The present invention relates to a unit counter block. According to an aspect of the present invention, the unit counter block includes a D-flipflop, a second MUX, and a first MUX. The-flipflop outputs first and second output signals in synchronism with a clock signal. The second MUX selects any one of external data and the second output signal of the D-flipflop in response to a data load signal and outputs a selected signal. The first MUX transfers any one of the first output signal of the D-flipflop and the output signal of the second MUX as an input signal of the D-flipflop in response to a counter enable signal or the data load signal. | 11-19-2009 |
| 20090290678 | COUNTING CIRCUIT AND ADDRESS COUNTER USING THE SAME - A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a 4-bit set terminal and outputs a signal according to a clock signal. The fifth FF is coupled to the output terminal of the fourth FF and is configured to output the output signal of the fourth FF synchronously with the clock signal. The logic operation unit logically combines the output signals of the second to fourth FFs and outputs first and second counting signals. | 11-26-2009 |
| 20100329032 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A nonvolatile memory device has memory cells coupled to bit lines and word lines and page buffers each coupled to one or more of the bit lines. Program and verification operations are performed on a first logical page from among first and second logical pages included in memory cells selected for a program operation. Data are loaded which will be programmed into the second logical page into first to third latches of a selected page buffer, coupled to the selected memory cells, from among the page buffers. A data setting operation is performed. The second logical page is programmed so that a distribution of threshold voltages of the selected memory cells has one of first to fourth threshold voltage distributions according to states of the data of the first to third latches and performing verification operations for the first to fourth threshold voltage distributions. | 12-30-2010 |
| 20110013741 | COUNTING CIRCUIT AND ADDRESS COUNTER USING THE SAME - A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a 4-bit set terminal and outputs a signal according to a clock signal. The fifth FF is coupled to the output terminal of the fourth FF and is configured to output the output signal of the fourth FF synchronously with the clock signal. The logic operation unit logically combines the output signals of the second to fourth FFs and outputs first and second counting signals. | 01-20-2011 |