Lim, Icheon-Si
Chang Sik Lim, Icheon-Si KR
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20100031938 | EXHAUST GAS RECIRCULATION VALVE FOR VEHICLE - The present invention relates to an exhaust gas recirculation (EGR) valve for a vehicle. The EGR valve includes a valve housing connected to an exhaust line for discharging exhaust gas therethrough, having a flow line with an inside area divided for taking and re-circulating a portion of the exhaust gas to a suction manifold, a driving unit on one side of the valve housing, and a valve unit mounted in a flow line of the valve housing for receiving driving force from the driving unit directly to control flows of the exhaust gas flowing through the flow line at the same time individually, thereby making stable control of the exhaust gas flowing through the EGR valve, preventing damage caused by the high temperature exhaust gas, and preventing the exhaust gas from leaking to an outside of the EGR valve. | 02-11-2010 |
20100124488 | ACTUATOR IN TURBOCHARGER OF VEHICLE AND METHOD FOR CONTROLLING THE SAME - Actuator in a turbocharger of a vehicle and method for controlling the same is disclosed, in which a position of a vane is followed up in controlling a PWM signal to be applied to a motor according to time for preventing an overcurrent from flowing to the motor connected to the vane of the turbocharger. | 05-20-2010 |
Gil Taek Lim, Icheon-Si KR
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20150242016 | Matrix Switching Type Touch Panel - Provided is a matrix switching type touch panel including a plurality of touch pads disposed in a visible area on a substrate in a dot matrix format, the touch pads spaced from one another, and a plurality of signal lines disposed in a space between the touch pads, each connecting a touch pad and a touch driving circuit of an invisible area. The panel comprises: unit electrodes made of a transparent electroconductive material and disposed within the visible area; touch pad areas each determined in an area corresponding to each touch pad; signal line areas each determined in an area corresponding to each signal line; and bridges electrically connecting the plurality of unit electrodes disposed in each touch pad area and each signal line area. The unit electrodes are arranged in a zigzag format with respect to a first axis parallel to the signal lines. | 08-27-2015 |
Hee Youl Lim, Icheon-Si KR
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20090170034 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises: forming a first photoresist pattern in a double patterning technology (DPT) for overcoming a resolution limit of an exposer; and forming a second photoresist pattern. The method further comprises forming a hard mask film and an anti-reflective film to prevent an intermixing phenomenon generated when the second photoresist pattern is formed. As a result, yield and reliability of the process can be improved. | 07-02-2009 |
Kwan-Yong Lim, Icheon-Si KR
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20090146246 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The present invention relates to a semiconductor device and a method of manufacture thereof, being capable of improving the high integration by increasing a cell region while securing the reliability of device and the process margin through forming a cell region and a core region with the stacking structure. | 06-11-2009 |
20090236656 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A semiconductor device having a substrate; a plurality of pillar structures, wherein each pillar structure includes an active pillar disposed over the substrate; a gate electrode surrounding an outer wall of the active pillar; an interlayer dielectric (ILD) layer insulating adjacent pillar structures; a gate contact penetrating the ILD layer and configured to connect to a sidewall of the gate electrode; and a word line connected to the gate contact. | 09-24-2009 |
20140252458 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A semiconductor device having a substrate; a plurality of pillar structures, wherein each pillar structure includes an active pillar disposed over the substrate; a gate electrode surrounding an outer wall of the active pillar; an interlayer dielectric (ILD) layer insulating adjacent pillar structures; a gate contact penetrating the ILD layer and configured to connect to a sidewall of the gate electrode; and a word line connected to the gate contact. | 09-11-2014 |
Kyu Nam Lim, Icheon-Si KR
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20120005397 | SENSE AMPLIFIER AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - A sense amplifier is configured to transfer data on a first data I/O line to a second data I/O line or to transfer data on the second data I/O line to the first data I/O line. The first data I/O line is substantially continuously coupled to the second data I/O line during an active operation. | 01-05-2012 |
20130155784 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes: a first sense amplification unit including first and second inverters configured to be driven to voltage levels of a power driving signal and a ground driving signal and forming a latch structure between a bit line and a bit line bar; and a second sense amplification unit including first and second transistors configured to be driven to the voltage level of the ground driving signal and forming a latch structure between the bit line and the bit line bar when an activated switching signal is applied, wherein a threshold voltage of the second sense amplification unit is set lower than that of the first sense amplification unit. | 06-20-2013 |
Sang O Lim, Icheon-Si KR
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20140063948 | NONVOLATILE MEMORY DEVICE AND DATA STORAGE DEVICE INCLUDING THE SAME - A nonvolatile memory device includes: a plurality of memory cells arranged in a region where word lines and bit lines intersect, a data read/write circuit including a plurality of latches configured to temporarily store data inputted from an external device, and configured to perform a program operation on the memory cells based on data stored in the latches, and a skip data control unit configured to determine whether data to be programmed into the memory cells are available, and to store program-inhibit data in a latch corresponding to a memory cell which is determined to not contain any data. | 03-06-2014 |
20140063956 | NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF - A nonvolatile memory device includes: a page buffer block including a plurality of cache latches configured to temporarily store data inputted to program memory cells, and configured to program the inputted data into the memory cells; and a column decoder configured to provide column select signals for selecting the cache latches to the cache latches according to a column address, wherein the column decoder activates column select signals for selecting a part of the cache latches at substantially the same time, while data are set up in the cache latches. | 03-06-2014 |
Sang Oh Lim, Icheon-Si KR
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20090285351 | COUNTER OF SEMICONDUCTOR DEVICE - The present invention relates to a unit counter block. According to an aspect of the present invention, the unit counter block includes a D-flipflop, a second MUX, and a first MUX. The-flipflop outputs first and second output signals in synchronism with a clock signal. The second MUX selects any one of external data and the second output signal of the D-flipflop in response to a data load signal and outputs a selected signal. The first MUX transfers any one of the first output signal of the D-flipflop and the output signal of the second MUX as an input signal of the D-flipflop in response to a counter enable signal or the data load signal. | 11-19-2009 |
20090290678 | COUNTING CIRCUIT AND ADDRESS COUNTER USING THE SAME - A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a 4-bit set terminal and outputs a signal according to a clock signal. The fifth FF is coupled to the output terminal of the fourth FF and is configured to output the output signal of the fourth FF synchronously with the clock signal. The logic operation unit logically combines the output signals of the second to fourth FFs and outputs first and second counting signals. | 11-26-2009 |
20100329032 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A nonvolatile memory device has memory cells coupled to bit lines and word lines and page buffers each coupled to one or more of the bit lines. Program and verification operations are performed on a first logical page from among first and second logical pages included in memory cells selected for a program operation. Data are loaded which will be programmed into the second logical page into first to third latches of a selected page buffer, coupled to the selected memory cells, from among the page buffers. A data setting operation is performed. The second logical page is programmed so that a distribution of threshold voltages of the selected memory cells has one of first to fourth threshold voltage distributions according to states of the data of the first to third latches and performing verification operations for the first to fourth threshold voltage distributions. | 12-30-2010 |
20110013741 | COUNTING CIRCUIT AND ADDRESS COUNTER USING THE SAME - A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a 4-bit set terminal and outputs a signal according to a clock signal. The fifth FF is coupled to the output terminal of the fourth FF and is configured to output the output signal of the fourth FF synchronously with the clock signal. The logic operation unit logically combines the output signals of the second to fourth FFs and outputs first and second counting signals. | 01-20-2011 |
20120008424 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes a plurality of latches for storing data, a set/reset circuit for transferring data, stored in a selected latch of the latches, to a common node, a transmission circuit for transferring the data of the common node to a first sense node, a bit line transmission circuit for transferring the data of the first sense node to a bit line, a sense circuit for transferring the data of the first sense node to a second sense node, and a discharge circuit for changing a voltage level of the common node based on the data of the second sense node. | 01-12-2012 |
20120008733 | COUNTING CIRCUIT AND ADDRESS COUNTER USING THE SAME - A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a | 01-12-2012 |
20120314518 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a count clock generation unit for generating a count clock in response to a clock signal and a dummy count clock, a column address generation unit for generating a column address in response to the count clock, and a Y decoder for sending data, stored in a page buffer unit, to a data line in response to the column address. | 12-13-2012 |
20140029363 | FAIL ADDRESS DETECTOR,SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME AND METHOD OF DETECTING FAIL ADDRESS - A fail address detector includes cam latch groups configured to store fail addresses and a comparing section connected to the cam latch groups in common and configured to detect whether or not a fail address corresponding to a comparison address exists among the fail addresses received from the cam latch groups. The cam latch groups share the comparing section in time division. | 01-30-2014 |
Soo Bin Lim, Icheon-Si KR
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20150206867 | SEMICONDUCTOR APPARATUS HAVING PAD AND BUMP - A semiconductor apparatus may include a semiconductor chip, and the semiconductor chip may include a first pad, a second pad, and a bump. The first pad may be configured to receive a signal from an external device, and the second pad may include first and second metal layers electrically isolated from each other. The bump may be stacked over the second pad, and may be configured to receive a signal from a controller chip. | 07-23-2015 |
Yu Ri Lim, Icheon-Si KR
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20130318407 | TEST MODE SIGNAL GENERATION CIRCUIT - A test mode signal generation circuit includes a pre-decoder block configured to output first and second control signals and test address signals in response to first and second address signals, and a signal generation block configured to decode the test address signals in response to the first control signal and generate first and second test mode group signals each including a plurality of test mode signals. | 11-28-2013 |
20150187438 | SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD USING THE SAME - A semiconductor memory apparatus includes first data outputted from a first data storage region; second data outputted from a second data storage region; a data comparison block configured to perform a comparison to determine whether the first data and the second data are the same, and generate a comparison result signal; a timing control block configured to latch the comparison result signal in response to a clock and a latency signal, and output a comparison signal; and a data output block configured to receive a test signal and invert the first data in response to the comparison signal and output data. | 07-02-2015 |