Patent application number | Description | Published |
20100110230 | BUFFER MEMORY FOR ROTATING IMAGE, IMAGE CAPTURE DEVICE AND DISPLAY DEVICE INCLUDING THE SAME - A buffer memory for rotating an image. The buffer memory is address-mapped in three dimensions including a first axis, a second axis, and a third axis, that are orthogonal to one another. Data may be sequentially accessed (read from or written to) the buffer memory in each of the direction of the first axis, the direction of the second axis, and the direction of the third direction. Second data may written to a given plane of the buffer memory at the same time that first data is read from the same plane of the buffer memory. | 05-06-2010 |
20100115142 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE - A method of operating a semiconductor memory device includes receiving a timeout index signal corresponding to a master of the first master group based on a residual capacity of a data buffer of the first master, setting a first timeout value in response to the timeout index signal, and changing an execution order of commands stored in a queue of the semiconductor memory device based on a result of counting the first timeout value and counting a second timeout value corresponding to a master of the second master group. | 05-06-2010 |
20100115320 | MOBILE SYSTEM ON CHIP (SoC) AND A MOBILE TERMINAL INCLUDING THE MOBILE SoC - A mobile System on Chip (SoC) including a central processing unit (CPU) and an audio out module that includes a buffer and an audio interface. A power mode of the audio out module is controlled separately from a power mode of the mobile SoC so that the audio out module operates when the mobile SoC is in a power down mode. | 05-06-2010 |
20100207672 | SYSTEM TIMER AND A MOBILE SYSTEM INCLUDING THE SAME - A system timer including a divider unit configured to fractionally divide a first clock signal and output a second clock signal having an asymmetric duty ratio and an interrupt generation unit configured to count a cycle of the second clock signal and output an interrupt signal according to the count. | 08-19-2010 |
20120191991 | MOBILE SYSTEM ON CHIP (SoC) AND A MOBILE TERMINAL INCLUDING THE MOBILE SoC - A mobile System on Chip (SoC) including a central processing unit (CPU) and an audio out module that includes a buffer and an audio interface. A power mode of the audio out module is controlled separately from a power mode of the mobile SoC so that the audio out module operates when the mobile SoC is in a power down mode. | 07-26-2012 |
Patent application number | Description | Published |
20100142291 | Mobile system on chip (SoC) and mobile terminal using the mobile SoC, and method for refreshing a memory in the mobile SoC - A mobile System on Chip (SoC) comprises a microprocessor and a first memory controller configured to control a refresh of a first memory. A temperature sensor detects a temperature in the first memory. When first temperature information received from the temperature sensor indicates that the detected temperature deviates from a predetermined temperature range, the first memory controller controls the first memory so as not to perform a self refresh. When second temperature information received from the temperature sensor indicates that the detected temperature is in the predetermined temperature range, the first memory controller outputs a self refresh command to the first memory. | 06-10-2010 |
20100165773 | SEMICONDUCTOR MEMORY DEVICE FOR SELF REFRESH AND MEMORY SYSTEM HAVING THE SAME - A semiconductor memory device includes a memory core unit including a memory cell array including a plurality of memory cells and a sense amplifier to sense and amplify data of the plurality of memory cells, and a self refresh control unit to apply at least one first core voltage to the memory core unit and to control a self refresh operation to be performed at every first self refresh cycle, in a first self refresh mode, and to apply at least one second core voltage to the memory core unit and to control the self refresh operation to be performed at every second self refresh cycle, in a second self refresh mode. In the semiconductor memory, a level of the at least one first core voltage is higher than that of a corresponding one of the at least one second core voltage, and the first self refresh cycle is shorter than the second self refresh cycle. | 07-01-2010 |
20100172193 | Semiconductor memory device and method of reducing consumption of standby current therein - A semiconductor memory device comprises a memory array including a plurality of bit lines and a plurality of dummy bit lines, a bias application unit configured to supply bias voltages having a plurality of voltage levels to the plurality of dummy bit lines, a standby current measuring unit configured to measure a value of at least one of standby currents between at least one of the plurality of bit lines and at least one of the plurality of dummy bit lines. Each of the standby currents is generated by each of the bias voltages applied by the bias application unit. | 07-08-2010 |