Patent application number | Description | Published |
20110115920 | MULTI-STATE TARGET TRACKING MEHTOD AND SYSTEM - A multi-state target tracking method and a multi-state target tracking system are provided. The method detects a crowd density of a plurality of images in a video stream and compares the detected crowd density with a threshold when receiving the video stream, so as to determine a tracking mode used for detecting the targets in the images. When the detected crowd density is less than the threshold, a background model is used to track the targets in the images. When the detected crowd density is greater than or equal to the threshold, a none-background model is used to track the targets in the images. | 05-19-2011 |
20110116682 | OBJECT DETECTION METHOD AND SYSTEM - An object detection method and an object detection system, suitable for detecting moving object information of a video stream having a plurality of images, are provided. The method performs a moving object foreground detection on each of the images, so as to obtain a first foreground detection image comprising a plurality of moving objects. The method also performs a texture object foreground detection on each of the images, so as to obtain a second foreground detection image comprising a plurality of texture objects. The moving objects in the first foreground detection image and the texture objects in the second foreground detection image are selected and filtered, and then the remaining moving objects or texture objects after the filtering are output as real moving object information. | 05-19-2011 |
20130155228 | MOVING OBJECT DETECTION METHOD AND APPARATUS BASED ON COMPRESSED DOMAIN - A moving object detection method and a moving object detection apparatus based on a compressed domain are disclosed. In the method, compressed video data and pixel video data are received. Moving object information in the first compressed video data is detected and integrated into the pixel video data. The pixel video data containing the moving object information is output. | 06-20-2013 |
Patent application number | Description | Published |
20120234683 | ELECTROCHEMICAL PLATING - A method for electrochemical plating includes providing a wafer for an electrochemical plating (ECP) process, determining a wafer electrical property affecting the ECP process, adjusting a plating current or voltage applied in the ECP process based on the determined wafer electrical property, and electroplating the wafer with the adjusted plating current or voltage. A controller for controlling a power supply, and a system for electrochemical plating are also disclosed. | 09-20-2012 |
20130320539 | Method and Apparatus for Back End of Line Semiconductor Device Processing - Methods and apparatus are disclosed for the back end of line process for fabrication of integrated circuits (ICs). The inter-metal dielectric (IMD) layer between two metal layers may comprise an etching stop layer over a metal layer, a low-k dielectric layer over the etching stop layer, a dielectric hard mask layer over the low-k dielectric layer, an nitrogen free anti-reflection layer (NFARL) over the dielectric hard mask layer, and a metal-hard-mask (MHM) layer of a thickness in a range from about 180 Å to about 360 Å over the NFARL. The MHM layer thickness is optimized at the range from about 180 Å to about 360 Å to reduce the Cu pits while avoiding the photo overlay shifting issue. | 12-05-2013 |
20140117547 | BARRIER LAYER FOR COPPER INTERCONNECT - A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming a metal-containing layer in the dielectric layer, forming a barrier layer overlying the metal-containing layer, and performing a thermal process to form a metal oxide layer underlying the conductive layer. The metal oxide layer is a barrier layer formed at the boundary between the dielectric layer and the metal-containing layer. | 05-01-2014 |
20140191402 | Barrier Layer for Copper Interconnect - A device including a dielectric layer overlying a substrate, a conductive line with a sidewall in the dielectric layer, a Ta layer adjoining the sidewall of the conductive line, and a metal oxide formed between the Ta layer and the dielectric layer. | 07-10-2014 |
20150044867 | Barrier Layer for Copper Interconnect - A device and a method of forming the device is provided. The device includes a dielectric layer overlying a substrate, a conductive line with a sidewall in the dielectric layer, a Ta layer adjoining the sidewall of the conductive line, and a metal oxide formed between the Ta layer and the dielectric layer. | 02-12-2015 |
Patent application number | Description | Published |
20090167018 | Coupling assembly with a core unit therein - A coupling assembly includes a female unit and a male unit which is removably connected with the female unit. A valve unit is located in the female unit and includes a core with two flexible disks on two ends thereof. A flange extends radially outward from a lower end of the core and is rested on a support frame in the female unit. The core extends through a through hole in a lower end of sleeve in the female unit. A plurality of paths are defined through the lower end of the sleeve so that by shifting the core to let either of two flexible disks to seal the paths in one direction, the direction of fluid flow can be controlled. The movement of the core is made by moving the sleeve. | 07-02-2009 |
20090314789 | Mouth piece assembly - A mouth piece assembly includes a mouth piece unit having a pivot which is pivotably connected to a first connector so that the mouth piece unit is pivotable about an axis of the pivot relative to the first connector. The first connector is pivotably inserted into a second connector so that the first connector is pivotable about an axis of the second connector. The two respective axes are perpendicular to each other. A locking key is connected to the second connector and engaged with the first connector inserted into the second connector. The mouth piece unit can be pivoted in two different directions and the volume of liquid sucked from the container is not changed. | 12-24-2009 |
20090314909 | Connection device for connecting box to bicycle handlebar - A connection device includes a fixing board connected to a rear end of a box, a main part and a clamping unit. A locking member extends through the front board and a spring contacts against between the locking member and a rear board. Two push rods extend from a lower end of a button and slidably connected with inclined surfaces of the locking member. A safety member is connected to a mediate portion of the button and includes a spring plate which contacts against the button. The clamping unit includes two collars which are securely engaged with the adjustment plate. A bridge member is connected between the two toothed members and supported on a lower side of a handlebar stem. The clamp pieces is located at an inner side of the toothed members and mounted on a handlebar. | 12-24-2009 |
20100012221 | Water refilling assembly for hydro pack - A hydro pack includes a water bag with a handle on a top end thereof and a outlet frame is located on a lower end of the water bag. A connection member is connected with the outlet frame and a hose with semi-circular cross section is connected to the connection member. The other end of the hose is connected with a female unit. A universal mouth piece assembly, a bottle water connector, a faucet connector, a filtering unit and a suction unit each have a male part which is optionally connected with the female unit so as to conveniently and quick refill clean water in the water bag. | 01-21-2010 |
20100040307 | Sealing handle for outdoor use water bag - A sealing handle for a water bag includes a clamp slot defined in an underside thereof and the clamp slot has a guide opening in one end and a closed end on the other end. A sealing rod is clamped in the clamp slot and has a first axial ridge extending radially from an outer surface of the sealing rod. The end having the opening of the water bag is inserted in the clamp slot and goes around the sealing rod. The sealing rod includes two second axial ridges, two third axial ridges and two fourth axial ridges extending radially therefrom and located at different heights of the sealing rod. The second, third or fourth ridges contact two respective insides of the two parts defined by of the clamp slot and the bag so as to seal the opening regardless of the thickness of the water bag. | 02-18-2010 |
20100084411 | Water storage unit with dual bladders - A water storage unit includes an outer bag with an inlet defined in a top end thereof and an inner bag is received in the outer bag. A coolant bag is received in the inner bag and has coolant received therein. An outlet part is connected to the lower end of the outer bag and connected with a hose so that the user can suck the water in the outer bag. The water is cooled by the coolant in the coolant bag which is located at the lower end of the outer bag. A handle has a clamp slot with which a sealing rod is securely engaged. The inlet of the outer bag can be sealed by the cooperation of the clamp slot of the handle and the sealing rod. | 04-08-2010 |
20110284105 | VALVE SET - A valve set includes a valve body which includes a central hole and multiple passages are located around the central hole. A tubular portion extends from the valve body a flexible plate has an insertion inserted into the central hole of the valve body and the flexible plate seals the passages from an underside of the valve body. A core member is securely engaged with the tubular portion has an inlet tube. Multiple releasing probes extend from an underside thereof. A spring is mounted to the inlet tube and biased between a shoulder on the inlet tube and an inner surface of the valve body. A bottom cap is connected to the underside of the valve body. Air is introduced into the valve set via the inlet tube and released by pushing the core member and the releasing probes push the flexible plate away from the passages. | 11-24-2011 |
Patent application number | Description | Published |
20100155546 | SUPPORT STAND WITH INTERMEDIATE CONNECTING ASSEMBLY - An exemplary support stand includes a base, a connecting assembly, a support bracket, two first hinge assemblies, and two second hinge assemblies. The connecting assembly is arranged between the base and the support bracket. The first hinge assemblies rotatably connect the connecting assembly to the base. The second hinge assemblies rotatably connect the connecting assembly to the support bracket. The connecting assembly comprises a connecting bracket and a connecting plate partially received in the connecting bracket. The connecting plate, the connecting bracket, one first hinge assembly, and one second hinge assembly form a quadrangle. | 06-24-2010 |
20110096541 | BACKLIT TOUCH BUTTON ASSEMBLY - A backlit touch button assembly includes a circuit board, one or more light sources, a reflecting plate, and a marked strip. The light sources are positioned on the circuit board. The reflecting plate and the marked strip are attached to opposite sides of the circuit board. The reflecting plate defines one or more optical grooves receiving the light sources. Each optical groove has a reflecting portion. The circuit board defines one or more through holes adjacent to the light sources and corresponding to the reflecting portion of the optical grooves. The reflecting portion has a first reflecting surface, a second reflecting surface, and a third reflecting surface. The first reflecting surface and the third reflecting surface meet the second reflecting surface, respectively, at an angle. | 04-28-2011 |
Patent application number | Description | Published |
20080286898 | Material composition having core-shell microstructure used for varistor - A material composition having a core-shell microstructure suitable for manufacturing a varistor having outstanding electrical properties, the core-shell microstructure of the material composition at least comprising a cored-structure made of a conductive or semi-conductive material and a shelled-structure made from a glass material to wrap the cored-structure, and electrical properties of the varistors during low temperature of sintering process can be decided and designated by precisely controlling the size of the grain of the cored-structure and the thickness and insulation resistance of the insulating layer of the shelled-structure of material composition. | 11-20-2008 |
20100117271 | Process for producing zinc oxide varistor - A process for producing zinc oxide varistors is to perform the doping of zinc oxide and the sintering of zinc oxide grains with a high-impedance sintering material through two independent procedures, so that the doped zinc oxide and the high-impedance sintering material are well mixed in a predetermined ratio and then used to make the zinc oxide varistors through conventional technology by low-temperature sintering (lower than 900° C.); the resultant zinc oxide varistors may use pure silver as inner electrode and particularly possess one or more of varistor properties, thermistor properties, capacitor properties, inductor properties, piezoelectricity and magnetism. | 05-13-2010 |
20110276488 | METHOD OF CREDIT CARD TRANSACTION AUTHORIZATION USING VOIPOW TECHNIQUE - A method of credit card transaction authorization using VoIPoW phone is provided to efficiently and economically perform authorization by both recognizing a credit card and identifying a holder of the credit card, which key feature of the method is that the VoIPoW phone is independent of environmental barriers, time as well as space limitations and communication costs, and a real-time intercommunication between a card holder and a relevant card issuing bank through VoIPoW phone can be performed to effectively preclude credit card fraud. | 11-10-2011 |
20120057265 | ZINC-OXIDE SURGE ARRESTER FOR HIGH-TEMPERATURE OPERATION - A ZnO surge arrester for high-temperature operation is characterized in that a grain boundary layer between ZnO grains thereof contains a BaTiO | 03-08-2012 |
20120135563 | PROCESS FOR PRODUCING MULTILAYER CHIP ZINC OXIDE VARISTOR CONTAINING PURE SILVER INTERNAL ELECTRODES AND FIRING AT ULTRALOW TEMPERATURE - A low-temperature firing process is available for cost saving to produce a multilayer chip ZnO varistor containing pure silver (Ag) formed as internal electrodes and calcined at ultralow firing temperature of 850-900° C., which process comprises:
| 05-31-2012 |
20120208040 | STRUCTURE OF MULTILAYER CERAMIC DEVICE - A multilayer ceramic device comprises a laminated ceramic body having opposite end surfaces, a pair of conductive electrodes each respectively attached to one end surface of the laminated ceramic body and a plurality of alternately staggered internal electrodes within the laminated ceramic body configured in an alternating manner and each electrically connected to the corresponding conductive electrodes respectively; each conductive electrodes of the multilayer ceramic device is further covered with a solder paste layer so that the multilayer ceramic device is thus made without any plating step and no need of treating waste liquid nickel or waste liquid tin as well as no problem of environmental pollution caused by plating solution, thereby lowering manufacturing costs and reducing processing time. | 08-16-2012 |
20130011963 | PROCESS FOR PRODUCING ZINC OXIDE VARISTOR - A process for producing zinc oxide varistors possessed a property of breakdown voltage (V1mA) ranging from 230 to 1,730 V/mm is to perform the doping of zinc oxide and the sintering of zinc oxide grains with a high-impedance sintered powder through two independent procedures, so that the doped zinc oxide and the high-impedance sintered powder are well mixed in a predetermined ratio and then used to make the zinc oxide varistors through conventional technology by low-temperature sintering (lower than 900° C.); the resultant zinc oxide varistors may use pure silver as inner electrode and particularly possess breakdown voltage ranging from 230 to 1,730 V/mm. | 01-10-2013 |
20130133183 | PROCESS FOR PRODUCING ZINC OXIDE VARISTOR HAVING HIGH POTENTIAL GRADIENT AND HIGH NON-LINEARITY COEFFICIENT - A process for producing zinc oxide varistor is disclosed to allow that one step of having zinc oxide grains doped with non-equivalent ions and sufficiently semiconductorized and the other one step of preparing sintered powders having property of high-impedance are prepared by two separate procedures respectively, resulted in that the zinc oxide varistor produced by the process features both a high potential gradient and a high non-linearity coefficient; and more particularly the disclosed process is suited for producing a specific zinc oxide varistor whose potential gradient ranges from 2,000 to 9000 V/mm as well as non-linearity coefficient (α) ranges from 21.5 to 55. | 05-30-2013 |
Patent application number | Description | Published |
20100183092 | ADAPTIVE DIFFERENTIAL PULSE CODE MODULATION/DEMODULATION SYSTEM AND METHOD - An adaptive differential pulse-code modulation-demodulation system and method thereof is provided. The method includes steps of modulating an analog audio input signal into a data packet, including a plurality of digital data through adaptive differential pulse-code modulation, an initial value and a scale factor associated with the digital data, to be sent to the communication network, and demodulating the data packet according to the digital data, the initial value and the scale factor, thereby reconstructing the data packet to an analog audio output signal. | 07-22-2010 |
20100296577 | Inverse Quantization Processing Method and Device - An inverse quantization processing method and device thereof is provided. The inverse quantization processing device includes a determining unit, a bit reduction unit, a frequency/time-domain conversion unit and a bit addition unit. The inverse quantization processing method includes receiving a plurality of quantized frequency-domain data; performing a bit reduction on a current quantized frequency domain data according to an adjusting factor, such that a bit-reduced quantized frequency-domain data is generated when an accumulated count value of a plurality of valid bit numbers of the plurality of quantized frequency-domain data greater than a first threshold reaches a second threshold; performing a frequency/time domain conversion on the bit-reduced quantized frequency-domain data to obtain a bit-reduced time-domain PCM data; and performing a bit addition on the bit-reduced time-domain PCM data according to the adjusting factor, so as to obtain a time-domain PCM data. | 11-25-2010 |
20100310081 | Multi-channel Audio Signal Decoding Method and Device - A multi-channel audio signal decoding method and device is provided. The multi-channel audio signal decoding method includes receiving a first multi-channel audio signal; performing a first decoding procedure on the first multi-channel audio signal to generate a second multi-channel audio signal; performing a second decoding procedure on a first single-channel audio data of the second multi-channel audio signal to generate a first single-channel audio signal when the first single-channel audio data belongs to a first classification; and performing a third decoding procedure on a second single-channel audio data of the second multi-channel audio signal to generate a second single-channel audio signal when the second single-channel audio data belongs to a second classification. The number of instructions of the third decoding procedure is less than that of the second decoding procedure. | 12-09-2010 |
20110022399 | Auto Detection Method for Frame Header - A method for auto-detecting a frame header is provided. By searching and comparing content of input frames and predetermined sync words, decoding efficiency is increased and the probability of incurring program errors is reduced. Once decoding errors occur, an auto-recovery mechanism soon recovers the audio decoding system operation. | 01-27-2011 |
20140219473 | SIGNAL FILTERING APPARATUS AND SIGNAL FILTERING METHOD - The present invention provides a signal filtering apparatus, which comprises a control circuit and a filter for receiving a transmitted input signal and generating an output signal. The filter comprises multiple filter taps for processing the transmitted input signal corresponding to different timings with different filter coefficients, respectively, to generate the output signal. The control circuit is configured to shrink at least part of the low-frequency-response filter taps having filter coefficients less than a predetermined value. | 08-07-2014 |
Patent application number | Description | Published |
20080217739 | Semiconductor packaging substrate structure with capacitor embedded therein - The present invention relates to a semiconductor packaging substrate structure with a capacitor embedded therein, which includes an inner circuit board, a patterned buffer layer, a high dielectric material layer, and a patterned metal layer. The buffer layer is disposed on at least one surface of the inner circuit board to expose the inner electrode layer of the internal board. The high dielectric material layer is located on the buffer layer and the inner electrode layer. The metal layer is placed on the high dielectric material layer including an outer circuit layer capable of electrical connection to the inner circuit layer, and an outer electrode layer corresponding to the inner electrode layer to form a capacitor. Owing to the assistance of the buffer layer, the structure can enhance the transmission and the quality of the products. | 09-11-2008 |
20080308309 | Structure of packaging substrate having capacitor embedded therein and method for fabricating the same - A structure of a packaging substrate having capacitors embedded therein is disclosed. The structure comprises a core substrate, a dielectric layer, and an outer circuit layer. The core substrate comprises an inner circuit layer. The dielectric layer is disposed at both sides of the core substrate, having first conductive vias each connecting to the inner circuit layer through a piece of outer electrode plate, a piece of high dielectric material layer, a piece of inner electrode plate, and a piece of adhesive layer, in sequence. The outer circuit layer is disposed on the surface of each of the dielectric layers. Herein, the capacitor is composed of a piece of the outer electrode plate, the high dielectric material layer and the inner electrode plate. The invention further comprises a method for manufacturing the same. This can achieve low costs, avoid the formation of voids, and reduce parasitic capacitance. | 12-18-2008 |
20120292089 | CIRCUIT BOARD STRUCTURE WITH CAPACITORS EMBEDDED THEREIN AND METHOD FOR FABRICATING THE SAME - A circuit board structure with capacitors embedded therein and a method for fabricating the same are disclosed. The structure comprises at least two core layers individually comprising a dielectric layer having two opposite surfaces, circuit layers disposed on the outsides of the two opposite surfaces of the dielectric layer, and at least two capacitors embedded respectively on the insides of the two opposite surfaces of the dielectric layer and individually electrically connecting with the circuit layer at the same side; at least one adhesive layer disposed between the core layers to combine the core layers as a core structure; and at least one conductive through hole penetrating the core layers and the adhesive layer, and electrically connecting the circuit layers of the core layers. Accordingly, the present invention can improve the flexibility of circuit layout, and realize parallel connection between the capacitors to provide more capacitance. | 11-22-2012 |
Patent application number | Description | Published |
20120149219 | SIGNAL TRANSMISSION DEVICE - A signal transmission device is provided. The signal transmission device comprises a linked unit, a data connector, a sliding block, a link and a lock block. The linked unit includes a first shaft, a second shaft, a third shaft, a first elastomer and a second elastomer. The data connector rotates and expands according to the first shaft and the first elastomer. During the retraction of the data connector, the data connector pushes the sliding block. Then the sliding block moves against the lock block so that the lock block rotates according to the second shaft. The lock block rotates to lock and secure the data connector by the lock piece, while a cam of the link moves to a secure location along an incline plane of a track of the sliding block. | 06-14-2012 |
20120149220 | SIGNAL TRANSMISSION MODULE - A signal transmission module is provided. The signal transmission module includes an electrical connector, a linked unit, a data connector, a sliding block, a link and a lock block. The data connector rotates and expands according to a first shaft and a first elastomer of the linked unit, and electrically connects to the electrical connector. During retraction of the data connector, the data connector pushes the sliding block. Then the sliding block moves against the lock block so that the lock block rotates. The lock block rotates to lock and secure the data connector by the lock piece, while a cam of the link moves to a secure location along an incline plane of a track of the sliding block. | 06-14-2012 |
Patent application number | Description | Published |
20090045452 | Structure and Method of Sub-Gate NAND Memory with Bandgap Engineered SONOS Devices - A bandgap engineered SONOS device structure for design with various AND architectures. The BE-SONOS device structure comprises a spacer oxide disposed between a control gate overlaying an oxide-nitride-oxide-nitride-oxide stack and a sub-gate overlaying a gate oxide. In one example, a BE-SONOS sub-gate-AND array architecture has multiple strings of SONONOS devices with sub-gate lines and diffusion bit lines. In another example, a BE-SONOS sub-gate-AND architecture has multiple strings of SONONOS devices with sub-gate lines, relying on the sub-gate lines that create inversions to substitute for the diffusion bit lines. | 02-19-2009 |
20100044803 | SEALING STRUCTURE FOR HIGH-K METAL GATE AND METHOD OF MAKING - The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer. | 02-25-2010 |
20100291751 | METHOD FOR FABRICATING AN ISOLATION STRUCTURE - The invention relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure made having almost no void. An exemplary method for fabricating an isolation structure, comprising: providing a substrate; forming a trench in the substrate; partially filling the trench with a first silicon oxide; exposing a surface of the first silicon oxide to a vapor mixture comprising NH3 and a fluorine-containing compound; heating the substrate to a temperature between 100° C. to 200° C.; and filling the trench with a second silicon oxide, whereby the isolation structure made has almost no void. | 11-18-2010 |
20120225529 | SEALING STRUCTURE FOR HIGH-K METAL GATE AND METHOD OF MAKING - The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer. | 09-06-2012 |
20130171803 | METHOD FOR FABRICATING AN ISOLATION STRUCTURE - A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide. | 07-04-2013 |
20130330906 | METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION - A method of fabricating a semiconductor IC is disclosed. The method includes receiving a device. The device includes a semiconductor substrate, a plurality of fins and trenches between fins in the semiconductor substrate. The method also includes filling the trenches with a dielectric material to form shallow trench isolations (STI), applying a low-thermal-budget annealing to the dielectric material, and applying a wet-treatment to the dielectric material. | 12-12-2013 |
Patent application number | Description | Published |
20110316846 | TOUCH PANEL FOR DISPLAYING STEREOSCOPIC IMAGE - A touch panel for displaying stereoscopic image includes a substrate, a plurality of first sensing strings, second sensing strings and third sensing strings. Each of the first sensing strings includes a plurality of sensing pads respectively having a first retarder region. The second sensing strings are parallel with the first sensing strings, and each of the second sensing strings includes a plurality of second sensing pads respectively having a second retarder region. The third sensing strings are perpendicular to the first sensing strings and the second sensing strings, and each of the third sensing strings includes a plurality of third sensing pads and fourth sensing pads arranged alternately. Each of the third sensing pads includes the first retarder region and each of the fourth sensing pads includes the second retarder region. | 12-29-2011 |
20120081652 | LIQUID CRYSTAL ALIGNMENT PROCESS - A liquid crystal alignment process comprises steps of: providing a first substrate and a second substrate to form a liquid crystal accommodating space therebetween; pouring a liquid crystal composition into the liquid crystal accommodating space, the liquid crystal composition comprising liquid crystal molecules, a first monomer material, and a second monomer material; applying a voltage difference to the first and second substrates for arranging the liquid crystal molecules at a pre-tilt angle; and exposing the liquid crystal composition by mixed multi-spectrum rays for polymerizing the first monomer material and the second monomer material to form at least one type of liquid crystal alignment polymer on opposite surfaces of the first and second substrates. The liquid crystal alignment process is capable of improving the efficiency of exposure procedure, reducing time to manufacture products, and is capable of solving the problems of high costs and waste pollution. | 04-05-2012 |
20120182517 | METHOD FOR MANUFACTURING MICRO RETARDER WITHOUT ALIGNMENT LAYER - A method for manufacturing a micro retarder without alignment layer includes providing a substrate, forming a liquid crystal (LC) layer having a plurality of LC molecules, a plurality of photosensitive monomers and a plurality of thermal reactive monomers, performing a first exposure treatment to form at least a first patterned retarder in the LC layer, performing a second exposure treatment to form at least a second patterned retarder in the LC layer, and performing a baking treatment to form the micro retarder without alignment layer. | 07-19-2012 |
20120257146 | LIQUID CRYSTAL MIXTURE AND LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display panel includes an active component array substrate, a color filter substrate, a pair of alignment films and a liquid crystal layer. The active component array substrate has a first plane. The color filter substrate has a second plane opposite to the first plane. The alignment films are disposed on the first plane and the second plane respectively. The liquid crystal layer is disposed between the alignment films and includes a liquid crystal material, a photo initiator and a first monomer material. The liquid crystal material, the photo initiator and the first monomer material are mixed together. When being irradiated by ultraviolet light, the photo initiator enables the first monomer material to react in a polymerization to form the alignment films. | 10-11-2012 |
20120313039 | PHOTOPOLYMERIZABLE LIQUID CRYSTAL MIXTURE AND MANUFACTURING METHOD OF PHOTOPOLYMERIZABLE LIQUID CRYSTAL - A photopolymerizable liquid crystal mixture includes a first photopolymerizable monomer, a second photopolymerizable monomer, a first photoinitiator, a second photoinitiator, and a liquid crystal material. A manufacturing method of photopolymerizable liquid crystal includes the following steps. A first light source is provided to irradiate the photopolymerizable liquid crystal mixture without providing a driving voltage, for inducing photopolymerization of the first photoinitiator and the first photopolymerizable monomer. A second light source is provided to irradiate the photopolymerizable liquid crystal mixture without providing a driving voltage, for inducing photopolymerization of the second photoinitiator and the second photopolymerizable monomer and aligning the liquid crystal material along a direction. | 12-13-2012 |
20130169895 | Three-Dimensional Imaging Device - A three-dimensional imaging device is provided which includes a display device and a viewing device. The display device includes a first substrate, a second substrate, a black absorbing layer and a cholesteric liquid crystal layer including a first levo-cholesteric liquid crystal layer and a first dextro-cholesteric liquid crystal layer. The viewing device includes a second levo-cholesteric liquid crystal layer and a second dextro-cholesteric liquid crystal layer. The first levo-cholesteric liquid crystal layer is made of a same material as the second levo-cholesteric liquid crystal layer, and the first dextro-cholesteric liquid crystal layer is made of a same material as the second dextro-cholesteric liquid crystal layer. | 07-04-2013 |
20130227830 | MANUFACTURING METHOD OF OPTICAL FILM AND MANUFACTURING METHOD OF STEREOSCOPIC DISPLAY - A manufacturing method of an optical film includes following steps. An alignment solution is coated onto a first substrate having a first area and a second area. The alignment solution on the first substrate is exposed to a polarized light to form an optical alignment film having a first alignment direction and a second alignment direction on the two areas, respectively. A composite liquid crystal (LC) material containing a reactive LC material and a monomer material is coated onto the optical alignment film. The optical alignment film is sequentially exposed to a first non-polarized light having a monomer material absorption wavelength and a second non-polarized light having a reactive LC material absorption wavelength, thus the monomer material reacts with the reactive LC material, and the reactive LC material is solidified along the first and second alignment directions in sequence. A manufacturing method of a stereoscopic display is also provided. | 09-05-2013 |
20130235184 | SYSTEM FOR ALIGNING AND ATTACHING A 3D IMAGE DISPLAY AND METHOD FOR POSITIONING A PHASE RETARDER SUBSTRATE - A method for positioning a phase retarder substrate includes the following steps. A phase retarder substrate is provided, wherein the phase retarder substrate includes a first align mark which includes a patterned phase retarder film. An image capturing unit is disposed at one side of the phase retarder substrate. A light source is disposed at the other side of the phase retarder substrate. An upper polarizing sheet is disposed between the image capturing unit and the patterned phase retarder film, and a lower polarizing sheet is disposed between the light source and the patterned phase retarder film. An image of the light which passes through the lower polarizing sheet, the patterned phase retarder film and the upper polarizing sheet is captured so as to position the phase retarder substrate. | 09-12-2013 |
20130258252 | TRANSPARENT LIQUID CRYSTAL DISPLAY DEVICE AND MANUFACTURING METHOD FOR THE SAME - The present invention discloses a transparent liquid crystal display device and manufacturing method thereof. By adding dichroic dyes and the dichroic dyes having characteristic of rotating with liquid crystal materials, light absorption ability of polymer network liquid crystals is increased. The present invention is capable of solving a problem which a dark state is not sufficiently dark, thus enhances contrast performance of the transparent liquid crystal display device. | 10-03-2013 |
20140016078 | LIQUID CRYSTAL COMPOSITION, LIQUID CRYSTAL DISPLAY PANEL AND FABRICATING METHOD THEREOF - A liquid crystal display panel including a first substrate, a second substrate, a liquid crystal molecule layer, a first liquid crystal cell layer and a second liquid crystal cell layer is provided. The second substrate is disposed opposite to the first substrate. The liquid crystal molecule layer has a plurality of liquid crystal molecules and disposed between the first substrate and the second substrate. The first liquid crystal cell layer has a plurality of first liquid crystal cells and disposed between the first substrate and the liquid crystal molecule layer. The second liquid crystal cell layer has a plurality of second liquid crystal cells and disposed between the second substrate and the liquid crystal molecule layer. Moreover, a liquid crystal composition used to make the liquid crystal display panel and a fabricating method of liquid crystal panel are also provided. | 01-16-2014 |
20140049707 | LIQUID CRYSTAL COMPOSITION FOR LC LENS AND 3D DISPLAY CONTAINING THE SAME - A liquid crystal composition for liquid crystal lens and a stereoscopic (3D) display containing the same are provided. The liquid crystal composition includes a main liquid crystal (chemical formula I), a first optical modifier (R811 or S811), a second optical modifier (CB15), and a dielectric constant modifier (chemical formula IV). The 3D display utilizes a horizontal electric field to make the above liquid crystal composition form crystal lens. | 02-20-2014 |
Patent application number | Description | Published |
20100296698 | MOTION OBJECT DETECTION METHOD USING ADAPTIVE BACKGROUND MODEL AND COMPUTER-READABLE STORAGE MEDIUM - A motion object detection method using an adaptive background model and a computer-readable storage medium are provided. In the motion object detection method, a background model establishing step is firstly performed to establish a background model to provide a plurality of background brightness reference values. Then, a foreground object detecting step is performed to use the background model to detect foreground objects. In the background model establishing step, a plurality of brightness weight values are firstly provided in accordance with the brightness of background pixels, wherein each of the brightness weight values is determined in accordance with the relative background pixel. Thereafter, the background brightness reference values are calculated based on the brightness of the background pixels and the brightness weight values. In addition, a computer can perform the motion object detection method after reading the computer-readable storage medium. | 11-25-2010 |
20130256416 | BARCODE RECOGNION METHOD AND COMPUTER PRODUCT THEREOF - A barcode recognition method and a computer program product thereof are provided. In the barcode recognition method, at first, a foreground extraction step is performed to obtain a binary image of a barcode image. Thereafter, an alignment step is performed to calculate a center coordinate, corner coordinates, a shift vector, and a rotation angle of the target barcode in accordance with the barcode image, the binary image, the shift vector, and the rotation angle. Thereafter, positions of data space patterns, boundary patterns, and an alignment type of the target barcode are determined in accordance with the center coordinate, the corner coordinates, the shift vector, and the rotation angle of the target barcode. Then, values of the target barcode are determined in accordance with the positions of the data space patterns, the boundary patterns, and the alignment type of the target barcode. | 10-03-2013 |
Patent application number | Description | Published |
20110081914 | RESOURCE ALLOCATION APPARATUS, SUBSCRIBER STATION, RESOURCE ALLOCATION METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM - The present invention relates to a resource allocation apparatus, subscriber station, resource allocation method, and non-transitory computer readable medium thereof. The resource allocation apparatus may know the unoccupied partition of the wireless network resource and allocate the unoccupied partition to the SS of the femtocell network. Thereby, the SS of the femtocell network will not occupy the same network resource of the macro BS or other femto SS, and interference of between femtocell and macrocell or other femtocell is reduced effectively. | 04-07-2011 |
20120082108 | FEMTOCELL BASE STATION, NETWORK RESOURCE ALLOCATION METHOD, AND NON-TRANSITORY TANGIBLE MACHINE-READABLE MEDIUM THEREOF - A femtocell Base Station (femto-BS), a network resource allocation method, and a non-transitory tangible machine-readable medium thereof are provided. There are a plurality of available network resource units. The femto-BS determines an expected value that is related to the available network resource units being used by the femto-BS and its neighboring femto-BSs without having interferences. The expected value is related to a number of the available network resource units and a number of the neighboring femto-BSs. Based on the expected value, the femto-BS calculates a plurality of strategy probability values that are related to different numbers of the available network resource units used by the femto-BS. The femto-BS calculates an assigned number according to the strategy probability values. Among the available network resource units, the femto-BS can use the assigned number of them. | 04-05-2012 |
20130329672 | RESOURCE ALLOCATION APPARATUS, RESOURCE ALLOCATION METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM - The present invention relates to a resource allocation apparatus, resource allocation method, and non-transitory computer readable medium thereof. The resource allocation apparatus adapted for a network comprising a femto base station (BS) which communicates with the femto BS and includes a storage, a transceiver and a processor connected to the storage and the transceiver. The storage stores a random function, reuse information and fractional frequency reuse (FFR) information which records an original cell ID/frequency corresponding relation of an unoccupied partition of the network. The processor selects a time partition from the unoccupied partition according to the random function and the reuse information, changes the original cell ID/frequency corresponding relation to generate a changed cell ID/frequency corresponding relation according to the FFR information; and generates an allocation message according to the time partition and the changed cell ID/frequency corresponding relation, wherein the transceiver conveys the allocation message to the femto BS. | 12-12-2013 |
20130331112 | SUBSCRIBER STATION, RESOURCE ALLOCATION METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM - The present invention relates to a subscriber station, resource allocation method, and non-transitory computer readable medium thereof. The subscriber station using in a femtocell network comprises a receiving interface and a processor. The receiving interface receives a frame of the femtocell network. The processor, electrically connected to the receiving interface, blindly decodes a first logical frequency resource unit (LRU) of a frequency partition of the frame to obtain an allocation message, determines the allocation message is relative to the subscriber station, and proceeds a data transmission in the femtocell network according to the allocation message. | 12-12-2013 |
Patent application number | Description | Published |
20120037989 | LDMOS HAVING SINGLE-STRIP SOURCE CONTACT AND METHOD FOR MANUFACTURING SAME - LDMOS devices having a single-strip contact pad in the source region, and related methods of manufacturing are disclosed. The LDMOS may comprise a first well lightly doped with a first dopant and formed into a portion of a substrate, the first well having a drain region at its surface heavily doped with the first dopant, and a second well lightly doped with a second dopant formed in another portion of the substrate, the second well having a source region at its surface comprising first portions heavily doped with the first dopant directly adjacent second portions heavily doped with the second dopant. Also, the LDMOS device may comprise a field oxide at the upper surface of the substrate between the source and drain regions, and contacting the first well but separated from the second well, and a gate formed partially over the field oxide and partially over the source region. The LDMOS may also comprise contact pads in contact with the gate, and source and drain regions, wherein the contact pad in contact with the source regions comprises a single-strip of conductive material extending across the source region. | 02-16-2012 |
20120146139 | HIGH VOLTAGE SEMICONDUCTOR DEVICE - A semiconductor device for a high voltage application includes a doped source base region, an N+ source region, a P+ source region and a gate structure. The doped source base region has P-type. The N+ source region extends downwards into the doped source base region. The P+ source region is close to the N+ source region, extends downwards into the doped source base region, and is doped heavier than the doped source base region. The gate structure is coupled to the N+ source region and is near to the P+ source region. | 06-14-2012 |
20120270350 | SEMICONDUCTOR BIO-SENSORS AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening. | 10-25-2012 |
20130037883 | LDPMOS STRUCTURE FOR ENHANCING BREAKDOWN VOLTAGE AND SPECIFIC ON RESISTANCE IN BICMOS-DMOS PROCESS - An LDPMOS structure having enhanced breakdown voltage and specific on-resistance is described, as is a method for fabricating the structure. A P-field implanted layer formed in a drift region of the structure and surrounding a tightly doped drain region effectively increases breakdown voltage while maintaining a relatively low specific on-resistance. | 02-14-2013 |
20130056825 | MOS DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region. | 03-07-2013 |
20130207236 | HIGH-BETA BIPOLAR JUNCTION TRANSISTOR AND METHOD OF MANUFACTURE - An NPN bipolar junction transistor is disclosed that exhibits a collector-to-emitter breakdown voltage greater than 10 volts and a beta greater than 300. The large value of beta is obtained by fabricating the transistor with an extra IN-type layer that reduces recombination of electrons and holes. | 08-15-2013 |
20140061721 | MOS DEVICE AND METHOD FOR FABRICATING THE SAME - An improved MOS device is provided whereby the p-top layer is defined by a series of discretely placed p type top diffusion regions. The invention also provides methods for fabricating the MOS device of the invention. | 03-06-2014 |
20140175547 | SEMICONDUCTOR DEVICE HAVING VARYING P-TOP AND N-GRADE REGIONS - An improved semiconductor is provided whereby n-grade and the p-top layers are defined by a series of discretely placed n-type and p-type diffusion segments. Also provided are methods for fabricating such a semiconductor. | 06-26-2014 |
20140197467 | HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE - A JFET structure includes a first JFET having a first terminal and a second JFET neighboring with the first JFET. Both JFETs commonly share the first terminal and the first terminal is between the gate of each JFET. The JFET also provides at least one tuning knob to adjust the pinch-off voltage and a tuning knob to adjust the breakdown voltage of the JFET structure. Moreover, the JFET has a buried layer as another tuning knob to adjust the pinch-off voltage of the JFET structure. | 07-17-2014 |
20140302654 | MOS device and method of manufacturing the same - A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region. | 10-09-2014 |
20150048452 | ULTRA-HIGH VOLTAGE SEMICONDUCTOR HAVING AN ISOLATED STRUCTURE FOR HIGH SIDE OPERATION AND METHOD OF MANUFACTURE - A semiconductor device, in particular, an ultra-high metal oxide semiconductor (UHV MOS) device, is defined by a doped gradient structure in a drain region. For example, an ultra-high n-type metal oxide semiconductor (UHV NMOS) device is defined by an n-doped gradient structure in the drain region. The n-doped gradient structure has at least one of a high voltage n- (HVN-) well, a drain side high voltage n-type deep (HVND) well, and a drain side n-type well (NW) disposed in the drain region. A drain side n+ well is additionally disposed in the at least one of the HVN- well, the drain side HVND well, and the drain side NW. A method of manufacturing a UHV NMOS device having a doped gradient structure of a drain region is also provided. | 02-19-2015 |
Patent application number | Description | Published |
20120241861 | Ultra-High Voltage N-Type-Metal-Oxide-Semiconductor (UHV NMOS) Device and Methods of Manufacturing the same - An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer. | 09-27-2012 |
20120280316 | Semiconductor Structure and Manufacturing Method for the Same - A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a first doped well, a first doped electrode, a second doped electrode, doped strips and a doped top region. The doped strips are on the first doped well between the first doped electrode and the second doped electrode. The doped strips are separated from each other. The doped top region is on the doped strips and extended on the first doped well between the doped strips. The first doped well and the doped top region have a first conductivity type. The doped strips have a second conductivity type opposite to the first conductivity type. | 11-08-2012 |
20130020680 | SEMICONDUCTOR STRUCTURE AND A METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a diode. The diode comprises a first doped region, a second doped region and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region and the third doped region are separated from each other by the first doped region. The third doped region has a first portion and a second portion adjacent to each other. The first portion and the second portion are respectively adjacent to and away from the second doped region. A dopant concentration of the first portion is bigger than a dopant concentration of the second portion. | 01-24-2013 |
20130265102 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and method for manufacturing the same are provided. The semiconductor structure includes a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type formed in the deep well and extending down from the surface of the substrate; and a second well having the second conductive type formed in the deep well and extending down from the surface of the substrate, and the second well adjacent to the first well. The first well includes a block region and plural finger regions joined to one side of the block region, while the second well includes plural channel regions interlaced with the finger regions to separate the finger regions. | 10-10-2013 |
20130295728 | Semiconductor Structure and Manufacturing Method for the Same - A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a first doped well, a first doped electrode, a second doped electrode, doped strips and a doped top region. The doped strips are on the first doped well between the first doped electrode and the second doped electrode. The doped strips are separated from each other. The doped top region is on the doped strips and extended on the first doped well between the doped strips. The first doped well and the doped top region have a first conductivity type. The doped strips have a second conductivity type opposite to the first conductivity type. | 11-07-2013 |
20140015016 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a bulk, a gate, a source, a drain and a bulk contact region. The gate is on the bulk. The source and the drain are in the bulk on opposing sides of the gate respectively. The bulk contact region is only in a region of the bulk adjacent to the source. The bulk contact region is electrically connected to the bulk. | 01-16-2014 |
20140024205 | SEMICONDUCTOR STRUCTURE AND A METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a diode. The diode comprises a first doped region, a second doped region and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region and the third doped region are separated from each other by the first doped region. The third doped region has a first portion and a second portion adjacent to each other. The first portion and the second portion are respectively adjacent to and away from the second doped region. A dopant concentration of the first portion is bigger than a dopant concentration of the second portion. | 01-23-2014 |
20140054656 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a device region, a first doped region and a gate structure. The first doped region is formed in the substrate adjacent to the device region. The gate structure is on the first doped region. The first doped region is overlapped the gate structure. | 02-27-2014 |
20140065781 | Ultra-High Voltage N-Type-Metal-Oxide-Semiconductor (UHV NMOS) Device and Methods of Manufacturing the same - An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer. | 03-06-2014 |
20140151764 | SEMICONDUCTOR AND MANUFACTURING METHOD THEREOF - A semiconductor element and a manufacturing method thereof are provided. The semiconductor element includes a base, an epitaxy layer, a first well, a second well, a third well, a first heavily doping region, a second heavily doping region, a implanting region and a conductive layer. The epitaxy layer is disposed on the base. The first well, the second well and the third well are disposed in the epitaxy layer. The third well is located between the first well and the second well. A surface channel is formed between the first heavily doping region and the second heavily doping region. The implanting region is fully disposed between the surface channel and the base and disposed at a projection region of the first well, the second well and the third well. | 06-05-2014 |
20140175560 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a first doped region, a second doped region, and a gate structure. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The gate structure is formed on the first doped region and the second doped region. The gate structure comprises a first gate portion and a second gate portion, which are separated from each other by a gap. | 06-26-2014 |
20140191792 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD AND OPERATING METHOD FOR THE SAME - A semiconductor device and a manufacturing method and an operating method for the same are provided. The semiconductor device comprises a substrate, a deep well, a first well, a first doped electrode region, a second doped electrode region and a high threshold voltage channel region. The substrate has a first type conductivity. The deep well is formed in the substrate and has a second type conductivity opposite to the first conductivity. The first well is formed in the deep well and has at least one of the first type conductivity and the second type conductivity. The first and the second doped electrode regions are formed in the first well. The second doped electrode is adjacent to the first doped electrode and has the second conductivity. The high threshold voltage channel region is formed in the first well and extending down from the surface of the substrate. | 07-10-2014 |
20140264855 | SEMICONDUCTOR COMPOSITE LAYER STRUCTURE AND SEMICONDUCTOR PACKAGING STRUCTURE HAVING THE SAME THEREOF - A semiconductor composite layer structure disposed on a substrate having an electronic circuit structure and a first conductive layer is disclosed. The semiconductor composite layer structure comprises a plurality of dielectric layers, a first wetting layer, a stiff layer and a second wetting layer. The dielectric layers are disposed on the substrate separately. The first wetting layer is disposed on the dielectric layer and the substrate between the dielectric layers. The stiff layer is disposed on the first wetting layer. The second wetting layer is disposed on stiff layer, for contacting with a second conductive layer. | 09-18-2014 |
20140342511 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The doped strip is formed in the first doped region and has the second type conductivity. The top doped region is formed in the doped strip and has the first type conductivity. The top doped region has a first sidewall and a second sidewall opposite to the first sidewall. The doped strip is extended beyond the first sidewall or the second sidewall. | 11-20-2014 |
Patent application number | Description | Published |
20090256183 | Single Gate Nonvolatile Memory Cell With Transistor and Capacitor - A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices. | 10-15-2009 |
20090256184 | Single Gate Nonvolatile Memory Cell With Transistor and Capacitor - A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices. | 10-15-2009 |
20110049677 | Buried Layer of An Integrated Circuit - Various aspects of the technology are directed to integrated circuit manufacturing methods and integrated circuits. In one method, a first charge type buried layer in a semiconductor material of an integrated circuit by implanting first charge type dopants of the first charge type buried layer through a sacrificial oxide over the semiconductor material and through an intermediate region of the semiconductor material transited by the implanted first charge type dopants. When the implanted dopants pass through the sacrificial oxide, damage to the semiconductor crystalline lattice is averted. If the sacrificial oxide were absent, the implanted dopants would have passed through and damaged the semiconductor crystalline lattice instead. Later, a pre-anneal oxide is grown and removed. | 03-03-2011 |
20110121373 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor memory device includes a substrate of a first impurity type, a first well region of a second impurity type in the substrate, the second impurity type being different from the first impurity type, a second well region of the first impurity type in the substrate, a patterned first dielectric layer on the substrate extending over the first and second well regions, a patterned first gate structure on the patterned first dielectric layer, a patterned second dielectric layer on the patterned first gate structure, and a patterned second gate structure on the patterned second dielectric layer. The patterned first gate structure may include a first section extending in a first direction and a second section extending in a second direction orthogonal to the first section, wherein the first section and the second section intersects each other in a cross pattern. The patterned second gate structure may include at least one of a first section extending in the first direction over the first section of the patterned first gate structure or a second section extending in the second direction over the second section of the patterned first gate structure. | 05-26-2011 |
20110169137 | HIGH-BETA BIPOLAR JUNCTION TRANSISTOR AND METHOD OF MANUFACTURE - An NPN bipolar junction transistor is disclosed that exhibits a collector-to-emitter breakdown voltage greater than 10 volts and a beta greater than 300. The large value of beta is obtained by fabricating the transistor with an extra N-type layer that reduces recombination of electrons and holes. | 07-14-2011 |
20110266601 | Single Gate Semiconductor Device - A semiconductor device has a gate multiple doping regions on both sides of the gate. The gate can be shared by a transistor and a capacitor. | 11-03-2011 |
20110303977 | LDPMOS STRUCTURE FOR ENHANCING BREAKDOWN VOLTAGE AND SPECIFIC ON RESISTANCE IN BICMOS-DMOS PROCESS - An LDPMOS structure having enhanced breakdown voltage and specific on-resistance is described, as is a method for fabricating the structure. A P-field implanted layer formed in a drift region of the structure and surrounding a lightly doped drain region effectively increases breakdown voltage while maintaining a relatively low specific on-resistance. | 12-15-2011 |
20120012900 | SEMICONDUCTOR BIO-SENSORS AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening. | 01-19-2012 |
20120025352 | BIPOLAR JUNCTION TRANSISTOR DEVICES - A bipolar junction transistor (BJT) device including a base region, an emitter region and a collector region comprises a substrate, a deep well region in the substrate, a first well region in the deep well region to serve as the base region, a second well region in the deep well region to serve as the collector region, the second well region and the first well region forming a first junction therebetween, and a first doped region in the first well region to serve as the emitter region, the first doped region and the first well region forming a second junction therebetween, wherein the first doped region includes a first section extending in a first direction and a second section extending in a second direction different from the first direction, the first section and the second section being coupled with each other. | 02-02-2012 |
20120086052 | HIGH VOLTAGE MOS DEVICE AND METHOD FOR MAKING THE SAME - A high-voltage metal-oxide-semiconductor (HVMOS) device may include a source, a drain, a gate positioned proximate to the source, a drift region disposed substantially between the drain and a region of the gate and the source, and a self shielding region disposed proximate to the drain. A corresponding method is also provided. | 04-12-2012 |
20120326276 | Buried Layer of An Integrated Circuit - Various aspects of the technology are directed to integrated circuit manufacturing methods and integrated circuits. In one method, a first charge type buried layer in a semiconductor material of an integrated circuit by implanting first charge type dopants of the first charge type buried layer through a sacrificial oxide over the semiconductor material and through an intermediate region of the semiconductor material transited by the implanted first charge type dopants. When the implanted dopants pass through the sacrificial oxide, damage to the semiconductor crystalline lattice is averted. If the sacrificial oxide were absent, the implanted dopants would have passed through and damaged the semiconductor crystalline lattice instead. Later, a pre-anneal oxide is grown and removed. | 12-27-2012 |
20140264336 | PATTERN FOR ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICE MANUFACTURING AND PROCESS MONITORING - A pattern for use in the manufacture of semiconductor devices is provided which, according to an example embodiment, may comprise at least one second field region comprising a main array of dies, each having a height of Y | 09-18-2014 |
Patent application number | Description | Published |
20120256273 | METHOD OF UNIFYING DEVICE PERFORMANCE WITHIN DIE - A method of unifying device performance within an integrated circuit die includes providing a layout of an integrated circuit die with multiple functional circuit blocks; filling a field between the multiple functional circuit blocks with dummy diffusion patterns; and filling the field between the multiple functional circuit blocks with dummy gate patterns such that the dummy gate patterns and the dummy diffusion patterns are completely overlapped. | 10-11-2012 |
20120286390 | ELECTRICAL FUSE STRUCTURE AND METHOD FOR FABRICATING THE SAME - An electrical fuse structure includes a top fuse, a bottom fuse and a via conductive layer positioned between the top fuse and the bottom fuse for providing electric connection. The top fuse includes a top fuse length and the top fuse length is equal to or larger than a predetermined value. The bottom fuse includes a bottom fuse length larger than the top fuse length. | 11-15-2012 |
20130062707 | DUMMY CELL PATTERN FOR IMPROVING DEVICE THERMAL UNIFORMITY - A dummy cell pattern includes a dummy diffusion pattern disposed within a predetermined region A; a trench isolation pattern encompassing the dummy diffusion pattern in the predetermined region A; a first dummy gate pattern disposed on the dummy diffusion pattern with two ends of the first dummy gate pattern extending above the trench isolation pattern, thereby forming overlapping areas C | 03-14-2013 |
20130240956 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device. | 09-19-2013 |
Patent application number | Description | Published |
20120173922 | APPARATUS AND METHOD FOR HANDLING FAILED PROCESSOR OF MULTIPROCESSOR INFORMATION HANDLING SYSTEM - An apparatus for handling a failed processor of a multiprocessor system including at least two processors interconnected by processor interconnects for facilitating transactions of the processors. The at least two processors include a first processor set as a default boot processor in response to a boot up operation of the multiprocessor computer, and a second processor. The apparatus includes: a baseboard management module for detecting and receiving health information of the processors; a multiplexer coupled to the baseboard management module and respectively to the processors, the multiplexer being operative to switch between the processors; and a processor ID controller coupled to the baseboard management module and respectively to the processors. In response to the health information indicating the first processor has failed, the processor ID controller sets the second processor as the default boot processor and the baseboard management module enables the multiplexer to switch to the second processor. | 07-05-2012 |
20120278653 | HANDLING A FAILED PROCESSOR OF MULTIPROCESSOR INFORMATION HANDLING SYSTEM - A method for handling a failed processor of a multiprocessor system, the multiprocessor system comprising at least two processors interconnected by processor interconnects for transactions between processors, the processors comprising a first processor and a second processor, the first processor being set as a default boot processor in response to a boot-up operation of the multiprocessor system. The method comprises: detecting and receiving, via a baseboard management module, health information of the at least two processors; providing a multiplexer operative to switch between the at least two processors, the multiplexer being coupled to the baseboard management module and respectively to the at least two processors; and, in response to the health information indicating the first processor has failed, setting, via a processor ID controller, the second processor as the default boot processor and enabling, via the baseboard management module, the multiplexer to switch to the second processor. | 11-01-2012 |