Liebmann, US
Frank E. Liebmann, American Fork, UT US
Patent application number | Description | Published |
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20090122826 | Infrared Target Temperature Correction System and Method - Infrared IR thermometer calibration systems and methods are disclosed in which the temperature of an IR thermometer calibration system is controlled such that radiation emitted by a target at a given input temperature is equal to the radiation emitted by a graybody heated to the input temperature and having an emissivity equal to an emissivity setting of an IR thermometer to be calibrated using the IR thermometer calibration system. | 05-14-2009 |
20100037626 | TEMPERATURE CALIBRATION DEVICE HAVING RECONFIGURABLE HEATING/COOLING MODULES TO PROVIDE WIDE TEMPERATURE RANGE - A temperature calibration device uses Peltier cells for heating and cooling. The Peltier cells are connected to a relay that connects the cells to each other in one configuration for heating and a different configuration for cooling. The Peltier cells also receive supply voltages having different magnitudes and polarities for heating and cooling. By changing the manner in which the Peltier cells are connected to each other and using different supply voltages for heating and cooling, the cells are able to operate closer to their specified maximum temperature differential without sacrificing the useful life of the cells. | 02-18-2010 |
20100103976 | INFRARED TARGET TEMPERATURE CORRECTION SYSTEM AND METHOD - Infrared IR thermometer calibration systems and methods are disclosed in which the temperature of an IR thermometer calibration system is controlled such that radiation emitted by a target at a given input temperature is equal to the radiation emitted by a graybody heated to the input temperature and having an emissivity equal to an emissivity setting of an IR thermometer to be calibrated using the IR thermometer calibration system. | 04-29-2010 |
Jeffrey M. Liebmann, Great Neck, NY US
Patent application number | Description | Published |
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20080292680 | Hypercompressed polymer particles for controlled release ophthalmic medications - An ophthalmic dispensing device having a polymer which is combined with an ophthalmic therapeutic agent in the form of a microparticle which is hypercompressed to form a controlled release dispensing device for ophthalmic use. | 11-27-2008 |
20090148498 | Controlled release implantable dispensing device and method - A dispensing device having a polymer which is combined with a therapeutic agent in the form of a microparticle which is compressed to form a controlled release dispensing device and methods of locally administering a therapeutic agent using said microparticles. | 06-11-2009 |
20090270308 | Controlled release implantable dispensing device and method - A dispensing device having a polymer which is combined with a therapeutic agent in the form of a microparticle or nanoparticle which is “hyper-compressed” to form a controlled release dispensing device and methods of locally administering a therapeutic agent using said microparticles. | 10-29-2009 |
20100173000 | Controlled release implantable dispensing device and method - A dispensing device having a polymer which is combined with a therapeutic agent in the form of a microparticle or nanoparticle which is “hyper-compressed” to form a controlled release dispensing device and methods of locally administering a therapeutic agent using said microparticles. | 07-08-2010 |
Lars Liebmann, Poughquag, NY US
Patent application number | Description | Published |
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20090125868 | MULTILAYER OPC FOR DESIGN AWARE MANUFACTURING - A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images. | 05-14-2009 |
Lars W. Liebmann, Hopewell Junction, NY US
Patent application number | Description | Published |
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20110166686 | AUTOMATED SENSITIVITY DEFINITION AND CALIBRATION FOR DESIGN FOR MANUFACTURING TOOLS - A method of automatic calibration of a design for manufacturing (DfM) simulation tool includes providing, as a first input, one or more defined rules for each of one or more semiconductor device levels to be simulated by the tool, and providing, as a second input, a plurality of defined feature size threshold ranges and increments for use in histogram generation of a number of failures with respect to a reference circuit; providing, as a third input, the reference circuit; executing the defined rules for the semiconductor device levels to be simulated, and outputting a fail count for the reference circuit at each defined threshold value, thereby generating histogram data of fail count versus threshold for the reference circuit; and providing, as a fourth input, a defined fail count metric, thereby calibrating the DfM tool for use with respect to a target circuit. | 07-07-2011 |
20120192137 | PLACEMENT AND OPTIMIZATION OF PROCESS DUMMY CELLS - A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells. | 07-26-2012 |
Lars Wolfgang Liebmann, Poughquag, NY US
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20130159955 | DYNAMIC PIN ACCESS MAXIMIZATION FOR MULTI-PATTERNING LITHOGRAPHY - A method, system, and computer program product for improving pin access in a design of an integrated circuit (IC) for multi-patterning lithography (MPL) are provided in the illustrative embodiments. A cell is placed in the IC design, the cell including a pin shape configured to connect a pin of the cell to a semi-conductor component in the IC design, the cell including a coloring conflict due to the pin shape and an other shape in the cell each being colored using a first color for fabricating onto a wafer using MPL. A net is routed to the pin shape without resolving the coloring conflict, wherein the routing routes the net using a first segment of the pin shape. The pin shape is modified after routing to resolve the coloring conflict to result in a modified cell. | 06-20-2013 |