Patent application number | Description | Published |
20090086801 | Method for reliable injection of deterministic jitter for high speed transceiver simulation - A method and a corresponding system for characterizing the performance of a clock and data recovery circuit in a digital transceiver is presented. The method comprises phase modulating a jitter-free data signal by a testing signal having added data jitter and measuring the time the clock and data recovery system takes to achieve bit lock of a phase modulated signal. Data uncorrelated timing jitter corresponding to a user defined probability distribution is included in the jitter testing signal. Utilization of a variable probability distribution in generating data uncorrelated timing jitter, as provided by the present invention, allows for greater flexibility and accuracy in clock and data recovery circuit testing and characterization. | 04-02-2009 |
20090086872 | Method for binary clock and data recovery for fast acquisition and small tracking error - A novel method and system for clock and data recovery in high speed serial transceiver applications allowing for fast bit lock acquisition and small data tracking error is presented. The clock and data recovery method utilizes a variable bandwidth loop filter to generate a phase adjustment signal used by a phase interpolator in generating a clock signal at the same frequency and phase as the incoming digital data stream. The loop filter bandwidth may be adjusted to correspond with a plurality of clock and data recovery operating modes. In particular, the filter bandwidth may be set to either a high or a low value depending on whether the phase difference between the recovered clock signal and the incoming digital data stream is above or below a programmed threshold value. | 04-02-2009 |
20090161452 | Systems and methods for clean DQS signal generation in source-synchronous DDR2 interface design - A method and circuit for generating a signal to synchronize DQ data transfer in memory interface design is presented. The presented method includes receiving a strobe signal having a preamble period before and post-amble period after data transfer burst synchronization signal edge transitions, determining a timing location of the strobe signal preamble period, determining a timing location of the strobe signal post-amble period, and generating a clean strobe signal that tracks the data transfer burst synchronization edge transitions of the strobe signal after the strobe signal preamble begins and before the strobe signal post-amble ends based on the respective determined timing locations of the strobe signal preamble and post-amble periods. In this manner, DQ data transfer may be synchronized according to the burst synchronization signal edge transitions and errors caused by strobe signal level jitter during the preamble and post-amble periods are reduced. | 06-25-2009 |
20090167443 | Digitally compensated highly stable holdover clock generation techniques using adaptive filtering - A system and method for generating a highly stable holdover clock utilizing an integrated circuit and an external OCXO is presented. The integrated circuit comprises an input reference clock receiver, a phase and frequency detector that generates an error signal between the input reference clock signal and a feedback clock signal, a data storage block that stores model parameters to predict frequency variations of the OCXO, an adaptive filtering module that includes a digital loop filter and algorithms for updating the model parameters and predicting frequency variations based on the model, a switch that enables the system to operate in normal or holdover mode, a digitally controlled oscillator, and a feedback divider. | 07-02-2009 |
20100008460 | Synchronous de-skew with programmable latency for multi-lane high speed serial interface - A method and system for performing clock calibration and de-skew on a multi-lane high speed serial interface is presented. Each of a plurality of serial lane transceivers associated with an individual bit lane receives a first data frame, comprising a training sequence header pattern. Based on each of the first data frames, the plurality of serial lane transceivers de-skew a plurality of data frames and generate a plurality of event signals. Using the plurality of event signals, a core clock, having a first phase, is adjusted to be phase aligned with the slowest bit lane. | 01-14-2010 |
20100098667 | CULTURE MEDIUM FOR BIFIDOBACTERIUM LONGUM, COMPOSITION COMPRISING THE SAME AND PREPARATION METHOD - The present invention provides a triple vital bacteria composition, including: powder of | 04-22-2010 |
20100119487 | CULTURE MEDIUM FOR LACTOBACILLUS ACIDOPHILUS AND STREPTOCOCCUS FAECALIS, COMPOSITION COMPRISING THE SAME AND PREPARATION METHOD THEREOF - The present invention provides a triple vital bacteria composition, including: powder of | 05-13-2010 |
20110098977 | HIGH SPEED CHIP SCREENING METHOD USING DELAY LOCKED LOOP - A voltage controlled delay line (VCDL) for measuring the maximum speed of a chip includes a first input configured to receive a reference clock signal, a first output configured to output an output clock signal, and a second input configured to receive a phase error signal representing a phase delay between the reference and output clock signals. A register stores a delay code applied by the VCDL to the reference clock signal to delay the reference clock signal to generate the output clock signal. The delay code is adjusted according to the phase error signal until the phase delay is equal to a predetermined value. A second output is coupled to an interface that reads the delay code from the register and outputs the delay code to automated testing equipment when the phase delay is equal to the predetermined value. The outputted delay code corresponds to the maximum chip speed. | 04-28-2011 |
20110103441 | CABLE MODEM - A cable modem includes an amplifier, a power module, a switch circuit, a monitor signal, a duplexer and a RF matching circuit. The switch includes a PMOS transistor and a first electronic switch. The RF matching circuit included a second electronic switch and an electronic matching device. The monitoring signal source is configured for outputting a control signal. When the monitoring signal source stops outputting the control signal, both the first electronic switch and the PMOS transistor are turned off to cut off the power to the amplifier, the second electronic switch is turned on, and conducts the RF signal received by the signal receiving/transmitting circuit to the duplexer which further conducts the RF signal to the radio frequency matching circuit. | 05-05-2011 |
20130034721 | POLYMER MODIFIED MORTAR FOR ROOFING SYSTEM - A roofing system comprising a thermal insulation foam layer which is applied onto a roof deck, and a mortar layer, wherein the thermal insulation foam layer is between the roof deck and the mortar layer. The mortar layer is made of a mortar composition, which could achieve the ratio of compressive strength to bending strength is less than 3 while keeping the bending strength larger than 7 MPa. | 02-07-2013 |
20130269260 | Scissor door block device with adjustable door block width - The invention discloses a scissor-type gate blocking apparatus with an adjustable blocking width of a gate leaf. According to its technical solutions, the apparatus comprises a shaft | 10-17-2013 |
20150087751 | DRY MIX FORMULATIONS CONTAINING CARBOXYLATED STYRENE-BUTADIENE REDISPERSIBLE POLYMER POWDERS AND ALUMINA RICH CONTAINING CEMENTS - Dry mix formulations containing a redispersible polymer powder (RDP) made of a low carboxylation, large particle size water-insoluble film—forming styrene butadiene polymer having at least one ethylenically unsaturated dicarboxylic acid monomer, and a high alumina content cement such as a calcium aluminate cement (CAC) or a calcium sulfoaluminate cement (CSA) provides cement compositions having unexpectedly superior water immersion shear strength and set time for a cement containing tile adhesive (CBTA or CTA), superior adhesion properties in water proofing mortars or mortar applications, and superior flexural and compressive strength in grout applications. | 03-26-2015 |