Patent application number | Description | Published |
20090195541 | RENDERING DYNAMIC OBJECTS USING GEOMETRY LEVEL-OF-DETAIL IN A GRAPHICS PROCESSING UNIT - The present embodiments provide a system for graphically rendering an object. This system operates first by pre-processing a geometry mesh for the object offline, wherein the geometry mesh is partitioned into a set of patches, and wherein each patch is bounded by a bounding box. The system then builds a multi-resolution representation for each of the set of patches. Next, during real time rendering, the system deforms the bounding boxes associated with the set of patches through superposition of object motions in each frame weighted by a set of predetermined mesh-skinning parameters. For each deformed bounding box, the system computes a geometry level-of-detail (LOD) value based on a projected area of the deformed bounding box in screen space. The system next deforms the object through a set of mesh skinning operations. The system then renders the deformed object based on the computed geometry LOD values for the set of patches and the multi-resolution representation for the geometry mesh. | 08-06-2009 |
20110289510 | ATOMIC-OPERATION COALESCING TECHNIQUE IN MULTI-CHIP SYSTEMS - A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available. | 11-24-2011 |
20120117317 | ATOMIC MEMORY DEVICE - In an integrated-circuit memory device having a memory core, a first data value is retrieved from an address-specified location within the memory core in response to a memory access command. The first data value is output from the memory device in response to the memory access command, and a second data value is stored in the address-specified location within the memory core in response to the memory access command. | 05-10-2012 |
20130275663 | ATOMIC-OPERATION COALESCING TECHNIQUE IN MULTI-CHIP SYSTEMS - A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available. | 10-17-2013 |
20150130818 | FLEXIBLE FILTER LOGIC FOR MULTI-MODE FILTERING OF GRAPHICAL TEXTURE DATA - Multi-mode texture filters suitable for performing both bilinear filtering based on a fractional texture address and generating a weighted average of a group of texel values based on predetermined texel weighting coefficients as dependent on a filter mode signal. In embodiments, the weighted average may be accumulated over a variety of filter footprints. In embodiments, multi-mode texture filter logic includes a plurality of flexible filter blocks. In further embodiments, a pair of flexible filter blocks staged with each performing one lerp phase in the bilinear filter mode while a pair of flexible filter blocks in the flexible filter mode generate a weighted average over a pair of texels of a texel quad. In embodiments, each flexible filter block has a same microarchitecture, enabling an efficient utilization in either bilinear filter or flexible filter mode. | 05-14-2015 |
20150130819 | MINIMUM-MAXIMUM FILTERING OF GRAPHICAL TEXTURE DATA - Texture filter logic suitable for determining a minimum or maximum texel value from a plurality of texel values associated with a filter footprint of arbitrary shape and size. In embodiments, logic circuitry includes a plurality of min/max comparison block stages is configured to perform comparisons and determine a min/max value of predetermined number of texel groups. In embodiments, the logic circuitry further includes a number of min/max collectors to accommodate filter footprints having more texel groups than the predetermined number accommodated by the min/max comparison block stages. Iterative comparisons may be performed until all texel groups in the given footprint have been compared. In further embodiments, the logic circuitry outputs four min/max texel values, which may then be further processed with a final comparison stages to arrive at one min/max value for a footprint. | 05-14-2015 |
20150130826 | LAND GRID ARRAY SOCKET FOR ELECTRO-OPTICAL MODULES - For a given texture address, a texture sampler fetches and reduces texture data with a filter accumulator suitable for providing a weighted average over a variety of filter footprints. A multi-mode texture sampler is configurable to provide both a wide variety of footprints in either a separable or non-separable filter modes and allow for a filter footprint significantly wider than the bi-linear (2×2 texel) footprint. In embodiments, sub-sample addresses are generated by the texture sampler logic to accommodate a desired footprint. The sub-sample addresses may be generated and sequenced by multi-texel units, such as 2×2 texel quads, for efficient filtering. In embodiments, filter coefficients are cached from coefficient tables stored in memory. | 05-14-2015 |
20150178187 | SINGLE COMMAND, MULTIPLE COLUMN-OPERATION MEMORY DEVICE - A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values. | 06-25-2015 |