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| 20100168871 | ARTIFICIAL DURA BIOMEDICAL DEVICE AND BRAIN SURGERY METHOD UTILIZING THE SAME - An artificial dura biomedical device and a brain surgery method utilizing the same are disclosed. The steps includes: fixing an artificial dura to a partial skull; and fixing the partial skull with the artificial dura to a cut hole of a whole skull. The artificial dura biomedical device includes an artificial dura and a connecting element. The connecting element fixes the partial skull with the artificial dura. | 07-01-2010 |
| 20100204508 | DENDRITIC COMPOUND AND USE THEREOF - A dendritic compound of the following structure: PD | 08-12-2010 |
| 20110015654 | SPINAL DISC ANULUS REPAIR METHOD AND APPARATUS - An apparatus for anulus fibrosus repair includes a shaft, a pair of curved suturing needles mounted in parallel on the shaft, and a rotational driving mechanism connected to the shaft, which is configured to rotate the shaft and the pair of needles about a rotation axis of the shaft. Each needle includes a substantially semi-annular body having a proximal end, a distal end, an inner periphery, and an outer periphery, and an arm extending radially inward from the proximal end, in which a concavity is formed in the body proximate to the distal end extending in a direction away from it. Also disclosed is a suturing technique associated with use of the repair apparatus. | 01-20-2011 |
| 20110117199 | FOAMY BIOMATERIAL FOR BIOLOGICAL TISSUE REPAIR - A kit for producing a foamed biocompatible material includes a container configured to sustain a high pressure, and a tissue-repair composition placed in the container. The composition contains a biocompatible material, a liquid carrier, and a gas. The container has an internal pressure of greater than 1 atm and less than 250 atm, and includes a valve and a nuzzle for releasing from the nuzzle a foam formed of the composition upon opening the valve. Methods of producing and applying the biocompatible material are also disclosed. | 05-19-2011 |
| 20110137318 | INJECTABLE THERMOPLASTIC POLYMERS FOR BIOLOGICAL TISSUE REPAIR - A method for filling a bone defect in a subject in need thereof is disclosed. The method includes heating a bone cement composition at a first temperature where the bone cement composition is fluidic, and delivering an effective amount of the fluidic bone cement composition at a second temperature to the bone defect thereby filling the bone defect and allowing the fluidic bone cement composition to solidify, the second temperature being sufficiently high for maintaining the bone cement composition fluidic without causing thermal necrosis. Also disclosed are systems for carrying out the method. | 06-09-2011 |
| 20120209383 | INTERVERTEBRAL CAGE AND IMPLANTING APPARATUS AND OPERATING METHOD THEREOF - An intervertebral cage, an implanting apparatus and an operating method thereof are provided. The intervertebral cage for being implanted between two adjacent vertebral bodies includes a body and a connecting portion. The body has a lateral convex surface, an inclined surface, a lateral concave surface and a connecting surface connected sequentially. The connecting portion includes a main portion and a protrusion. The main portion connected to the connecting surface has a through hole. The protrusion is protruded from the main portion into the through hole to form first and second inner arc surfaces. The maximum width of the intervertebral cage is a distance between first and second lines. The first and second lines are substantially parallel to a tangent line of the lateral convex surface and the first line, respectively. The distance between the inclined surface and the first line decreases gradually along a direction away from the connecting portion. | 08-16-2012 |
| 20120215322 | ARTIFICIAL DURA BIOMEDICAL DEVICE AND BRAIN SURGERY METHOD UTILIZING THE SAME - An artificial dura biomedical device and a brain surgery method utilizing the same are disclosed. The steps includes: fixing an artificial dura to a partial skull; and fixing the partial skull with the artificial dura to a cut hole of a whole skull. The artificial dura biomedical device includes an artificial dura and a connecting element. The connecting element fixes the partial skull with the artificial dura. | 08-23-2012 |
| 20120323242 | SURGICAL AWL AND METHOD OF USING THE SAME - A bone awl is provided for preparing a bone for implantation with a screw. The awl includes a shaft having a first end and a second end opposed to the first end. A handle is fixed to the first end, and an extension extends from the second end. The extension includes a first cutting portion configured to form a hole in bone and a second cutting portion configured to form an internal screw thread in the bone along the surface of the hole. The awl also includes an axial through passage that extends from the handle to the first cutting portion and is dimensioned to receive a Kirshner pin therein. | 12-20-2012 |
| 20120323278 | MINIMALLY INVASIVE SPINAL STABILIZATION SYSTEM - A spinal fixation assembly includes a pedicle rod and pedicle screws which secure the pedicle rod to the spine. Each pedicle screw includes a head configured to receive a portion of the pedicle rod, and a threaded portion extending from a first end of the head and configured to engage a vertebra. The pedicle rod is secured to the head by a fastener. The head includes a breakaway region that defines a location in which at least a first portion of the head can be easily separated from the remainder of the head upon application of sufficient force to the first portion. A minimally invasive method of implanting the spinal fixation assembly is disclosed. | 12-20-2012 |
| 20120323279 | MINIMALLY INVASIVE SPINAL STABILIZATION METHOD - A spinal fixation assembly includes a pedicle rod and pedicle screws which secure the pedicle rod to the spine. Each pedicle screw includes a head configured to receive a portion of the pedicle rod, and a threaded portion extending from a first end of the head and configured to engage a vertebra. The pedicle rod is secured to the head by a fastener. The head includes a breakaway region that defines a location in which at least a first portion of the head can be easily separated from the remainder of the head upon application of sufficient force to the first portion. A minimally invasive method of implanting the spinal fixation assembly is disclosed. | 12-20-2012 |
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| 20110102081 | AMPLIFIER CIRCUIT WITH OVERSHOOT SUPPRESSION - An amplifier circuit with overshoot suppress scheme including an input amplifier, an output amplifier, and a diode is provided. A first and a second input ends of the output amplifier are coupled to a differential output pair of the input amplifier. A first end of the diode is coupled to an output end of the output amplifier. A second end of the diode is coupled to the first input end of the output amplifier. When the voltage difference between the output and the input ends of the output amplifier is greater then the barrier voltage of the diode, the diode is turned on, so that the output end of the output amplifier is coupled to the input end of the output amplifier. In the transient state, it rapidly smoothes the overshoot signal. In the steady state, the diode is cut off to maintain the normal operation of the operational amplifier. | 05-05-2011 |
| 20120119834 | AMPLIFIER CIRCUIT WITH OVERSHOOT SUPPRESSION - An amplifier circuit with overshoot suppress scheme including an input amplifier, an output amplifier, and a diode is provided. A first and a second input ends of the output amplifier are coupled to a differential output pair of the input amplifier. The diode is coupled between an output end and the first input end of the output amplifier. When the voltage difference between the output and the input ends of the output amplifier is greater then the barrier voltage of the diode, the diode is turned on, so that the output end of the output amplifier is coupled to the input end of the output amplifier. In the transient state, it rapidly smoothes the overshoot signal. In the steady state, the diode is cut off to maintain the normal operation of the operational amplifier. | 05-17-2012 |
| 20120188015 | AMPLIFIER - An amplifier includes an output stage circuit, a current source, a PMOS input pair, an NMOS input pair and a current transferring circuit. The output stage circuit is electrically coupled to a supply voltage and a ground voltage. The current source has a node to provide a current. The PMOS input pair is coupled to the node and the ground voltage and controlled by an input voltage. The NMOS input pair coupled to the supply voltage is controlled by the input voltage. The current transferring circuit is coupled to the node and the NMOS input pair. When the input voltage is less than a specific value, the current flows into the PMOS input pair through the node. When the input voltage is larger than or equal to the specific value, the current flows into the NMOS input pair through the node and the current transferring circuit. | 07-26-2012 |
| 20120242411 | OPERATIONAL AMPLIFIER - An operational amplifier providing an output voltage signal to drive a load in response to an input voltage signal is provided. The operational amplifier includes a first input stage and a second input stage, a second stage and an output enable switch. The first input stage provides a first intermediate signal according to the voltages of an input and an output voltage signals in a transitional state. The second input stage provides a second intermediate signal according to the input and the output voltage signals in a steady state. The second stage provides the output voltage signal to an output node according to the first and the second intermediate signals in the transitional and the steady states respectively. The output enable switch is enabled in an output enable period to drive the load with the output voltage signal. | 09-27-2012 |
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| 20100308469 | METHOD AND APPARATUS OF FORMING A VIA - The present disclosure provides a semiconductor device that includes, a substrate; a first conductive line located over the substrate and extending along a first axis, the first conductive line having a first length and a first width, the first length being measured along the first axis; a second conductive line located over the first conductive line and extending along a second axis different from the first axis, the second conductive line having a second length and a second width, the second length being measured along the second axis; and a via coupling the first and second conductive lines, the via having an upper surface that contacts the second conductive line and a lower surface that contacts the first conductive line. The via has an approximately straight edge at the upper surface, the straight edge extending along the second axis and being substantially aligned with the second conductive line. | 12-09-2010 |
| 20110070738 | DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a hard mask layer on a material layer and forming a capping layer on the hard mask layer. The capping layer does not react with oxygen gas during a photoresist ashing process. The capping layer is patterned by using a first resist pattern and a second resist pattern as etch masks. After the capping layer is patterned, the hard mask layer is patterned by using the patterned capping layer as an etch mask. | 03-24-2011 |
| 20110108994 | INTEGRATED CIRCUITS AND METHODS FOR FORMING THE INTEGRATED CIRCUITS - A method for forming an integrated circuit includes forming a first dielectric layer over a gate electrode of a transistor. An etch-stop layer is formed over the first dielectric layer. An opening is formed through the first dielectric layer and the etch-stop layer, exposing a source/drain (S/D) region of the transistor. A metal layer is formed in the opening, contacting the S/D region of the transistor. The metal layer has a surface that is at least partially substantially level with a first top surface of the etch-stop layer. A damascene structure is formed and coupled with the metal layer. | 05-12-2011 |
| 20110275218 | DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a hard mask layer on a material layer and forming a capping layer on the hard mask layer. The capping layer does not react with oxygen gas during a photoresist ashing process. The capping layer is patterned by using a first resist pattern and a second resist pattern as etch masks. After the capping layer is patterned, the hard mask layer is patterned by using the patterned capping layer as an etch mask. | 11-10-2011 |
| 20120149204 | METHOD OF FORMING VIA HOLES - A method for forming vias and trenches for an interconnect structure on a substrate includes exposing via pitch reduction patterns in a photoresist layer, developing the patterns to remove the via pitch reduction patterns, etching the photoresist layer partially using a polymer gas to reshape the pattern into small via shapes, and etching the remaining photoresist layer to extend the reshaped pattern. The reshaped small via shape patterns have a smaller pitch than the via pitch reduction patterns in a long direction. For via pitch reduction patterns having two vias each, the pattern has a peanut-shape. During the reshaping etch operation, the polymer gas deposits more in a pinched-in middle section while allowing downward etch in unpinched sections. | 06-14-2012 |
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| 20110231621 | SYSTEM RECOVERY METHOD, AND STORAGE MEDIUM CONTROLLER AND STORAGE SYSTEM USING THE SAME - A system recovery method is provided. The system recovery method includes grouping storage addresses corresponding to a storage device into a first memory area and a second memory area. The system recovery method also includes storing initial data from a host system into the storage addresses of the first memory area, storing update data for updating the initial data into the storage addresses of the second memory area, and establishing an address corresponding table to record update information corresponding to the storage addresses for storing the update data. The system recovery method further includes erasing the update information from the address corresponding table when the storage device is powered off and re-coupled to the host system. Thereby, the system recovery method can instantly recover system settings. | 09-22-2011 |
| 20120297115 | PROGRAM CODE LOADING AND ACCESSING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS - A method of loading a program code from a rewritable non-volatile memory module is provided, wherein the program code includes data segments and two program code copies corresponding to the program code are stored in the rewritable non-volatile memory module. The method includes loading a first data segment of a first program code copy and determining whether the first data segment contains any uncorrectable error bit. The method still includes, when the first data segment does not contain any uncorrectable error bit, loading a second data segment of the first program code copy. The method further includes, when the first data segment contains an uncorrectable error bit, loading a first data segment of a second program code copy, and then loading a second data segment of the first program code copy or the second program code copy. Thereby, the program code can be successfully loaded. | 11-22-2012 |
| 20120324205 | MEMORY MANAGEMENT TABLE PROCESSING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS - A memory management table processing method for storing a plurality of entries belonging to a plurality of memory management tables into a buffer memory of a memory storage apparatus is provided, wherein each of the entries has at least one invalid bit. The present method includes following steps. An area corresponding to each of the memory management tables is configured in the buffer memory. Invalid bit information corresponding to each of the memory management tables is recorded. The invalid bit in each of the entries is removed according to the invalid bit information corresponding to each of the memory management tables, so as to generate a valid data stream corresponding to each of the entries. Each of the valid data streams is written into the corresponding area in the buffer memory. Accordingly, the storage space of the buffer memory can be efficiently utilized. | 12-20-2012 |
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| 20100140741 | STRUCTURE OF CAPACITOR SET - A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array. | 06-10-2010 |
| 20100148263 | SEMICONDUCTOR DEVICE STRUCTURE AND FABRICATING METHOD THEREOF - A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate. | 06-17-2010 |
| 20100271750 | CAPACITOR STRUCTURE - A capacitor structure is provided. The capacitor structure comprises a plurality of parallel conductive line levels and a plurality of vias. Each conductive line level comprises first conductive lines parallel to each other and second conductive lines parallel to each other. Also, the first conductive lines on different conductive line levels are aligned to each other and the second conductive lines on different conductive line levels are aligned to each other so as to form first conductive line co-planes and second conductive line co-planes. The vias are located on the conductive line co-planes and between the conductive line levels for connecting the conductive lines on the neighboring conductive line levels. The vias, on a height level of each of the conductive line co-planes, are arranged only on one of the neighboring conductive line co-planes. | 10-28-2010 |
| 20100320540 | SEMICONDUCTOR DEVICE STRUCTURE AND FABRICATING METHOD THEREOF - A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate. | 12-23-2010 |
| 20100327378 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a resistor and a metal gate structure. The substrate has a first area and a second area. The resistor is disposed in the first area, wherein the resistor does not include any metal layer. The metal gate structure is disposed in the second area. | 12-30-2010 |
| 20110156161 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device including a substrate, a first device, a second device and an interlayer dielectric layer is provided. The substrate has a first area and a second area. The first device is disposed in the first area of the substrate and includes a first dielectric layer on the substrate and a metal gate on the first dielectric layer. The second device is in the second area of the substrate and includes a second dielectric layer on the substrate and, a polysilicon layer on the second dielectric layer. It is noted that the height of the polysilicon layer is less than that of the metal gate of the first device. The interlayer dielectric layer covers the second device. | 06-30-2011 |
| 20110292565 | CAPACITOR STRUCTURE - A capacitor structure includes a plurality of conductive line levels located over the substrate. Each of the conductive line levels includes a first conductive line and a second conductive line. The first conductive lines in the conductive line levels form a first conductive line co-plane and the second conductive lines in the conductive line levels form a second conductive line co-plane. A first conductive end is electrically connected to the first conductive lines on the conductive line levels. A second conductive end is electrically connected to the second conductive lines on the conductive line levels. A plurality of vias are located between the neighboring conductive line levels and placed on only one of the first and second conductive line co-planes on a same level. | 12-01-2011 |
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| 20100097142 | DRIVING CIRCUIT SYSTEM AND METHOD OF ELEVATING SLEW RATE OF OPERATIONAL AMPLIFIER - The invention discloses a driving circuit system and a method of elevating a slew rate of an operational amplifier. The driving circuit system comprises an operational amplifier, a judging module and a bias enhancing module. The operational amplifier has an input stage driven by a bias current. The bias enhancing module is electrically connected to the judging module and the input stage of the operational amplifier respectively. The judging module is used to generate a bias enhancing signal according to an edge-trigger of a control signal. When the bias enhancing module receives the bias enhancing signal, the bias enhancing module provides an additional current, which cooperates with the bias current, for driving the input stage of the operational amplifier, so as to elevating a slew rate of the operational amplifier. | 04-22-2010 |
| 20100164929 | SOURCE DRIVER - The invention discloses a source driver. The source driver comprises a plurality of channels and a control module. Each of the plurality of channels comprises an output buffer, an output pad, a driving switch, and a charge sharing switch. The control module is used to control a gate signal of the driving switch or the charge sharing switch in each channel to be changed linearly. By doing so, a peak current generated by the source driver can be lowered to reduce the electromagnetic interference (EMI). | 07-01-2010 |
| 20110122102 | Driving Circuit and Output Buffer - An output buffer including a first switch circuit and a buffer is provided. The first switch circuit receives first and second input signals. The buffer circuit includes first and second input stages, first and second output stages and a second switch circuit. The first and the second input stages are coupled to the first switch circuit. The first and the second output stages are coupled to the second switch circuit. The second switch circuit, coupled to the first and the second input stages and the first and the second output stages, selectively couples one of first and the second input stages to the first output stage and selectively couples the other to the second output stage. The first switch circuit further selectively provides one of the first and the second input signals to the first input stage and selectively provides the other to the second input stage. | 05-26-2011 |
| 20120176168 | SIGNAL CIRCUIT - A signal circuit includes a clock terminal for transmitting a reference clock and a data terminal for transmitting an input/output data. In an embodiment, the frequency of the reference clock is one-eighth of the bit rate of the input/output data. | 07-12-2012 |
| 20120249244 | OUTPUT BUFFER OF SOURCE DRIVER - An output buffer of a source driver is disclosed. The output buffer includes a buffer input, a buffer output, a differential input stage, a bias current source, an output stage, a compensation capacitor, and a comparator. The output stage and the comparator are both operated between an analog supply voltage (AVDD) and a half analog supply voltage (HAVDD), or both operated between the half analog supply voltage (HAVDD) and a ground voltage. The comparator compares an input signal with an output signal and outputs a control signal to the bias current source according to the compared result. | 10-04-2012 |
| 20120249245 | OUTPUT BUFFER OF SOURCE DRIVER - An output buffer of a source driver is disclosed. The output buffer includes a buffer input, a buffer output, a differential input stage, a bias current source, an output stage, a compensation capacitor, and a comparator. The output stage and the comparator are both operated between an analog supply voltage (AVDD) and a ground voltage (AGND). The comparator compares an input voltage and an output voltage and outputs a control signal to the bias current source according to the compared result to control a bias current outputted by the bias current source to enhance the slew rate of the output buffer. | 10-04-2012 |
