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Liang, Hsinchu City
Chao-Hu Liang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090107527 | METHOD OF CLEANING TRANSPARENT DEVICE IN A THERMAL PROCESS APPARATUS, THERMAL PROCESS APPARATUS AND PROCESS USING THE SAME THERMAL PROCESS APPARATUS - A method of cleaning a transparent device in a thermal process apparatus, wherein the transparent device is disposed in a chamber of a thermal process apparatus, and the transparent device includes a wafer holder for carry a wafer disposed under the transparent device, and an energy source output device disposed above the transparent device in the chamber, is provided. The method of the present invention includes performing a surface treatment step to clean a surface of the transparent device. | 04-30-2009 |
Chih-Ping Liang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080203935 | Limited current circuit for electro-luminescent lamp inverter - A current limiting device includes a constant current source circuit constructed and arranged to be connected to a direct current input voltage source and to regulate electrical current and a resonance source circuit receiving current from the constant current source circuit. The resonance source circuit is constructed and arranged to be electrically connected with an electro-luminescent (EL) lamp so that the EL lamp receives alternating current. The constant current source circuit and the resonance source circuit are constructed and arranged such that when current flows from the constant current source circuit to the resonance source circuit and to the EL lamp, a maximum peak current received by a user contacting an output of the device or contacting the EL lamp is less than about 0.7 mA. | 08-28-2008 |
| 20080265792 | Constant Brightness Control For Electro-Luminescent Lamp - A ballast ( | 10-30-2008 |
| 20090146574 | Safety circuit for electro-luminescent lamp ballast - A safety circuit is provided for a ballast of an electro-luminescent (EL) lamp. The EL lamp had an electrical ground shield on at least a portion thereof and has a separate ground lead. The ballast is an isolated ballast with a line input being isolated from an output. The ballast is constructed and arranged to be electrically connected with the separate ground lead. The circuit includes a current sensing structure constructed and arranged to connect between the separate ground lead and a potential ground of the ballast. In the event a user contacts the EL lamp to replace the EL lamp or contacts a defective EL lamp, the ballast is shut down based on a value of current sensed by the current sensing structure. | 06-11-2009 |
| 20100237804 | CONSTANT BRIGHTNESS CONTROL FOR ELECTROLUMINESCENT LAMP - A ballast ( | 09-23-2010 |
Ching-Feng Liang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110103303 | WIRELESS COMMUNICATION SYSTEM AND ROUTING METHOD FOR PACKET SWITCHING SERVICE, FEMTO AP USING THE ROUTING METHOD - A wireless communication system, a routing method for a packet switched service, and a Femto AP (FAP) using the routing method are provided. The wireless communication system may include a core network, a broadband IP network, a FAP and at least a user equipment (UE). The UE connects the core network through the FAP and the broadband IP network. The routing method is as follows. The FAP may evaluate a request of the packet switched service sent by the UE, and may reply an accept message to the UE. The accept message may include a FAP address. The UE may use the FAP address to send a packet switching data to the FAP in order to obtain the packet switched service. The FAP may directly conduct the packet switched service with a packet switched service supply end through the broadband IP network without routing through the core network. | 05-05-2011 |
Fan-Kuei Liang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090278439 | Lamp Tube having Bent Segments - A lamp tube includes a lamp tube body, which are formed with bent segments by being heated, bent and then cooled at potions thereof desired to be bent. In this manner, luminance efficiency and lifetime of the lamp tube are effectively improved and prolonged. | 11-12-2009 |
Fu-Sheng Liang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100295996 | CIRCUIT AND METHOD FOR IMAGE PROCESSING - A circuit and a method for image processing are provided. The image processing circuit has an adaptor and a sharpening circuit. The adaptor has a processing unit and a weight generator. The processing unit receives an input video signal, and the input video signal has information of a plurality of pixels. The processing unit processes the input video signal to calculate a color difference value of a target pixel of the pixels. The weight generator generates a weighting signal according to the color difference value. The sharpening circuit performs a sharpening operation on the input video signal according to the weighting signal to generate a sharpened video signal. | 11-25-2010 |
Huang-Chien Liang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100168871 | ARTIFICIAL DURA BIOMEDICAL DEVICE AND BRAIN SURGERY METHOD UTILIZING THE SAME - An artificial dura biomedical device and a brain surgery method utilizing the same are disclosed. The steps includes: fixing an artificial dura to a partial skull; and fixing the partial skull with the artificial dura to a cut hole of a whole skull. The artificial dura biomedical device includes an artificial dura and a connecting element. The connecting element fixes the partial skull with the artificial dura. | 07-01-2010 |
| 20100204508 | DENDRITIC COMPOUND AND USE THEREOF - A dendritic compound of the following structure: PD | 08-12-2010 |
| 20110015654 | SPINAL DISC ANULUS REPAIR METHOD AND APPARATUS - An apparatus for anulus fibrosus repair includes a shaft, a pair of curved suturing needles mounted in parallel on the shaft, and a rotational driving mechanism connected to the shaft, which is configured to rotate the shaft and the pair of needles about a rotation axis of the shaft. Each needle includes a substantially semi-annular body having a proximal end, a distal end, an inner periphery, and an outer periphery, and an arm extending radially inward from the proximal end, in which a concavity is formed in the body proximate to the distal end extending in a direction away from it. Also disclosed is a suturing technique associated with use of the repair apparatus. | 01-20-2011 |
| 20110117199 | FOAMY BIOMATERIAL FOR BIOLOGICAL TISSUE REPAIR - A kit for producing a foamed biocompatible material includes a container configured to sustain a high pressure, and a tissue-repair composition placed in the container. The composition contains a biocompatible material, a liquid carrier, and a gas. The container has an internal pressure of greater than 1 atm and less than 250 atm, and includes a valve and a nuzzle for releasing from the nuzzle a foam formed of the composition upon opening the valve. Methods of producing and applying the biocompatible material are also disclosed. | 05-19-2011 |
| 20110137318 | INJECTABLE THERMOPLASTIC POLYMERS FOR BIOLOGICAL TISSUE REPAIR - A method for filling a bone defect in a subject in need thereof is disclosed. The method includes heating a bone cement composition at a first temperature where the bone cement composition is fluidic, and delivering an effective amount of the fluidic bone cement composition at a second temperature to the bone defect thereby filling the bone defect and allowing the fluidic bone cement composition to solidify, the second temperature being sufficiently high for maintaining the bone cement composition fluidic without causing thermal necrosis. Also disclosed are systems for carrying out the method. | 06-09-2011 |
Keko-Chun Liang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110102081 | AMPLIFIER CIRCUIT WITH OVERSHOOT SUPPRESSION - An amplifier circuit with overshoot suppress scheme including an input amplifier, an output amplifier, and a diode is provided. A first and a second input ends of the output amplifier are coupled to a differential output pair of the input amplifier. A first end of the diode is coupled to an output end of the output amplifier. A second end of the diode is coupled to the first input end of the output amplifier. When the voltage difference between the output and the input ends of the output amplifier is greater then the barrier voltage of the diode, the diode is turned on, so that the output end of the output amplifier is coupled to the input end of the output amplifier. In the transient state, it rapidly smoothes the overshoot signal. In the steady state, the diode is cut off to maintain the normal operation of the operational amplifier. | 05-05-2011 |
Ke-Ming Liang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100021551 | PROCESS FOR PREPARING NANOPARTICLES OF CHITOSAN IN WATER PHASE - A method for preparing chitosan nanoparticles in water phase is provided. The method comprises the following steps: | 01-28-2010 |
Mao-Tse Liang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110050523 | THREE-DIMENSIONAL DUAL-BAND ANTENNA - A three-dimensional dual-band antenna including a first radiation portion, a second radiation portion, a connection portion, an impedance matching portion and a feeding portion is provided. The second radiation portion is located under the radiation portion and parallel with the first radiation portion. The connection portion is connected to the first side of the first radiation portion and extended downward vertically, for connecting the first radiation portion and the second radiation portion. The impedance matching portion is connected to a second side of the first radiation portion and extended downward vertically. The first side and the second side are opposite. The feeding portion is connected to the second side and extended downward vertically. The feeding portion receives a feeding signal. The first and the second radiation portion are operated at the first and the second bandwidth respectively, wherein the second bandwidth is in higher frequency than the first bandwidth. | 03-03-2011 |
Ming-Chung Liang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100308469 | METHOD AND APPARATUS OF FORMING A VIA - The present disclosure provides a semiconductor device that includes, a substrate; a first conductive line located over the substrate and extending along a first axis, the first conductive line having a first length and a first width, the first length being measured along the first axis; a second conductive line located over the first conductive line and extending along a second axis different from the first axis, the second conductive line having a second length and a second width, the second length being measured along the second axis; and a via coupling the first and second conductive lines, the via having an upper surface that contacts the second conductive line and a lower surface that contacts the first conductive line. The via has an approximately straight edge at the upper surface, the straight edge extending along the second axis and being substantially aligned with the second conductive line. | 12-09-2010 |
| 20110070738 | DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a hard mask layer on a material layer and forming a capping layer on the hard mask layer. The capping layer does not react with oxygen gas during a photoresist ashing process. The capping layer is patterned by using a first resist pattern and a second resist pattern as etch masks. After the capping layer is patterned, the hard mask layer is patterned by using the patterned capping layer as an etch mask. | 03-24-2011 |
| 20110108994 | INTEGRATED CIRCUITS AND METHODS FOR FORMING THE INTEGRATED CIRCUITS - A method for forming an integrated circuit includes forming a first dielectric layer over a gate electrode of a transistor. An etch-stop layer is formed over the first dielectric layer. An opening is formed through the first dielectric layer and the etch-stop layer, exposing a source/drain (S/D) region of the transistor. A metal layer is formed in the opening, contacting the S/D region of the transistor. The metal layer has a surface that is at least partially substantially level with a first top surface of the etch-stop layer. A damascene structure is formed and coupled with the metal layer. | 05-12-2011 |
| 20110275218 | DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a hard mask layer on a material layer and forming a capping layer on the hard mask layer. The capping layer does not react with oxygen gas during a photoresist ashing process. The capping layer is patterned by using a first resist pattern and a second resist pattern as etch masks. After the capping layer is patterned, the hard mask layer is patterned by using the patterned capping layer as an etch mask. | 11-10-2011 |
Ming-Jen Liang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110231621 | SYSTEM RECOVERY METHOD, AND STORAGE MEDIUM CONTROLLER AND STORAGE SYSTEM USING THE SAME - A system recovery method is provided. The system recovery method includes grouping storage addresses corresponding to a storage device into a first memory area and a second memory area. The system recovery method also includes storing initial data from a host system into the storage addresses of the first memory area, storing update data for updating the initial data into the storage addresses of the second memory area, and establishing an address corresponding table to record update information corresponding to the storage addresses for storing the update data. The system recovery method further includes erasing the update information from the address corresponding table when the storage device is powered off and re-coupled to the host system. Thereby, the system recovery method can instantly recover system settings. | 09-22-2011 |
Mong-Song Liang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100065921 | SEMICONDUCTOR DEVICE WITH LOCAL INTERCONNECTS - A semiconductor device with local interconnects is provided. The semiconductor device comprises a first gate line structure and a second gate line structure disposed on a substrate and substantially collinear. A first pair of source/drain regions is formed in the substrate on both sides of the first gate line structure and a second pair of source/drain regions is formed in the substrate on both sides of the second gate line structure. A pair of conductive lines is disposed on the substrate on both sides of the first gate line structure and the second gate line structure, such that each conductive line is connected to one of the first pair of source/drain regions and one of the second pair of source/drain regions. | 03-18-2010 |
Sheng-Long Liang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090243254 | Intelligent bicycle and front fork thereof - The present invention provides an intelligent bicycle and the front fork thereof, in which piezoelectric elements are provided on a position of a bicycle front fork or frame having vibration amplitude greater than a set value under a vibration frequency. By converting of direct and converse piezoelectric effect by the designed circuit modules integrated on the front fork or frame, the intelligent bicycle according to the present invention is provided with functions of energy storage and vibration suppression. | 10-01-2009 |
Shen-Long Liang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100310098 | ELECTRET TRANSDUCER WITH SOLAR POWER - The present invention provides an electret transducer with solar power. The provided electrets transducer includes a solar power supply device, an amplifier circuit having a first input terminal coupled to the solar power supply device and a second input terminal coupled to an audio signal input terminal, and an electret loudspeaker coupled to an output terminal of the amplifier circuit. The amplifier circuit receives a first voltage level via the first input terminal and boosts the first voltage level to a second voltage level, and receives a first audio signal via the second input terminal and amplifies the first audio signal to a second audio signal. The electret loudspeaker coupled to the output terminal of the amplifier circuit receives the second audio signal and outputs a sound corresponding to the second audio signal. | 12-09-2010 |
Victor Chiang Liang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100140741 | STRUCTURE OF CAPACITOR SET - A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array. | 06-10-2010 |
| 20100148263 | SEMICONDUCTOR DEVICE STRUCTURE AND FABRICATING METHOD THEREOF - A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate. | 06-17-2010 |
| 20100271750 | CAPACITOR STRUCTURE - A capacitor structure is provided. The capacitor structure comprises a plurality of parallel conductive line levels and a plurality of vias. Each conductive line level comprises first conductive lines parallel to each other and second conductive lines parallel to each other. Also, the first conductive lines on different conductive line levels are aligned to each other and the second conductive lines on different conductive line levels are aligned to each other so as to form first conductive line co-planes and second conductive line co-planes. The vias are located on the conductive line co-planes and between the conductive line levels for connecting the conductive lines on the neighboring conductive line levels. The vias, on a height level of each of the conductive line co-planes, are arranged only on one of the neighboring conductive line co-planes. | 10-28-2010 |
| 20100320540 | SEMICONDUCTOR DEVICE STRUCTURE AND FABRICATING METHOD THEREOF - A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate. | 12-23-2010 |
| 20100327378 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a resistor and a metal gate structure. The substrate has a first area and a second area. The resistor is disposed in the first area, wherein the resistor does not include any metal layer. The metal gate structure is disposed in the second area. | 12-30-2010 |
| 20110156161 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device including a substrate, a first device, a second device and an interlayer dielectric layer is provided. The substrate has a first area and a second area. The first device is disposed in the first area of the substrate and includes a first dielectric layer on the substrate and a metal gate on the first dielectric layer. The second device is in the second area of the substrate and includes a second dielectric layer on the substrate and, a polysilicon layer on the second dielectric layer. It is noted that the height of the polysilicon layer is less than that of the metal gate of the first device. The interlayer dielectric layer covers the second device. | 06-30-2011 |
Wei-Chen Liang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110272783 | SEMICONDUCTOR DEVICE WITH BIPOLAR TRANSISTOR AND CAPACITOR - A semiconductor device with a bipolar transistor and a capacitor that has a down-sized circuit area is presented. During the manufacture of the bipolar transistor, a polysilicon-insulator-polysilicon capacitor, a polysilicon-insulator-metal layer or a metal-insulator-metal capacitor can be formed on the isolating insulator and/or the protective insulator to achieve reduced circuit area, less manufacturing steps and lowered manufacturing cost. | 11-10-2011 |
Wei Yun Liang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110241719 | SOLAR CELL MEASUREMENT SYSTEM AND SOLAR SIMULATOR - A measurement system having a light source, a holding device, and a measurement device. The light source includes a plurality of light emitting diodes (LEDs) configured to generate light beams with different wavelengths, and the emission spectrum of the light source complies with a predetermined standard. The holding device is configured to hold an object under test. The measurement device is configured to measure the electrical properties of the object under test after the object under test is illuminated by the light source. | 10-06-2011 |
Wen-Chung Liang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100147363 | Encapsulant material, crystalline silicon photovoltaic module and thin film photovoltaic module - An encapsulant material with enhanced light reflectivity, a crystalline silicon photovoltaic module and a thin film photovoltaic module are provided. The encapsulant material has a porous structure therein, and an average pore diameter of the porous structure is between several hundreds of nanometers and several hundreds of micrometers, so that the light reflectance of the encapsulant material is improved. Moreover, the encapsulant material is crosslinked by a physical or chemical crosslinking method, so heat resistance thereof is improved. Therefore, the encapsulant material is suitable for the crystalline silicon photovoltaic module and the thin film photovoltaic module, so as to increase power conversion efficiency of these modules. | 06-17-2010 |
Wen-Jya Liang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090261409 | SEMICONDUCTOR DEVICES FOR HIGH POWER APPLICATION - Semiconductor devices for high voltage application are presented. A high power semiconductor device includes a first type doped semiconductor substrate and a second type doped epitaxial layer deposited thereon. A first type doped body region is disposed in the second type doped epitaxial layer. A heavily doped drain region is formed in the second type doped epitaxial layer and isolated from the first type doped body region with an isolation region and a channel. A second type deep heavily doped region extends from the heavily doped drain region to the semiconductor substrate. A pair of inversed type heavily doped source regions is disposed in the first type doped body region. A gate electrode is disposed overlying the channel with a dielectric layer interposed therebetween. The high power semiconductor device is isolated from the other semiconductor devices with a first type deep heavily doped region. | 10-22-2009 |
Yann Hsiung Liang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100097142 | DRIVING CIRCUIT SYSTEM AND METHOD OF ELEVATING SLEW RATE OF OPERATIONAL AMPLIFIER - The invention discloses a driving circuit system and a method of elevating a slew rate of an operational amplifier. The driving circuit system comprises an operational amplifier, a judging module and a bias enhancing module. The operational amplifier has an input stage driven by a bias current. The bias enhancing module is electrically connected to the judging module and the input stage of the operational amplifier respectively. The judging module is used to generate a bias enhancing signal according to an edge-trigger of a control signal. When the bias enhancing module receives the bias enhancing signal, the bias enhancing module provides an additional current, which cooperates with the bias current, for driving the input stage of the operational amplifier, so as to elevating a slew rate of the operational amplifier. | 04-22-2010 |
| 20100164929 | SOURCE DRIVER - The invention discloses a source driver. The source driver comprises a plurality of channels and a control module. Each of the plurality of channels comprises an output buffer, an output pad, a driving switch, and a charge sharing switch. The control module is used to control a gate signal of the driving switch or the charge sharing switch in each channel to be changed linearly. By doing so, a peak current generated by the source driver can be lowered to reduce the electromagnetic interference (EMI). | 07-01-2010 |
| 20110122102 | Driving Circuit and Output Buffer - An output buffer including a first switch circuit and a buffer is provided. The first switch circuit receives first and second input signals. The buffer circuit includes first and second input stages, first and second output stages and a second switch circuit. The first and the second input stages are coupled to the first switch circuit. The first and the second output stages are coupled to the second switch circuit. The second switch circuit, coupled to the first and the second input stages and the first and the second output stages, selectively couples one of first and the second input stages to the first output stage and selectively couples the other to the second output stage. The first switch circuit further selectively provides one of the first and the second input signals to the first input stage and selectively provides the other to the second input stage. | 05-26-2011 |