Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Liang, Hsinchu
Bau-Jy Liang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080231577 | Displaying method - A displaying method for trans-flective type display device is provided. The pixel array of the display device has a selected pixel unit formed by three sub-pixels selected from three basic-color sub-pixels and one enhancement sub-pixel, wherein there is a reflective area within the enhancement sub-pixel. The displaying method includes the following steps. Firstly, an original image having an image data is provided to the display device. Next, when the backlight is turned off, the resolution of the original image is scaled down for obtaining an adjusted image data. Then, another pixel unit consisting of the three basic-color sub-pixels and the enhancement sub-pixel is re-selected, and the driving value of the enhancement sub-pixel is calculated according to the adjusted image data for driving the enhancement sub-pixel. | 09-25-2008 |
Chia-Wen Liang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080237734 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND METHOD OF FABRICATING THE SAME - A complementary metal-oxide-semiconductor (CMOS) transistor comprising a substrate, a first conductive type MOS transistor, a second conductive type MOS transistor, a buffer layer, a first stress layer and a second stress layer is provided. The substrate has a device isolation structure therein that defines a first active area and a second active area. The first conductive type MOS transistor and the second conductive type MOS transistor are respectively disposed in the first active area and the second active area of the substrate. A first nitride spacer of the first conductive type MOS transistor has a thickness greater than that of a second nitride spacer of the second conductive type MOS transistor. The buffer layer is disposed on the first conductive type MOS transistor. The first stress layer is disposed on the buffer layer. The second stress layer is disposed on the second conductive type MOS transistor. | 10-02-2008 |
| 20110156156 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a substrate, a first stress, and a second stress. The substrate has a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The first-type and the second-type are opposite conductivity types with respect to each other. The first stress layer is only disposed on the first-type MOS transistor, and the second stress layer is different from the first stress, and is only disposed on the core second-type MOS transistor. The I/O second-type MOS transistor is a type of I/O MOS transistor and without not noly the first stress layer but also the second stress layer disposed thereon, the core second-type MOS transistor is a type of core MOS transistor. | 06-30-2011 |
Hsiang-Fa Liang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080213354 | Nanoparticles for protein drug delivery - The invention discloses the nanoparticles composed of chitosan, poly-γ-glutamic acid, and at least one bioactive agent characterized with a positive surface charge and their enhanced permeability for paracellular drug delivery. | 09-04-2008 |
| 20090142405 | Nanoparticles for protein drug delivery - The invention discloses the nanoparticles composed of chitosan, poly-glutamic acid, and at least one protein drug or bioactive agent characterized with a positive surface charge and their enhanced permeability for paracellular protein drug and bioactive agent delivery. | 06-04-2009 |
| 20090155374 | Nanoparticles for protein drug delivery - The invention discloses the nanoparticles composed of chitosan, poly-glutamic acid, and at least one protein drug or bioactive agent characterized with a positive surface charge and their enhanced permeability for paracellular protein drug and bioactive agent delivery. | 06-18-2009 |
| 20090202628 | Nanoparticles for protein drug delivery - The invention discloses the nanoparticles composed of chitosan, poly-glutamic acid, and at least one protein drug or bioactive agent characterized with a positive surface charge and their enhanced permeability for paracellular protein drug and bioactive agent delivery. | 08-13-2009 |
| 20100330167 | Nanoparticles for protein drug delivery - The invention discloses the nanoparticles composed of chitosan, poly-γ-glutamic acid, and at least one bioactive agent characterized with a positive surface charge and their enhanced permeability for paracellular drug delivery. | 12-30-2010 |
Kuang-Heng Liang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100309111 | Electrophoretic Display Panel - An electrophoretic display panel includes a first substrate and an electrophoretic layer disposed on the first substrate. The first substrate includes a plurality of pixel areas. Each of the pixel areas has a first electrode and a second electrode formed therein. The first electrode is electrically insulated with the second electrode. The electrophoretic display panel has better light utility efficiency. | 12-09-2010 |
Li-Han Liang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110305269 | DEVICE AND METHOD FOR RECEIVER-EQUALIZER CALIBRATION - The disclosure is a device and a method for receiver-equalizer calibration, in which the device includes an adaptive filter, a Clock Data Recovery (CDR) unit, an adaptive control unit and a run length encoding unit. The adaptive filter receives a channel signal, calibrates the channel signal according to a filter control signal and compensates the channel signal to obtain a compensative signal. The CDR unit receives the compensative signal to generate a sampling clock signal, a data signal and a transition sampling signal. The run length encoding unit receives the data signal and run-length encodes the data signal to generate first code data and second code data. The adaptive control unit receives the first code data, the second code data, the data signal and the transition sampling signal, and performs weight calculation to adjust the filter control signal. | 12-15-2011 |
Ming-Chung Liang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080311756 | Method for Fabricating Low-k Dielectric and Cu Interconnect - A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch. | 12-18-2008 |
Mong-Song Liang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080242108 | Method for fabricating semiconductor device - A method for fabricating a semiconductor device is disclosed. The method includes providing a first chamber and a second chamber. The first chamber and the second chamber are connected by a pressure differential unit, for depositing a metallic film over a substrate in the first chamber, transferring the substrate to the second chamber via the pressure differential unit without exposing the substrate to the ambient environment, and depositing a silicon-containing film on the metallic film in the second chamber. | 10-02-2008 |
| 20080254588 | METHODS FOR FORMING TRANSISTORS WITH HIGH-K DIELECTRIC LAYERS AND TRANSISTORS FORMED THEREFROM - A method for forming a semiconductor structure includes forming a gate dielectric layer over a substrate. A top surface of the gate dielectric layer is treated so as to at least partially nitridize the gate dielectric layer. The treated gate dielectric layer is thermally treated with an oxygen-containing precursor such that the at least partially nitridized gate dielectric layer has a nitrogen concentration between about 0.5 atomic percentage (at. %) and about 20 at %. | 10-16-2008 |
| 20100117190 | FUSE STRUCTURE FOR INTERGRATED CIRCUIT DEVICES - A fuse structure for an IC device and methods of fabricating the structure are provided. The fuse structure comprises a metal-containing conductive strip formed over a portion of a semiconductor substrate. A dielectric layer is formed over the semiconductor substrate, covering the conductive strip. A first interconnect and a second interconnect are formed in vias extending through the dielectric layer, each physically and electrically connecting to a part of the conductive layer. First and second wiring structures are formed over the dielectric layer in electrical contact with the first and second interconnects respectively. The contact area between one of the interconnects and the strip is chosen so that electromigration will occur when a pre-selected current is applied to the fuse structure. | 05-13-2010 |
| 20100285658 | INTEGRATING A FIRST CONTACT STRUCTURE IN A GATE LAST PROCESS - A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact. | 11-11-2010 |
Pi-Hui Liang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090306174 | Novel Five-Membered Iminocyclitol Derivatives as Selective and Potent Glycosidase Inhibitors: New Structures for Antivirals and Osteoarthritis Therapeutics - Novel 5-membered iminocyclitol derivatives were found to be a potent and selective inhibitors of the glycoprotein processing α- and β-glucosidase which were further found to be active antiviral agents against Japanese encephalitis virus, dengue virus serotype 2 (DEN-2), human SARS coronavirus and human β-hexosaminidase, a new target for development of osteoarthritis therapeutics. | 12-10-2009 |
Shih-Chang Liang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100094435 | Accumulative Method For Estimating Velocity Limitation - A method for controlling acceleration and deceleration before interpolating is provided. The method comprises steps of previewing and analyzing a processing program to estimate a limitation of a processing velocity, which comprises providing the processing program including a pathway formed by plural blocks; unitizing the motion vector of each block into the unit vector | 04-15-2010 |
Ting Wei Liang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100059213 | HEAT DISSIPATING STRUCTURE AND METHOD OF FORMING THE SAME - A forming method for a heat dissipating structure is provided. According to the method, an extrudate is formed by extrution molding, wherein the extrudate includes protruding bending portions extending in parallel. Fins are extruded monolithically on the bending portions. One or more cut channels are formed by cutting the fins and the extrudate with a cutting tool. The cutting tool cuts the fins for forming a notch on each fin at first, and then cuts the bending portions for forming a cut-through slot on each bending portion, wherein each cut-through slot is formed for cooling air flowing through two side of the extrudate. By cutting the bending portions and the fins by the cutting tool at the same time, a large number of cut-through slots are formed in despite of the existence of the fins, and the performance of heat dissipation is enhanced. | 03-11-2010 |