| Patent application number | Description | Published |
| 20090077460 | SYNCHRONIZING SLIDE SHOW EVENTS WITH AUDIO - Technologies are described herein for synchronizing slide show events with audio. Data defining one or more animation events, slide transitions, or visual effects and an audio file to be played during the defined events is received. The audio file is processed to identify the audio events contained therein. Once the audio events in the audio file have been identified, the defined animation events are synchronized to the identified audio events using an audio synchronization scheme that includes data defining how the audio events are to be synchronized to the animation events. A user interface may be provided that allows a user to select an audio synchronization scheme to be applied to a presentation. A user interface may also be provided that allows a user to visually associate an animation event with any audio event identified within an audio file. | 03-19-2009 |
| 20090079744 | ANIMATING OBJECTS USING A DECLARATIVE ANIMATION SCHEME - Technologies are described herein for animating objects through the use of animation schemes. An animation scheme is defined using a declarative language that includes instructions defining the animations and/or visual effects to be applied to one or more objects and how the animations or visual effects should be applied. The animation scheme may include rules which, when evaluated, define how the objects are to be animated. An animation scheme engine is also provided for evaluating an animation scheme along with other factors to apply the appropriate animation to each of the objects. The animation scheme engine retrieves an animation scheme and data regarding the objects. The animation scheme engine then evaluates the animation scheme along with the data regarding the objects to identify the animation to be applied to each object. The identified animations and visual effects are then applied to the objects. | 03-26-2009 |
| 20100077319 | Presentation Facilitation - Multiple schemes and techniques for facilitating presentations with an interactive application are described. For example, an interactive application provides a console view overlay for integrating multiple productivity applications into a graphical user interface (GUI) window. An interactive application can also share a selected display portion of the console view overlay with other interactive applications. As another example, presenters and other audience members can draw on the selected display portion being shared, and the drawn graphics are synchronously displayed by the other interactive applications. Interactive applications, as directed by their users, can join various member groups and specific presentations thereof. Moreover, a user may share content in accordance with membership grouping. | 03-25-2010 |
| 20100156911 | TRIGGERING ANIMATION ACTIONS AND MEDIA OBJECT ACTIONS - A request may be received to trigger an animation action in response to reaching a bookmark during playback of a media object. In response to the request, data is stored defining a new animation timeline configured to perform the animation action when playback of the media object reaches the bookmark. When the media object is played back, a determination is made as to whether the bookmark has been encountered. If the bookmark is encountered, the new animation timeline is started, thereby triggering the specified animation action. An animation action may also be added to an animation timeline that triggers a media object action at a location within a media object. When the animation action is encountered during playback of the animation timeline, the specified media object action is performed on the associated media object. | 06-24-2010 |
| 20100169753 | MEDIA PORTABILITY AND COMPATIBILITY FOR DIFFERENT DESTINATION PLATFORMS - Tools and techniques for media portability and compatibility for different destination platforms are provided. These tools may receive commands to launch a media portability capability, and may receive source media as input for transformation. These tools may also receive indications of profile settings for specifying how to transform the source media for enhanced portability on destination systems for playback. The source media may be transformed in response to the profile setting, with the transformed media inserted into a document. The tools may then distribute the document to the destination system for playback | 07-01-2010 |
| 20100275123 | Media Timeline Interaction - Media timeline interaction may be provided. An electronic presentation may comprise a media object. A user may select the media object within a presentation application and use an on-object user interface in conjunction with the application's user interface to modify the media object. The user may also display the modified media object within the presentation application. | 10-28-2010 |
| 20110314361 | GENERATING RECOMMENDATIONS FOR IMPROVING A PRESENTATION DOCUMENT - User actions, content, and other elements related to a presentation document are received. These elements are analyzed to generate recommendations for improving a presentation document. The presentation document may be modified in accordance with the recommendations. | 12-22-2011 |
| Patent application number | Description | Published |
| 20090174885 | Sensor And Method Utilizing Multiple Optical Interferometers - Disclosed is a low-cost high-resolution compact accelerometer which utilizes multiple self-mixing optical interferometers. The device is also a micro-opto-electro-mechanical systems (MOEMS) sensor. The interferometers are used to detect acceleration as well as monitor the wavelength, temperature, and refractive index and perform differential measurements. In addition, photodetectors are employed to monitor the input optical power. | 07-09-2009 |
| 20090195789 | Biosensing Apparatus And Method Using Optical Interference - A label-free interferometric biosensor is disclosed which is based on the self-mixing optical interferometer. Inside the biosensor, an incoming beam is divided into two beam portions which pass through a channel and bio materials, respectively. Interference of the portions is realized by the self-mixing effect and used to detect existence of an analyte, such as DNA or protein molecules. The label-free biosensor is compact and can be made on a chip using the semiconductor technology. It is also convenient to use due to moderate alignment requirement. Furthermore, an array of the interferometers fabricated on a chip enables high-throughput and highly parallel measurements. | 08-06-2009 |
| 20110310394 | Compact Surface Plasmon Resonance Apparatus And Method - A miniaturized surface plasmon resonance (SPR) sensor is introduced for on-chip applications. The sensor's sensing surface is arranged in between a light source and detector. The structure facilitates building a SPR device on a chip. In one embodiment, a prism and light source are placed on top of a detector chip. In another embodiment, a self-mixing interferometer is incorporated to enable highly sensitive phase measurement. Other embodiments include SPR systems with integrated optical power monitors or on-chip microfluidic SPR systems. | 12-22-2011 |
| Patent application number | Description | Published |
| 20080313053 | PAYMENT SERVICE - A method and system to offer a payment service to a consumer user. The system receives a check-out request from the consumer user of an electronic storefront. The check-out request is for purchase one or more products from the electronic storefront. The system determines whether to offer a payment service to the consumer user by identifying whether the consumer user is authorized to use the payment service to make purchases from the electronic storefront. Finally, the system serves a web-based check-out interface to a client used by the consumer user. The check-out interface includes an offer to the consumer user to use the payment service. Specifically, the offer includes an option to enable the consumer user to make payment for the one or more products via the payment service. | 12-18-2008 |
| 20100057589 | PAYMENT SERVICE TO EFFICIENTLY ENABLE ELECTRONIC PAYMENT - A method to redirect a browser client is disclosed. The method comprises serving a first web page including a check-out option and receiving a check-out request from a consumer user of an electronic storefront web site. The check-out request is to purchase a product. In response to the check-out request the browser client is redirected to a web page hosted by a payment service web site. The payment service web site stores information that includes a return URL that corresponds to a web-based interface that is hosted by the electronic storefront web site. The redirection further includes a comparison of the return URL in the stored information to a return URL that corresponds to the web-based interface that is hosted by the electronic storefront web site. The comparison is to determine whether redirection to the web-based interface hosted by the electronic storefront web site should be performed. | 03-04-2010 |
| 20100325042 | PAYMENT SERVICE TO EFFICIENTLY ENABLE ELECTRONIC PAYMENT - A method to redirect a browser client is disclosed. The method comprises storing information at a payment service web site that includes a return URL (uniform resource locator) corresponding to a web-based interface hosted by a merchant web site. Next, the method comprise extracting the return URL embedded in the information and comparing, the return URL to a reference return URL corresponding to the web-based interface hosted by the merchant web site. Finally, the method comprises identifying the return URL matches the reference return URL and redirecting the browser client to the web-based interface hosted by the merchant web site responsive to the identifying the match. | 12-23-2010 |
| 20110246367 | Payment service to efficiently enable electronic payment - A method to forward a browser client is disclosed. The method comprises storing information at a payment service server. The information includes a return network address corresponding to a interface hosted by a merchant server. Next, the method performs the step of comparing the return network address that is included in the information to a reference return network address corresponding to the interface hosted by the merchant server and identifying whether the return network address matches the reference return network address. Finally, the method comprises forwarding the browser client to the interface hosted by the merchant server responsive to the identifying the match. | 10-06-2011 |
| Patent application number | Description | Published |
| 20100250414 | INTER-LAYER PARAMETER LIAISON SYSTEMS AND METHODS - An exemplary method includes generating an access record associated with a data session provided by at least one access layer element over an access network, generating an application record associated with an application provided by at least one application layer element over the access network, transmitting data representative of a correlation parameter associated with application from the at least one application layer element to the at least one access layer element via an inter-layer liaison subsystem, and inserting the correlation parameter associated with application and received from the at least one application layer element via the inter-layer liaison subsystem in the access record. In some examples, the method further includes correlating the access record and the application record based on the correlation parameter associated with the application. Other exemplary inter-layer parameter liaison methods and systems are also disclosed. | 09-30-2010 |
| 20110058658 | EMERGENCY CALLS IN INTERNET PROTOCOL MULTIMEDIA SUBSYSTEM (IMS) OVER EVOLVED PACKET CORE (EPC) NETWORKS - A device receives an emergency call invite generated by a user device associated with an Internet protocol (IP) multimedia subsystem (IMS) media gateway, and forwards the emergency call invite to a location resource function/route determination function (LRF/RDF) device for determining public safety answering point (PSAP) routing information. The device receives, from the LRF/RDF device, the PSAP routing information based on the emergency call invite, and routes the emergency call invite to a particular PSAP based on the PSAP routing information. If the emergency call invite is routed to a legacy PSAP, the emergency call is routed to the legacy PSAP via legacy mobile switching center (MSC) direct trunks. If the emergency call invite is routed to an IP PSAP, the emergency call is routed to the IP PSAP via an IP connection. | 03-10-2011 |
| 20110141947 | INTEGRATED LAWFUL INTERCEPT FOR INTERNET PROTOCOL MULTIMEDIA SUBSYSTEM (IMS) OVER EVOLVED PACKET CORE (EPC) - A method and a system provide integrated lawful intercept, for IMS over an Evolved Packet Core (EPC), for both packet data and session initiation protocol (SIP)-based applications. The system includes a device that receives a lawful intercept request from a law enforcement agency, and determines whether a packet data lawful intercept or a SIP-based applications (SBA) lawful intercept is requested by the lawful intercept request. The device also provisions, when a packet data lawful intercept is requested by the lawful intercept request, a policy control and charging rules function (PCRF) and a packet data network (PDN) gateway (PGW) for the packet data lawful intercept. The device further provisions, when a SBA lawful intercept is requested, a proxy call session control function (P-CSCF), a serving-CSCF (S-CSCF), and a session border controller (SBC) for the SBA lawful intercept. | 06-16-2011 |
| 20110151865 | INTER-NETWORK PROFILE REPOSITORY INTERWORKING SYSTEMS AND METHODS - Exemplary inter-network profile repository interworking systems and methods are disclosed. An exemplary system includes an interface facility that interfaces with a home subscriber server (“HSS”) of a long term evolution (“LTE”) communications network and a home location register (“HLR”) of an alternate communications network, the HSS and the HLR maintaining separate profiles associated with a user device configured to access the LTE communications network and the alternate communications network. The exemplary system further includes a synchronization facility communicatively coupled to the interface facility and that synchronizes profile data associated with the user device across the separate profiles maintained by the HSS and the HLR. Corresponding systems and methods are also disclosed. | 06-23-2011 |
| 20110230195 | LOCATION-BASED ROUTING OF IMS CALLS THROUGH FEMTOCELLS - Location-based calling may be provided for callers that connect to a wireless network using femtocells. A network device may receive a call initiation message including an identifier of a femtocell through which the call was placed. The network device may obtain an identifier of a macro cell base station that serves a geographical coverage area that includes the femtocell and replace the identifier of the femtocell, in the message, with the identifier of the macro cell base station, to obtain a modified message. The modified message may be forwarded through the network to be processed as if the caller placed the location-based call through the macro cell base station. | 09-22-2011 |
| 20110249666 | LOCATION BASED ROUTING - A method may include receiving a session initiation protocol (SIP) Invite message associated with a call and determining that the call involves location based processing. The method may also include identifying location information associated with the call based on header information included in the SIP Invite message and identifying a location ID based on the location information. The method may further include modifying the SIP Invite message to include the location ID, identifying a call type associated with the call and identifying a mobile switching center to which the SIP Invite message is to be forwarded based on the call type and the location information. | 10-13-2011 |
| 20110282931 | DYNAMIC INTERNET PROTOCOL REGISTRY FOR MOBILE INTERNET PROTOCOL BASED COMMUNICATIONS - A server device configured to store an Internet protocol (IP) registry, the registry includes information for a user device, the information includes particular identifiers for the user device, an IP address for the user device, and a particular access point name (APN), where the particular APN corresponds to a service, an application, a network, or data used by the user device; receive a query that includes identifiers and an APN; perform, using the IP registry, an operation to identify the information, for the user device, based on the identifiers and the APN; obtain the information for the user device, when the identifiers match the particular identifiers stored in the IP registry and when the APN matches the particular APN stored in the IP registry; and send, to an application server, the information for the user device, where the IP address permits the application server to communicate with the user device. | 11-17-2011 |
| Patent application number | Description | Published |
| 20090041137 | INDIVIDUAL INTERLEAVING OF DATA STREAMS FOR MIMO TRANSMISSION - The present invention, generally speaking, provides interleavers and methods of interleaving that satisfy the need for backward compatibility while effectively addressing competing design objectives. In accordance with one aspect of the invention, data is transmitted using a number of transmit antennas greater than an expected number of receive antennas. At least one pair of transmit antennas (ant′_1, ant′_) is formed, and multiple second data streams ( | 02-12-2009 |
| 20090067524 | GUARD INTERVAL LENGHT SELECTION IN AN OFDM SYSTEMS BASED ON COHERENCE BANDWIDTH OF THE CHANNEL - A system, apparatus and methods are described that identify a maximum cyclic delay and corresponding cyclic prefix for a multi-path communications channel. In one embodiment, the maximum cyclic delay ( | 03-12-2009 |
| 20090074091 | INDIVIDUAL INTERLEAVING OF DATA STREAMS FOR MIMO TRANSMISSION - The present invention, generally speaking, provides interleavers and methods of interleaving that satisfy the need for backward compatibility while effectively addressing competing design objectives. In accordance with one aspect of the invention, data is transmitted using a number of transmit antennas greater than an expected number of receive antennas. At least one pair of transmit antennas is formed, and multiple second data streams are formed from a first data stream, successive bits in said first data stream being assigned to different ones of said second data streams. Block interleaving of multiple respective ones of said second data streams is individually performed. During successive transmission intervals, the pair of transmit antennas is used to transmit a pair of data symbols taken from different ones of said second data streams, followed by an equivalent transformed pair of data symbols. | 03-19-2009 |
| 20090080555 | GUARD INTERVAL LENGHT SELECTION IN AN OFDM SYSTEMS BASED ON COHERENCE BANDWIDTH OF THE CHANNEL - A system, apparatus and methods are described that select a guard interval length ( | 03-26-2009 |
| 20090190682 | SYSTEM AND METHOD FOR MAXIMUM LIKELIHOOD DECODING IN MULTIPLE OUT WIRELESS COMMUNICATION SYSTEMS - A system and method for a simplified Maximum Likelihood (ML) decoding ( | 07-30-2009 |
| Patent application number | Description | Published |
| 20080198774 | Superframe Having Increased Data Transmission Efficiency - A TDD/TDMA wireless superframe includes a slot having a plurality of OFDM symbols. A guard time interval is arranged after the slot containing the OFDM symbols. There are a plurality of packets arranged subsequent to the guard time interval. A majority of the plurality packets comprise payload frames that are dynamically assigned in concatenation so as to provide access to/from one or more legacy devices operating in a LAN environment under a different protocol. The TDD/TDMA protocol is compatible with existing legacy devices under CSMA/CA. When there is at least one legacy device and one non-legacy device receiving communication, the legacy device is provided communication by enabling the Dynamic Contention packet service, with both the legacy device and non-legacy device receiving communications in the same frequency band. | 08-21-2008 |
| 20090009258 | Enhanced Spectral Keying for Wireless Ultra Wideband Communications - Methods provide for the amount of information encoded by spectral keying into a UWB symbol having a plurality of modulation symbol times, to be increased by operating two or more frequency band carriers simultaneously during at least one of a plurality of modulation symbol times. In one aspect of the present invention, once a frequency resource, such as a carrier, has been used during a given modulation symbol time, those frequency resources are not used again within that UWB symbol. A method of transmitting symbols, includes providing ( | 01-08-2009 |
| 20090313388 | Wireless communication networks based on existing digital broadcasting protocols - A system, apparatus and method are described for transforming an existing broadcasting protocol to a wireless communication networks. Since the initial frequency band is unknown between the server and the client, a protocol is proposed to synchronize the client with the server first in frequency band and second in time. Once the synchronization is done, any message exchanging protocols can facilitate communications. For example, several packets in the broadcasting protocols can be aggregated to form a frame structure. The same protocol can be used when there is a repeater between the server and the client. For video application, a rendering device such as a TV could be controlled by the client via an interface such as infrared. The rendering device can be automatically tuned to the server's transmit frequency automatically by the client without user's intervention. | 12-17-2009 |
| Patent application number | Description | Published |
| 20090043736 | EFFICIENT TUPLE EXTRACTION FROM STREAMING XML DATA - A method and apparatus are disclosed for querying streaming extensible markup language (XML) data comprising: routing elements to query nodes, the elements derived from the streaming extensible markup language data; filtering out elements not conforming to one or more predetermined path query patterns; adding remaining elements to one or more dynamic element lists; accessing a decision table to select and return a query node related to a cursor element from the dynamic element lists; and processing the cursor element related to the returned query node to produce an extracted tuple output. | 02-12-2009 |
| 20090043806 | EFFICIENT TUPLE EXTRACTION FROM STREAMING XML DATA - A method and apparatus are disclosed for querying streaming extensible markup language (XML) data comprising: routing elements to query nodes, the elements derived from the streaming extensible markup language data; filtering out elements not conforming to one or more predetermined path query patterns; adding remaining elements to one or more dynamic element lists; accessing a decision table to select and return a query node related to a cursor element from the dynamic element lists; and processing the cursor element related to the returned query node to produce an extracted tuple output. | 02-12-2009 |
| 20090070313 | ADAPTIVELY REORDERING JOINS DURING QUERY EXECUTION - A method is disclosed for executing a predetermined query plan, the method comprising: executing a portion of the query plan; providing a reordered query plan; comparing ranking metrics for the query plans; and executing the query plan having the lower ranking metric. | 03-12-2009 |
| 20110184933 | JOIN ALGORITHMS OVER FULL TEXT INDEXES - According to one embodiment of the present invention, a method for processing join predicates in full-text indexes is provided. The method includes evaluating local predicates of an outer full text index to generate a first posting list of documents. For each document in the first posting list, the value of a join attribute is determined and an inner full text index is probed to obtain a second posting list of documents containing one of the join attributes determined for each document. Local predicates of an inner full text index are evaluated to generate a third posting list of documents, and the second posting list is merged with the third posting list to generate a merge list of documents. Documents in the first posting list may be paired up with documents in the merge list. | 07-28-2011 |
| Patent application number | Description | Published |
| 20080313357 | MULTIPLE CHANNEL DATA BUS CONTROL FOR VIDEO PROCESSING - A method, apparatus, computer medium, and other embodiments for selectably enabling a plurality of data transfer modes along one or more channels are described. In one embodiment, data transfer between a first device and a second device is controlled based on selecting a combination of access and operation modes. In another embodiment, a video processing system capable of selectably enabling a plurality of data transfer modes along one or more channels is described. | 12-18-2008 |
| 20100026331 | Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies - Enhanced microfabricated spring contact structures and associated methods, e.g. such as for electrical contactors and interposers, comprise improvements to spring structures that extend from the substrate surface, and/or improvements to structures on or within the support substrate. Improved spring structures and processes comprise embodiments having selectively formed and etched, coated and/or plated regions, which are optionally further processed through planarization and/or annealment. Enhanced solder connections and associated processes provide a gap between substrates for componentry, and or improved manufacturing techniques using distributed spacers. Enhanced probe card assembly structures and processes provide improved planarization adjustment and thermal stability. | 02-04-2010 |
| 20120023730 | CONSTRUCTION STRUCTURES AND MANUFACTURING PROCESSES FOR INTEGRATED CIRCUIT WAFER PROBE CARD ASSEMBLIES - Enhanced microfabricated spring contact structures and associated methods, e.g. such as for electrical contactors and interposers, comprise improvements to spring structures that extend from the substrate surface, and/or improvements to structures on or within the support substrate. Improved spring structures and processes comprise embodiments having selectively formed and etched, coated and/or plated regions, which are optionally further processed through planarization and/or annealment. Enhanced solder connections and associated processes provide a gap between substrates for componentry, and or improved manufacturing techniques using distributed spacers. Enhanced probe card assembly structures and processes provide improved planarization adjustment and thermal stability. | 02-02-2012 |
| Patent application number | Description | Published |
| 20080307270 | EMERGING BAD BLOCK DETECTION - Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques can be embodied in a device driver of an operating system. Errors are tracked during read operations. If sufficient errors are observed during read operations, the block is then retired when it is requested to be erased or a page of the block is to be written. One embodiment is a technique to recover data from uncorrectable errors. For example, a read mode can be changed to a more reliable read mode to attempt to recover data. One embodiment further returns data from the memory device regardless of whether the data was correctable by decoding of error correction code data or not. | 12-11-2008 |
| 20100287410 | SYSTEMS AND METHODS FOR RETRIEVING DATA - Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques can be embodied in a device driver of an operating system. Errors are tracked during read operations. If sufficient errors are observed during read operations, the block is then retired when it is requested to be erased or a page of the block is to be written. One embodiment is a technique to recover data from uncorrectable errors. For example, a read mode can be changed to a more reliable read mode to attempt to recover data. One embodiment further returns data from the memory device regardless of whether the data was correctable by decoding of error correction code data or not. | 11-11-2010 |
| 20110239061 | SYSTEMS AND METHODS FOR RETRIEVING DATA - Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques can be embodied in a device driver of an operating system. Errors are tracked during read operations. If sufficient errors are observed during read operations, the block is then retired when it is requested to be erased or a page of the block is to be written. One embodiment is a technique to recover data from uncorrectable errors. For example, a read mode can be changed to a more reliable read mode to attempt to recover data. One embodiment further returns data from the memory device regardless of whether the data was correctable by decoding of error correction code data or not. | 09-29-2011 |
| Patent application number | Description | Published |
| 20090289369 | MEMORY DEVICE PERIPHERAL INTERCONNECTS AND METHOD OF MANUFACTURING - An integrated circuit memory device, in one embodiment, includes a substrate and first and second inter-level dielectric layers successively disposed on the substrate. One or more contacts in the peripheral extend through the first inter-level dielectric layer to respective components. One or more vias and a plurality of dummy vias extend through the second inter-level dielectric layer in the peripheral area. Each of the one or more peripheral vias extend to a respective peripheral contact. The peripheral dummy vias are located proximate the peripheral vias. | 11-26-2009 |
| 20100207191 | METHOD AND DEVICE EMPLOYING POLYSILICON SCALING - A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack. | 08-19-2010 |
| 20100276746 | SONOS MEMORY CELLS HAVING NON-UNIFORM TUNNEL OXIDE AND METHODS FOR FABRICATING SAME - Methods for forming a memory cell are disclosed. A method includes forming a source-drain structure in a semiconductor substrate where the source-drain structure includes a rounded top surface and sidewall surfaces. An oxide layer is formed on the top and sidewall surfaces of the source-drain structure. The thickness of the portion of the oxide layer that is formed on the top surface of the source-drain structure is greater than the thickness of the portion of the oxide layer that is formed on the sidewall surfaces of the source-drain structure. | 11-04-2010 |
| 20110057315 | MEMORY DEVICE PERIPHERAL INTERCONNECTS - An integrated circuit memory device, in one embodiment, includes a substrate and first and second inter-level dielectric layers successively disposed on the substrate. One or more contacts in the peripheral extend through the first inter-level dielectric layer to respective components. One or more vias and a plurality of dummy vias extend through the second inter-level dielectric layer in the peripheral area. Each of the one or more peripheral vias extend to a respective peripheral contact. The peripheral dummy vias are located proximate the peripheral vias. | 03-10-2011 |
| Patent application number | Description | Published |
| 20090272881 | Apparatus, method, and system providing pixel having increased fill factor - A method, apparatus, and system providing a pixel having increased fill factor by removing the row select transistor. A reset transistor in the pixel is connected to a column line, and the column line is used alternatively as a pixel readout line and as a voltage supply line for resetting a storage region in the pixel through the resent transistor. | 11-05-2009 |
| 20090302323 | Method and apparatus for providing a low-level interconnect section in an imager device - Imager pixels with low-level interconnect sections, methods of assembling imager pixels with low-level interconnect sections, and systems containing imager pixels with low-level interconnect sections. Imager pixels are formed such that specific interconnections between transistors and other components of an imager array are removed from one or more upper level metallization sections and placed on a low-level interconnect section closer to the photodetector, such that one upper metallization section is eliminated. | 12-10-2009 |
| 20100079646 | Vertical 4-way shared pixel in a single column with internal reset and no row select - A method and apparatus for reducing space and pixel circuit complexity by using a 4-way shared vertically aligned pixels in a same column. The at least four pixels in the pixel circuit share a reset transistor and a source follower transistor, can have a plurality of same colored pixels and a plurality of colors, but do not include a row select transistor. | 04-01-2010 |
| 20110310278 | SYSTEMS AND METHODS FOR ADAPTIVE CONTROL AND DYNAMIC RANGE EXTENSION OF IMAGE SENSORS - Systems and methods are provided for obtaining adaptive exposure control and dynamic range extension of image sensors. In some embodiments, an image sensor of an image system can include a pixel array with one or more clear pixels. The image system can separately control the amount of time that pixels in different lines of the pixel array are exposed to light. As a result, the image system can adjust the exposure times to prevent over-saturation of the clear pixels, while also allowing color pixels of the pixel array to be exposed to light for a longer period of time. In some embodiments, the dynamic range of the image system can be extended through a reconstruction and interpolation process. For example, a signal reconstruction module can extend the dynamic range of one or more green pixels by combining signals associated with green pixels in different lines of the pixel array. | 12-22-2011 |
| Patent application number | Description | Published |
| 20080244359 | Techniques For Correcting Errors Using Iterative Decoding - Techniques are provided for iteratively decoding data recorded on a data storage device. An iterative decoder decodes the data using multiple decoding iterations to correct errors. In multiple iterations of the iterative decoder, a post processing block generates soft information, and a decoder applies a minimum sum decoding algorithm to a low density parity check (LDPC) code to generate extrinsic information based on the soft information and updated soft information. | 10-02-2008 |
| 20090006930 | Techniques For Generating Bit Reliability Information In The Post Processor - A detector generates a detected sequence, and a post processor generates probability values that indicate the likelihood of a plurality of error events in the detected sequence. The post processor partitions the values into first and second subsets. The post processor selects a first most likely value from the first subset of the values and a second most likely value from the second subset of the values. The post processor generates a bit reliability based on the first and the second most likely values. | 01-01-2009 |
| 20090006931 | Techniques For Generating Bit Reliability Information In A Post-Processor Using An Error Correction Constraint - Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the first bit value, finds a second set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the second bit value, selects a first most likely combination of one or more events of the first set and a second most likely combination of one or more events of the second set, and generates a bit reliability based on the first and the second most likely values. | 01-01-2009 |
| 20110029826 | Systems and Methods for Re-using Decoding Parity in a Detector Circuit - Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes receiving an LDPC codeword, and grouping active bits from the LDPC codeword into a series of data bits including one or more user data bits including and at least one LDPC parity bit. The series of data bits satisfies an LDPC parity equation. | 02-03-2011 |
| 20110029835 | Systems and Methods for Quasi-Cyclic LDPC Code Production and Decoding - Various embodiments of the present invention provide systems and methods for generating a parity check matrix used in data processing. As an example, a method for generating a parity check matrix including selecting a non-affiliated variable node; identifying a check node of the lowest degree; connecting a first edge of the non-affiliated variable node to the identified check node; and connecting one or more additional edges of the non-affiliated variable node to check nodes in accordance with a quasi-cyclic constraint associated with a circulant is disclosed. | 02-03-2011 |
| 20110029837 | Systems and Methods for Phase Dependent Data Detection in Iterative Decoding - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes a first data detection circuit that applies a phase dependent data detection algorithm to a data set such that a first output of the first data detection circuit varies depending upon a phase of the data set presented to the first data detection circuit. A first phase of the data set is presented to the first data detection circuit. The circuits further include a decoder circuit that applies a decoding algorithm to the first output to yield a decoded output, and a phase shift circuit that phase shifts the decoded output such that a second phase of the data set is provided as a phase shifted output. A second detection circuit applies a phase dependent data detection algorithm to the phase shifted output such that a second output of the second data detection circuit varies from the first output at least in part due to a different phase of the data set presented to the second data detection circuit. | 02-03-2011 |
| 20110029839 | Systems and Methods for Utilizing Circulant Parity in a Data Processing System - Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes receiving a codeword that has at least a first circulant with a plurality of data bits and a first circulant parity bit, a second circulant with a plurality of data bits and a second circulant parity bit, and one or more codeword parity bits. The methods further include decoding the codeword using the one or more codeword parity bits to access the first circulant and the second circulant, performing a first circulant parity check on the first circulant, and performing a second circulant parity check on the second circulant. | 02-03-2011 |
| 20110167246 | Systems and Methods for Data Detection Including Dynamic Scaling - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a channel detector circuit. The channel detector circuit includes a branch metric calculator circuit that is operable to receive a number of violated checks from a preceding stage, and to scale an intrinsic branch metric using a scalar selected based at least in part on the number of violated checks to yield a scaled intrinsic branch metric. | 07-07-2011 |
| 20110199699 | FREQUENCY-BASED APPROACH FOR DETECTION AND CLASSIFICATION OF HARD-DISC DEFECT REGIONS - In a hard-disc drive read channel, frequency-based measures are generated at two different data frequencies (e.g., 2T and DC) by applying a transform, such as a discrete Fourier transform (DFT), to signal values, such as ADC or equalizer output values, corresponding to, e.g., a 2T data pattern stored on the hard disc. The frequency-based measures are used to detect defect regions on the hard disc and/or to classify defect regions as being due to either thermal asperity (TA) or drop-out media defect (MD). | 08-18-2011 |
| 20110235490 | AMPLITUDE-BASED APPROACH FOR DETECTION AND CLASSIFICATION OF HARD-DISC DEFECT REGIONS - In a hard-disc drive, a defect region on the hard disc is classified as corresponding to either thermal asperity (TA) or media defect (MD) by generating two statistical measures. A first measure (e.g., ∝ | 09-29-2011 |
| 20110264980 | Systems and Methods for Low Density Parity Check Data Decoding - Various embodiments of the present invention provide systems and methods for decoding data. As an example, a data processing circuit is disclosed that includes a multi-tier decoding circuit having a first tier decoding circuit operable to decode portions of an encoded data set exhibiting low row weight, and a second tier decoding circuit operable to decode portions of an encoded data set exhibiting high row weight. | 10-27-2011 |
| 20110264987 | Systems and Methods for Low Density Parity Check Data Encoding - Various embodiments of the present invention provide systems and methods for encoding data. As an example, a data encoding circuit is disclosed that includes a first stage data encoder circuit and a second stage data encoder circuit. The first stage data encoder circuit is operable to provide a first stage output. The first stage data encoder circuit includes a first vector multiplier circuit operable to receive a data input and to multiply the data input by a first sparse matrix to yield a first interim value. The second stage encoder circuit includes a second vector multiplier circuit operable to multiply the first stage output by a second sparse matrix to yield a second interim value. | 10-27-2011 |
| 20110311002 | Turbo-Equalization Methods For Iterative Decoders - Certain embodiments of the present invention are improved turbo-equalization methods for decoding encoded codewords. In one embodiment, in global decoding iteration i, the magnitude values of all decoder-input LLR values (L | 12-22-2011 |