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Li-Ping

Li Ping Lin, Kaohsiung City TW

Patent application numberDescriptionPublished
20120280727POWER-ON RESET CIRCUIT - A power on reset circuit is capable of changing logic level of reset signal at different threshold voltages.11-08-2012
20120306828DRIVING CIRCUIT AND OPERATING METHOD THEREOF - The invention provides a driving circuit applied in a LCD apparatus and operating method thereof. The driving circuit includes at least one first channel, at least one second channel, a timing controller, and a panel driver. The timing controller includes a digital signal switching unit. The digital signal switching unit selectively performs a polarity exchange to a first digital data signal and a second digital data signal according to a control signal. The panel driver includes an analog signal switching unit. The analog signal switching unit performs a switching corresponding to the polarity exchange according to the control signal to make the driving circuit selectively operated under a first operation mode or a second operation mode.12-06-2012

Li Ping Peng, Dongguan CN

Patent application numberDescriptionPublished
20130050877SLIDER, HEAD GIMBAL ASSEMBLY AND DISK DRIVE UNIT WITH THE SAME - A slider includes a substrate having a trailing edge, a leading edge opposite the trailing edge, and an air bearing surface connecting the trailing edge with the leading edge; a read/write transducer formed at the trailing edge; and a coat layer attached on the trailing edge and covering on the read/write transducer. The slider further includes a protection layer for shielding the read/write transducer thereby preventing the read/write transducer from damaging during a laser soldering process. The present invention can prevent the read/write transducer from damaging during the laser bonding process and, in turn improve the reading and writing performance of the slider. The invention also discloses an HGA and a disk drive unit.02-28-2013

Li Ping Wang, Ningbo CN

Patent application numberDescriptionPublished
20080283278Flexible Circuit Substrate - The present invention is directed to a substrate for subsequent eutectic bonding with a subsequently applied metal to provide, or as a precursor to the provision of, a circuit substrate. The circuit substrate comprises a dielectric film and a layer of an oxide or oxides of a metal on the film. The metal oxide layer has been formed by sputtering the metal of the metal oxide or oxides onto a surface of the film in the presence of an inert atmosphere save for at least one reactive gas content to provide the oxygen of the oxides.11-20-2008

Li Ping Wang, Taipei TW

Patent application numberDescriptionPublished
20090314826PACKAGE BOX AND METHOD FOR PACKAGING ARTICLE - The invention discloses a package box and a method for packaging thereof. The package box includes a box-shaped body and a sheet. The box-shaped body has a containing space for placing an article and a first fastening portion. The sheet is used to wrap the box-shaped body and has a first lateral part and a second lateral part. The first lateral part has a first fastening unit, and the second lateral part has a second fastening unit. When the sheet wraps the box-shaped body, the first fastening unit of the sheet and the first fastening portion of the box-shaped body are fastened with each other, and the first fastening unit of the sheet and the second fastening unit of the sheet are fastened with each other.12-24-2009

Li Ping Yang, Beijing CN

Patent application numberDescriptionPublished
20080208857PROCESSING, BROWSING AND EXTRACTING INFORMATION FROM AN ELECTRONIC DOCUMENT - The present invention relates to methods, apparatus and systems for processing an electronic document and its corresponding device. It provides methods for browsing an electronic document and its corresponding browser, and methods for extracting information segments from an electronic document and its corresponding system for the same. An example of a method for processing an electronic document comprises extracting one or more information segments of the domains to which the electronic document relates from the electronic document being written by an author, and correspondingly storing said extracted information segments with said document. Wherein one or more information extraction patterns are used to extract information segments of different domains to which the electronic document relates from said document. And the extracted information segments are verified by the writer so as to ensure its correctness, reliability and readability.08-28-2008
20080222138Method and Apparatus for Constructing a Link Structure Between Documents - A method and computer system for constructing a link structure for T documents. An initial link structure G09-11-2008
20080288535Method, Apparatus and System for Linking Documents - A method, apparatus and system for linking documents, the method comprising the steps of: providing a plurality of clusters in an enterprise intranet, each cluster consists of one or more documents; building a cluster page for each cluster to present the documents in the cluster; and building links between the cluster pages, between the documents, and between the cluster page and the document, based on analysis of the contents of the clusters and the documents. The present invention is useful for building the links between separate documents and may apply a link analyzing algorithm to the search for these documents to implement better search performance within the enterprise intranet.11-20-2008
20090024610COMPUTER AIDED AUTHORING, ELECTRONIC DOCUMENT BROWSING, RETRIEVING, AND SUBSCRIBING AND PUBLISHING - Provides methods, apparatus, and systems for computer aided authoring. Included are: a method for browsing an electronic document, an apparatus for aided authoring, an electronic document browser, a method for retrieving an electronic document, a system for retrieving electronic documents, a method for subscribing and publishing an electronic document as well as a system for subscribing and publishing electronic documents. An example method for computer aided authoring includes: generating one or more topic summaries based on an electronic document while a writer is writing said electronic document, wherein the reliability of the topic summary is ensured by the writer; and saving said topic summary information in correspondence with said electronic document.01-22-2009
20090307217Method, Device and System for Processing, Browsing and Searching an Electronic Documents - A method for processing electronic document and its corresponding device, a method for browsing electronic document and its corresponding browser, as well as a method for searching electronic document and its corresponding searching system are disclosed in the present invention. The method comprises at least the following steps of: generating one or more query according to the content of said document when an author is composing the electronic document; and correspondingly storing information about said one or more query with said electronic document. Wherein the query comprises keywords, keyword string or questions, and the query has passed the verification in order to ensure its reliability.12-10-2009

Patent applications by Li Ping Yang, Beijing CN

Li-Ping Chang, Spring Valley, NY US

Patent application numberDescriptionPublished
20080306131Progesterone receptor modulator and uses thereof - Compounds of the structure:12-11-2008

Li-Ping Chen, Shanghai CN

Patent application numberDescriptionPublished
20110094788PRINTED CIRCUIT BOARD WITH INSULATING AREAS - A printed circuit board includes a substrate including a first surface and a second surface opposite to the first surface, a pair of first pads positioned on the first surface and the second surface, and a plurality of insulating areas. The substrate defines a through hole and a plurality of vias extending from the first surface to the second surface. Each of the pair of first pads surrounds the through hole. The insulating areas are adjacent to the first pad to divide a reference metal layer of the substrate adjacent to the first pads into a plurality of metal strips to reduce heat dissipation area of the reference metal layer adjacent to the first pads. The vias are adjacent to the metal strips to supply extra heat to molten solder on the first surface in a wave-soldering process.04-28-2011

Li-Ping Chen, San Jose, CA US

Patent application numberDescriptionPublished
20090208223FOUR WAVE MIXING SUPPRESSION - Methods, systems and computer program products for countering the effects of four wave mixing are described. In one implementation, a controller can be used to shift an operating wavelength of an optical transmitter away from a zero-dispersion wavelength through which signals of the optical transmitter are transmitted. The controller can perform the shifting process while allowing sufficient margin for division multiplexing and minimal dispersion. The controller may determine an appropriate offset to be used for shifting the operating wavelength without subjecting the signals to a significant increase in undesirable effects such as dispersion, crosstalk and signal distortion which can impact the overall bit-error rate.08-20-2009
20090290880Dispersion Compensation Circuitry and System for Analog Video Transmission With Direct Modulated Laser - An improved precompensation circuit includes a greatly improved differentiator in the dispersion precompensation path, a preprocessor in the dispersion precompensation path for reducing f2−f1 type Composite Second Order (CSO) distortion, and a broadband phase shifter for compensating undesired vector interaction between the laser predistortion and dispersion compensation.11-26-2009
20110210777DISPERSION COMPENSATION CIRCUITRY AND SYSTEM FOR ANALOG VIDEO TRANSMISSION WITH DIRECT MODULATED LASER - An improved precompensation circuit includes a greatly improved differentiator in the dispersion precompensation path, a preprocessor in the dispersion precompensation path for reducing f2−f1 type Composite Second Order (CSO) distortion, and a broadband phase shifter for compensating undesired vector interaction between the laser predistortion and dispersion compensation.09-01-2011
20120027421Four Wave Mixing Suppression - Methods, systems and computer program products for countering the effects of four wave mixing are described. In one implementation, a controller can be used to shift an operating wavelength of an optical transmitter away from a zero-dispersion wavelength through which signals of the optical transmitter are transmitted. The controller can perform the shifting process while allowing sufficient margin for division multiplexing and minimal dispersion. The controller may determine an appropriate offset to be used for shifting the operating wavelength without subjecting the signals to a significant increase in undesirable effects such as dispersion, crosstalk and signal distortion which can impact the overall bit-error rate.02-02-2012

Patent applications by Li-Ping Chen, San Jose, CA US

Li-Ping Chen, Taipei Hsien TW

Patent application numberDescriptionPublished
20090034190AIRFLOW-GUIDING DEVICE AND COMPUTER HAVING SAME - An airflow-guiding device for guiding airflow to heat generating components includes an airflow-guiding shield and at least one airflow-guiding piece rotatable in the airflow-guiding shield. The airflow-guiding piece includes a guiding surface guiding airflow, and a blocking surface blocking airflow. An airflow-guiding position where the guiding surface faces the heat generating components guides airflow thereto, and an airflow-blocking position where the blocking surface faces the airflow blocks the airflow. The airflow-guiding piece rotates between the airflow-guiding position and the airflow-blocking position.02-05-2009

Li-Ping Huang, Taipei TW

Patent application numberDescriptionPublished
20100210086Junction Profile Engineering Using Staged Thermal Annealing - An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.08-19-2010
20100237441Gated Diode with Non-Planar Source Region - A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.09-23-2010

Li-Ping Huang, Taipei City TW

Patent application numberDescriptionPublished
20080237746Gated diode with non-planar source region - A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.10-02-2008
20080242039METHOD OF ENHANCING DOPANT ACTIVATION WITHOUT SUFFERING ADDITIONAL DOPANT DIFFUSION - A method of enhancing dopant activation without suffering additional dopant diffusion, includes forming shallow and lightly-doped source/drain extension regions in a semiconductor substrate, performing a first anneal process on the source/drain extension regions, forming deep and heavily-doped source/drain regions in the substrate adjacent to the source/drain extension regions, and performing a second anneal process on source/drain regions. The first anneal process is a flash anneal process performed for a time of between about 1 millisecond and 3 milliseconds, and the second anneal process is a rapid thermal anneal process performed for a time of between about 1 second and 30 seconds.10-02-2008
20110147765DUMMY STRUCTURE FOR ISOLATING DEVICES IN INTEGRATED CIRCUITS - The present disclosure provides an integrated circuit. The integrated circuit includes a first operational device having a first transistor of a first composition; a second operational device having a second transistor of the first composition; and an isolation transistor disposed between the first and second transistors, the isolation transistor having a second composition different from the first composition.06-23-2011
20120091540STRAINED STRUCTURE OF A P-TYPE FIELD EFFECT TRANSISTOR - In a p-type field effect transistor, a pair of spacers are formed over the top surface of a substrate. A channel recess cavity includes an indentation in the substrate top surface between the pair of spacers. A gate stack has a bottom portion in the channel recess cavity and a top portion extending outside the channel recess cavity. A source/drain (S/D) recess cavity has a bottom surface and sidewalls below the substrate top surface. The S/D recess cavity has a portion extending below the gate stack. A strained material is filled the S/D recess cavity04-19-2012
20120100686METHOD OF FORMING ULTRA-SHALLOW JUNCTIONS IN SEMICONDUCTOR DEVICES - A method of forming ultra-shallow lightly doped source/drain (LDD) regions of a CMOS transistor in a surface of a substrate includes the steps of providing a semiconductor substrate, providing a gate stack on the semiconductor substrate, performing a low temperature pocket implantation process on the substrate, performing a low temperature co-implanted ion implantation process on the substrate, and/or performing a low temperature lightly doped source/drain implantation process on the substrate.04-26-2012
20120319203SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed device comprises a gate structure over a substrate and defining a channel region in the substrate, an epitaxial feature with a first dopant in the substrate, and an epitaxial source/drain feature with a second dopant in the substrate. The epitaxial source/drain feature is farther from the channel region than the epitaxial feature is. The second dopant has an electrical carrier type opposite to the first dopant.12-20-2012

Patent applications by Li-Ping Huang, Taipei City TW

Li-Ping Li, Shenzhen City CN

Patent application numberDescriptionPublished
20090027359STYLUS WITH SUCTION CUP - A stylus includes a suction cup configured for being attached to a user' finger and a touch body mounted on the suction cup. In using this kind of stylus, a user can accomplish an input operation in a portable electronic device by using one hand to hold the portable electronic device and using a finger of the same hand to manipulate the stylus.01-29-2009

Li-Ping Lin, Taipei TW

Patent application numberDescriptionPublished
20090077281KVM CONSOLE CABLE AND MULTI-COMPUTER SYSTEM USING THE SAME - The invention provides KVM console cables, comprising a video connector, a first console connector, a second console connector, a third console connector, a combined connector, and a transmission line. The video connector is utilized to connect to a video monitor. The first, second, and third console connectors are utilized to connect to a first console device, a second console device and third console device, respectively. The combined connector is utilized to connect to a KVM switch. The video connector and the first, second and third console connectors are connected to the combined connector by the transmission line.03-19-2009

Li-Ping Liu, Northridge, CA US

Patent application numberDescriptionPublished
20080234188Antimicrobial Peptides - A method is described for treating a microbial infection with a peptide whose amino acid sequence has a formula selected from the group consisting of:09-25-2008

Li-Ping Liu, Beijing CN

Patent application numberDescriptionPublished
20080247932Method for making colloidal nanocrystals - A method for making colloidal nanocrystals includes the following steps: dissolving a nanocrystal powder in an organic solvent, and achieving a solution A of a concentration of 1-30 mg/ml; dissolving a surfactant in water, and achieving a solution B of a concentration of 0.002-0.05 mmol/ml; mixing the solution A and the solution B in a volume ratio of 1: (5-30), and achieving a mixture; stirring and emulsifying the mixture, until an emulsion C is achieved; removing the organic solvent from the emulsion C, and achieving a deposit; then washing the deposit with deionized water, and achieving colloidal nanocrystals. The present method for making colloidal nanocrystals is economical and timesaving, and has a low toxicity associated therewith. Thus, the method is suitable for industrial mass production. The colloidal nanocrystals made by the present method have a readily controllable size, a narrow size distribution, and good configuration.10-09-2008
20100278721Method for making mesoporous material - A method for making the mesoporous material includes the following steps: dissolving a nanocrystal powder in an organic solvent, and achieving a solution A with concentration of 1-30 mg/ml; dissolving a surfactant in water, and achieving a solution B with an approximate concentration of 0.002-0.05 mol/ml; mixing the solution A and the solution B in a volume ratio of 1: (5-30), and achieving a mixture; stirring and emulsifying the mixture, until an emulsion C is achieved; removing the organic solvent from the emulsion C, and achieving a deposit; washing the deposit with deionized water, and achieving a colloid; and drying and calcining the colloid, and eventually achieving a mesoporous material. The mesoporous material has a large specific surface area, a high porosity, and a narrow diameter distribution.11-04-2010

Li-Ping Weng, Kwei-Shan TW

Patent application numberDescriptionPublished
20110020846Oral cancer biomarker and inspection method using the same - The present invention discloses an oral cancer biomarker and an inspection method using the same. The biomarker is Mca-2 binding protein (Mac-2BP), which can be directly detected in the specimen of the body fluid of a testee, and which can realize a fast and effective clinical diagnosis of oral cancer.01-27-2011
20110021750Oral cancer biomarker and inspection method using the same - The present invention discloses an oral cancer biomarker and an inspection method using the same. The biomarker is Mca-2 binding protein (Mac-2BP), which can be directly detected in the specimen of the body fluid of a testee, and which can realize a fast and effective clinical diagnosis of oral cancer.01-27-2011

Li-Ping Yang, Taipei TW

Patent application numberDescriptionPublished
20090286358Method of fabricating integrated circuits, integrated circuit component mask layout set, and component photomask set - A method of fabricating integrated circuits includes the steps of: a) with reference to a physical design of a hardware unit, preparing an integrated circuit component mask layout set associated with component photomasks suitable for fabricating an array of the hardware units on a wafer; b) preparing the component photomasks with reference to the integrated circuit component mask layout set; c) forming the array of the hardware units and interconnections between adjacent hardware units on the wafer using the component photomasks prepared in step b) ; and d) cutting the wafer along selected ones of the scribe lines so as to form a plurality of integrated circuit dies. Each of the integrated circuit dies is independently selected from a single-type including only one of the hardware units, and a multi-type including a plurality of the hardware units that are interconnected electrically via uncut ones of the conductive paths.11-19-2009