Patent application number | Description | Published |
20120065186 | ANTIMICROBIAL COMPOSITIONS - The present invention relates to antimicrobial compositions and more specifically compositions of quinolone carboxylic acid derivatives. These compositions have improved solubility, stability, and tolerability. These compositions are useful for intravenous administration for treating, preventing, or reducing the risk of infection. | 03-15-2012 |
20120122887 | SOLID STATE FORMS OF A POTENT HCV INHIBITOR - This invention relates to novel sodium salt forms of the following Compound (1), and methods for the preparation thereof, pharmaceutical compositions thereof, and their use in the treatment of Hepatitis C Viral (HCV) infection: | 05-17-2012 |
20120208857 | Pharmaceutical Compositions - The present invention relates to pharmaceutical compositions useful for administration for treating, preventing, or reducing the risk of microbial infections. | 08-16-2012 |
20140057928 | SOLID STATE FORMS OF A POTENT HCV INHIBITOR - This invention relates to novel sodium salt forms of the following Compound (1), and methods for the preparation thereof, pharmaceutical compositions thereof, and their use in the treatment of Hepatitis C Viral (HCV) infection: | 02-27-2014 |
20140088164 | Pharmaceutical Compositions - The present invention relates to pharmaceutical compositions useful for administration for treating, preventing, or reducing the risk of microbial infections. | 03-27-2014 |
20140094463 | Pharmaceutical Compositions - The present invention relates to carrier systems useful for pharmaceutical compositions. These carriers comprise an emulsifier, and also in further embodiments a polymeric dissolution aid. These carriers are useful for delivering pharmaceutical actives such as antimicrobial agents. | 04-03-2014 |
20150366857 | Antimicrobial Compositions with Effervescent Agents - The present invention relates to pharmaceutical compositions comprising a quinolone carboxylic acid derivative antimicrobial agent and an effervescent agent. These compositions have improved gastrointestinal tolerability and/or reduced potential to cause gastrointestinal side effects. These compositions are useful for oral administration, for treating, preventing, or reducing the risk of microbial infections. | 12-24-2015 |
20150366858 | Methods for Treating Infections - The present invention relates to methods for treating, preventing, or reducing the risk of microbial infections while minimizing adverse gastrointestinal effects using a two-stage dosing regimen comprising about 1 to about 7 days of intravenous administration followed by about 1 to about 14 days of oral administration of an antimicrobial agent. | 12-24-2015 |
Patent application number | Description | Published |
20100100126 | KNOTLESS SUTURE ANCHOR AND METHOD FOR KNOTLESSLY SECURING TISSUES - A method for securing first and second tissues with a suture anchor comprising the steps of forming a borehole in the first tissue; threading a suture through the second tissue forming a loop in the suture with the tissue thereby secured in the loop, the loop defining two suture portions; attaching the two suture portions to the anchor whereby the two suture portions are threaded through the anchor and initially movable with respect to the anchor; and providing a force to a shaft of the anchor, the force causing clamping of the two suture portions in the anchor and deformation of a deformable portion of the anchor to cause the deformable portion to engage a wall of the borehole thereby to secure the suture anchor in the first tissue and the loop holding the second tissue to the suture anchor. | 04-22-2010 |
20100100129 | KNOTLESS SUTURE ANCHOR AND METHOD FOR KNOTLESSLY SECURING TISSUES - A method for securing first and second tissues with a suture anchor comprising the steps of forming a borehole in the first tissue; threading a suture through the second tissue forming a loop in the suture with the tissue thereby secured in the loop, the loop defining two suture portions; attaching the two suture portions to the anchor whereby the two suture portions are threaded through the anchor and initially movable with respect to the anchor; and providing a force to a shaft of the anchor, the force causing clamping of the two suture portions in the anchor and deformation of a deformable portion of the anchor to cause the deformable portion to engage a wall of the borehole thereby to secure the suture anchor in the first tissue and the loop holding the second tissue to the suture anchor. | 04-22-2010 |
20100121310 | MULTIPLE COMPONENT MIXING AND DELIVERY SYSTEM - A multiple component cartridge includes a barrel defining a chamber and a longitudinal axis. A first plunger is disposed within the chamber and in sealing engagement with the barrel. The first plunger includes at least one member and is movable relative to the barrel such that the at least one member is configured for movement relative to the first plunger to facilitate passage of at least a first component through the first plunger. A second plunger is disposed within the chamber and in sealing engagement with the barrel. The second plunger includes at least one member and is movable relative to the barrel such that the at least one member of the second plunger is configured for movement relative to the second plunger to facilitate passage of at least a second component through the second plunger. | 05-13-2010 |
20100121376 | Suture Anchoring System and Method - A suture anchoring system and method includes a plurality of anchor members interconnected to form an anchor assembly with a suture extending therefrom. The anchor assembly has an insertion configuration wherein the anchor members are aligned in a substantially linear arrangement for delivery through an aperture in bodily tissue and an expanded configuration wherein the anchor members are transitioned to a non-linear arrangement to prevent passage of the anchor assembly back through the aperture. | 05-13-2010 |
20100191295 | ANNULUS REPAIR SYSTEM - An annulus repair system is provided. This repair system may cover a hole or opening in the annulus or repair a defect or damage to the annulus. In one embodiment, the annulus repair system comprises a blocking component that covers a hole in the annulus, a stabilizing component that helps stabilize the blocking component and a suturing material that connects the two components together. In certain embodiments, the annulus repair system may further comprise a cannula for guiding the blocking component, the stabilizing component and at least a portion of the suturing material through body tissue and into the disc space. Methods for utilizing the annulus repair system of the present invention also are provided. | 07-29-2010 |
20110028978 | Transpedicular Intervertebral Disk Access Methods and Devices - Methods and devices for treating diseases and conditions that change the spacial relationship between the vertebral bodies and the intervertebral disks, or that cause instability of the vertebral column, or both, and a method and devices that allow the surgeon to access the intervertebral space to restore a more normal three-dimensional configuration of the space, with or without additionally fusing two adjacent vertebrae. | 02-03-2011 |
20110040327 | KNOTLESS SUTURE ANCHOR AND METHOD FOR KNOTLESSLY SECURING TISSUES - A method for securing first and second tissues with a suture anchor comprising the steps of forming a borehole in the first tissue; threading a suture through the second tissue forming a loop in the suture with the tissue thereby secured in the loop, the loop defining two suture portions; attaching the two suture portions to the anchor whereby the two suture portions are threaded through the anchor and initially movable with respect to the anchor; and providing a force to a shaft of the anchor, the force causing clamping of the two suture portions in the anchor and deformation of a deformable portion of the anchor to cause the deformable portion to engage a wall of the borehole thereby to secure the suture anchor in the first tissue and the loop holding the second tissue to the suture anchor. | 02-17-2011 |
20120065735 | ANNULUS REPAIR SYSTEMS AND TECHNIQUES - Systems and methods for repairing annulus defects include at least one blocking member positionable in or adjacent to the annulus defect, at least one attachment portion for securing the blocking member to adjacent tissue, and instruments for placing and engaging the blocking member in and/or adjacent to the annulus defect. The blocking member extends at least partially across the annulus defect for repair of the defect and/or retention of nucleus material, one or more implants, bio-compatible materials or device, and/or other objects positioned in the disc space. | 03-15-2012 |
Patent application number | Description | Published |
20130340406 | FAN STAGGER ANGLE FOR GEARED GAS TURBINE ENGINE - A gas turbine engine includes a spool, a turbine coupled with the spool, a propulsor coupled to be rotated about an axis by the turbine through the spool and a gear assembly coupled between the propulsor and the spool such that rotation of the spool results in rotation of the propulsor at a different speed than the spool. The propulsor includes a hub and a row of propulsor blades that extends from the hub. Each of the propulsor blades has a span between a root at the hub and a tip, and a chord between a leading edge and a trailing edge such that the chord forms a stagger angle α with the axis. The stagger angle α is less than 62° at all positions along the span, with said hub being at 0% of the span and the tip being at 100% of the span. | 12-26-2013 |
20150233251 | GAS TURBINE ENGINE AIRFOIL - An airfoil for a turbine engine includes pressure and suction sides that extend in a radial direction from a 0% span position at an inner flow path location to a 100% span position at an airfoil tip. The airfoil has a relationship between a stacking offset and a span position that is at least a third order polynomial curve that includes at least one positive and negative slope. The positive slope crosses an initial axial stacking offset that corresponds to the 0% span position at a zero-crossing position. A first axial stacking offset X | 08-20-2015 |
20150233252 | GAS TURBINE ENGINE AIRFOIL - An airfoil of a turbine engine includes pressure and suction sides that extend in a radial direction from a 0% span position at an inner flow path location to a 100% span position at an airfoil tip. The airfoil has a relationship between a tangential stacking offset and a span position that is at least a third order polynomial curve that includes at least one positive and negative slope. The positive slope leans toward the suction side and the negative slope leans toward the pressure side. An initial slope starting at the 0% span position is either zero or positive. The first critical point is in the range of 5-15% span. | 08-20-2015 |
20150233323 | GAS TURBINE ENGINE AIRFOIL - A gas turbine engine includes a fan section, a compressor section and a turbine section, one of which includes an airfoil. The airfoil includes pressure and suction sides extending in a radial direction from a 0% span position at an inner flow path location to a 100% span position at an airfoil tip. The airfoil has a maximum chord length projection that is not in an axial view. | 08-20-2015 |
20150354362 | GAS TURBINE ENGINE AIRFOIL - An airfoil for a turbine engine includes pressure and suction sides that extend in a radial direction from a 0% span position at an inner flow path location to a 100% span position at an airfoil tip. The airfoil has a relationship between a total chord length and a span position and corresponds to a curve that has an increasing total chord length from the 0% span position to a first peak. The first peak occurs in the range of 45-65% span position, and the curve either remains generally constant or has a decreasing total chord length from the first peak to the 100% span position. The total chord length is at the 0% span position in the range of 8.2-10.5 inches (20.8-26.7 cm). | 12-10-2015 |
20150354363 | GAS TURBINE ENGINE AIRFOIL - An airfoil for a turbine engine includes an airfoil having pressure and suction sides extending in a radial direction from a 0% span position at an inner flow path location to a 100% span position at an airfoil tip. The airfoil has a curve corresponding to a relationship between a trailing edge sweep angle and a span position. The trailing edge sweep angle is in a range of 10° to 20° in a range of 40-70% span position. The trailing edge sweep angle is positive from 0% span to at least 95% span. | 12-10-2015 |
20150354364 | GAS TURBINE ENGINE AIRFOIL - An airfoil for a turbine engine includes an airfoil that has pressure and suction sides that extend in a radial direction from a 0% span position at an inner flow path location to a 100% span position at an airfoil tip. The airfoil has a curve that corresponds to a relationship between a trailing edge sweep angle and a span position. The trailing edge sweep angle is in a range of 10° to 20° in a range of 40-70% span position, and the trailing edge sweep angle is positive from 0% span to at least 95% span. The airfoil has a relationship between a leading edge dihedral and a span position. The leading edge dihedral is negative from the 0% span position to the 100% span position. A positive dihedral corresponds to suction side-leaning, and a negative dihedral corresponds to pressure side-leaning. | 12-10-2015 |
20150354367 | GAS TURBINE ENGINE AIRFOIL - An airfoil for a turbine engine includes an airfoil having pressure and suction sides extending in a radial direction from a 0% span position at an inner flow path location to a 100% span position at an airfoil tip. The airfoil has a relationship between a leading edge dihedral and a span position. The leading edge dihedral is negative from the 0% span position to the 100% span position. A positive dihedral corresponds to suction side-leaning, and a negative dihedral corresponds to pressure side-leaning. | 12-10-2015 |
20150361797 | GAS TURBINE ENGINE AIRFOIL - An airfoil for a turbine engine includes pressure and suction sides that extend in a radial direction from a 0% span position at an inner flow path location to a 100% span position at an airfoil tip. The airfoil has a relationship between a stacking offset and a span position that is at least a third order polynomial curve that includes at least one positive and negative slope. The positive slope leans aftward and the negative slope leans forward relative to an engine axis. The positive slope crosses an initial axial stacking offset corresponding to the 0% span position at a zero-crossing position. A first axial stacking offset X | 12-17-2015 |
20160024929 | GAS TURBINE ENGINE AIRFOIL - An airfoil for a turbine engine includes an airfoil that has pressure and suction sides that extend in a radial direction from a 0% span position at an inner flow path location to a 100% span position at an airfoil tip. The airfoil has a relationship between a leading edge dihedral and a span position. The leading edge dihedral is negative from the 0% span position to the 100% span position. A positive dihedral corresponds to suction side-leaning, and a negative dihedral corresponds to pressure side-leaning. The airfoil is a fan blade for a gas turbine engine. The airfoil has a relationship between a trailing edge dihedral and a span position. The trailing edge dihedral is positive from the 0% span position to the 100% span position. A positive dihedral corresponds to suction side-leaning and a negative dihedral corresponds to pressure side-leaning. | 01-28-2016 |
20160032728 | GAS TURBINE ENGINE AIRFOIL - An airfoil of a turbine engine includes pressure and suction sides that extend in a radial direction from a 0% span position at an inner flow path location to a 100% span position at an airfoil tip. The airfoil has a relationship between a tangential stacking offset and a span position that is at least a third order polynomial curve that includes at least one positive and negative slope. The positive slope leans toward the suction side and the negative slope leans toward the pressure side. An initial slope starts at the 0% span position is either zero or positive. The first critical point is less than 15% span. | 02-04-2016 |
Patent application number | Description | Published |
20090112954 | A ROBUST SPECTRAL ANALYZER FOR ONE-DIMENSIONAL AND MULTI-DIMENSIONAL DATA ANALYSIS - A method of analyzing a spectrum of one-dimensional or multi-dimensional signal X(t) requires a number of steps including deriving coefficients [A | 04-30-2009 |
20090187464 | METHOD AND APPARATUS FOR END-TO-END RETAIL STORE SITE OPTIMIZATION - A method and apparatus for end-to-end retail store one-stop site configuration integrates multiple data sources, identifying key customers, forecasting merchandise demand. Site configuration is formulated as a mathematical optimization problem with both in-store and external data as input to the problem whose solution provides proper suggestions for retail store transformation. | 07-23-2009 |
20090234782 | METHOD AND APPARATUS FOR LOCATION EVALUATION AND SITE SELECTION - Method, apparatus and system for location evaluation and site selection, capable of effectively configuring the site network and evaluating the facility location by scientifically modeling and incorporating human knowledge are provided. In one aspect, geographic and demographic data associated with a plurality of locations and human knowledge comprising partial rating knowledge and pair-wise preference knowledge are used in a regression algorithm to construct a location evaluation model. The regression algorithm is further refined using active learning that identifies a plurality of pairs of locations to improve precision of the regression algorithm. | 09-17-2009 |
20090281869 | METHOD AND APPARATUS FOR INTEGRATED MULTIPLE FACTORS INTO A UNIFIED OPTIMIZATION MODEL FOR RETAIL NETWORK CONFIGURATION - A method and system for integrating multiple factors into a unified optimization model for retail network configuration, in one aspect, obtains input data for modeling store configuration. The input data may include demand of each merchandise category from each customer segment in each facility, geographic distribution of stores in an area, current revenue of stores, and physical cost of reconfiguring stores. A trade area is generated as a function of store location, store format, and store capacity. The method and system also generates trade area demand summation representing predicted total demand of all stores for all merchandise categories for all customer segments in the trade area, as a function of store location, store format, store capacity, merchandise category, and customer segment associated with the trade area. An objective function is constructed as a function of said trade area demand summation, current revenue of stores, and physical cost of reconfiguring stores. | 11-12-2009 |
20100228858 | METHODS AND APPARATUS FOR DYNAMIC ALLOCATION OF SERVERS TO A PLURALITY OF CUSTOMERS TO MAXIMIZE THE REVENUE OF A SERVER FARM - A method and structure for dynamic allocation of servers to customers in a server farm which supports a flexible contract structure such that the total revenue of the farm is maximized. The invention creates a resource allocation plan based on a long term forecast for the server farm, taking into account traffic, number of servers, customers' contracts and revenue optimization algorithms. The plan is then modified as indicated by short term forecasting using currently monitored load metrics to reallocate to maximize revenue for particular time periods. | 09-09-2010 |
20120016716 | JOINT MULTI-CHANNEL CONFIGURATION OPTIMIZATION FOR RETAIL INDUSTRY - A data integration module is operable to integrate a plurality of data sources, a customer preference module builds a model representing preference to different channels in merchandise category for each customer segment. A customer satisfaction module creates a model representing customer satisfaction metrics. A joint multi-channel optimization module is operable to use an optimization model that utilizes the customer preference model and the customer satisfaction model and maximize retailer's profit and customer satisfaction. | 01-19-2012 |
20120046991 | COMPETING SIMULATOR IN MULTI-CHANNEL RETAILING ENVIRONMENT AMONG MULTIPLE RETAILERS - A system, method and computer program product for providing the ability for retailers to devise a current channel strategy (e.g., adaptive price setting) that considers competitors in a dynamic competing environment, and that enables computing a competitive advantage of a channel. To estimate a price for selling a product j in a commerce channel comprises: a) receiving, at a processor device, real market data including sales and price history data of a product j sold by one or more retailers over one or alternate sales channels t; generating, by the processor device, a competitive advantage parameter value based on the sales and price history data; and, computing, utilizing the competitive advantage parameter value, an optimum price for a particular product to be marketed in one of the one or alternate sales channel. | 02-23-2012 |
20120078943 | HIGH QUANTITATIVE PATTERN SEARCHING USING SPATIAL INDEXING - A computer searching technique identifies high quantitative patterns in data. A spatial indexing technique, such as an R-tree is used to represent the data. Then a pattern searching algorithm is used to identify anchor points that define the componentwise minimum patterns. High quantitative patterns are found responsive to the componentwise minimum patterns. The search strategy is demonstrated relevant to the problem of finding suitable locations for a retail business with reference to environments of prior successful retail businesses. | 03-29-2012 |
20120084118 | SALES PREDICATION FOR A NEW STORE BASED ON ON-SITE MARKET SURVEY DATA AND HIGH RESOLUTION GEOGRAPHICAL INFORMATION - A method for predicting sales for a new store in a certain geographical area is disclosed, the method comprising geographic and non-geographic information and customer segmentation in the area to estimate sales and optionally the impact on existing competitor stores. | 04-05-2012 |
20130066577 | ROBUST SPECTRAL ANALYZER FOR ONE-DIMENSIONAL AND MULTI-DIMENSIONAL DATA ANALYSIS - A method of analyzing a spectrum of one-dimensional or multi-dimensional signal X(t) requires a number of steps including deriving coefficients [A | 03-14-2013 |
20140025416 | Clustering Based Resource Planning, Work Assignment, and Cross-Skill Training Planning in Services Management - An embodiment of the invention provides a method for service management, wherein resources that have performed tasks in at least two of a first category, a second category, and at least one additional category are identified. A plurality of correlation sums are determined where the correlation sum includes at least two categories, wherein the correlation sums are added together to produce a correlation value. A correlation product for each correlation sum is calculated based on the respective correlation sum and the number of resources that have performed tasks with respect to the correlation sum. A quotient is calculated for each correlation sum based on the respective correlation product and the correlation value. The categories are grouped into clusters with a clustering module based on the quotients; and, resources are associated with the clusters based on task performance history of the resources. | 01-23-2014 |
20140025418 | Clustering Based Resource Planning, Work Assignment, and Cross-Skill Training Planning in Services Management - An embodiment of the invention provides a method for service management, wherein resources that have performed tasks in at least two of a first category, a second category, and at least one additional category are identified. A plurality of correlation sums are determined where the correlation sum includes at least two categories, wherein the correlation sums are added together to produce a correlation value. A correlation product for each correlation sum is calculated based on the respective correlation sum and the number of resources that have performed tasks with respect to the correlation sum. A quotient is calculated for each correlation sum based on the respective correlation product and the correlation value. The categories are grouped into clusters with a clustering module based on the quotients; and, resources are associated with the clusters based on task performance history of the resources. | 01-23-2014 |
20150025931 | BUSINESS OPPORTUNITY FORECASTING - A method and apparatus to determine: (a) the likelihood and timing for a sales opportunity to become a sale based on analytical models that incorporate the history of sales stage evolution and other covariates; and (b) the expected number of sales from invisible opportunities prior to a target date. Additionally, the method and apparatus is configured to predict an expected amount of revenue and/or an amount of resources given a current sales history. | 01-22-2015 |
20150051935 | SCHEDULING FOR SERVICE PROJECTS VIA NEGOTIATION - Assignment scheduling for service projects, in one aspect, may comprise preparing input parameter data for servicing a client service request; generating a schedule for servicing the client service request by executing an optimization algorithm with the input parameter data; determining whether the schedule is acceptable by the client; and repeating automatically the preparing, the generating, the transmitting and the determining until it is determined that the schedule is acceptable by the client, wherein each iteration automatically prepares different input parameter data for inputting to the optimization algorithm and generates a different schedule based on the different input parameter data. | 02-19-2015 |
20150052182 | SCHEDULING FOR SERVICE PROJECTS VIA NEGOTIATION - Assignment scheduling for service projects, in one aspect, may comprise preparing input parameter data for servicing a client service request; generating a schedule for servicing the client service request by executing an optimization algorithm with the input parameter data; determining whether the schedule is acceptable by the client; and repeating automatically the preparing, the generating, the transmitting and the determining until it is determined that the schedule is acceptable by the client, wherein each iteration automatically prepares different input parameter data for inputting to the optimization algorithm and generates a different schedule based on the different input parameter data. | 02-19-2015 |
20150236934 | METRICS MANAGEMENT AND MONITORING SYSTEM FOR SERVICE TRANSITION AND DELIVERY MANAGEMENT - A service engagement map may be generated based on data collected associated with the service transition and delivery processes. The service engagement map may be refined iteratively by discovering additional data associated with the service transition and delivery processes and updating the service engagement map according to the additional data. Engagement metrics may be computed based on the service engagement map and presented. The service engagement map may also be presented visually. | 08-20-2015 |
20150302337 | BENCHMARKING ACCOUNTS IN APPLICATION MANAGEMENT SERVICE (AMS) - An application management service account benchmarking. An account profile is generated associated with a target account. Data associated with the target account collected and prepared for benchmarking. A benchmarking pool is formed to include a set of accounts with which to compare the target account. Operational KPIs are designed for benchmarking analysis. Measurements associated with the operational KPIs are determined for the target account and the set of accounts in the benchmarking pool. Benchmarking is conducted based on the measurements. A graph of a distance map is generated and presented on a graphical user interface. Post benchmarking analysis is performed that suggests an action to be performed for the target account. | 10-22-2015 |
20150324726 | BENCHMARKING ACCOUNTS IN APPLICATION MANAGEMENT SERVICE (AMS) - An application management service account benchmarking. An account profile is generated associated with a target account. Data associated with the target account collected and prepared for benchmarking. A benchmarking pool is formed to include a set of accounts with which to compare the target account. Operational KPIs are designed for benchmarking analysis. Measurements associated with the operational KPIs are determined for the target account and the set of accounts in the benchmarking pool. Benchmarking is conducted based on the measurements. A graph of a distance map is generated and presented on a graphical user interface. Post benchmarking analysis is performed that suggests an action to be performed for the target account. | 11-12-2015 |
Patent application number | Description | Published |
20090112009 | AMORPHOUS GE/TE DEPOSITION PROCESS - Germanium, tellurium, and/or antimony precursors are usefully employed to form germanium-, tellurium- and/or antimony-containing films, such as films of GeTe, GST, and thermoelectric germanium-containing films. Processes for using these precursors to form amorphous films are also described. Further described is the use of [{nBuC(iPrN) | 04-30-2009 |
20100164057 | PRECURSORS FOR SILICON DIOXIDE GAP FILL - A full fill trench structure comprising a microelectronic device substrate having a high aspect ratio trench therein and a full filled mass of silicon dioxide in the trench, wherein the silicon dioxide is of a substantially void-free character and has a substantially uniform density throughout its bulk mass. A corresponding method of manufacturing a semiconductor product is described, involving use of specific silicon precursor compositions for use in full filling a trench of a microelectronic device substrate, in which the silicon dioxide precursor composition is processed to conduct hydrolysis and condensation reactions for forming the substantially void-free and substantially uniform density silicon dioxide material in the trench. The fill process may be carried out with a precursor fill composition including silicon and germanium, to produce a microelectronic device structure including a GeO | 07-01-2010 |
20100209598 | IN SITU GENERATION OF RuO4 FOR ALD OF Ru AND Ru RELATED MATERIALS - Apparatus and method for generating ruthenium tetraoxide in situ for use in vapor deposition, e.g., atomic layer deposition (ALD), of ruthenium-containing films on microelectronic device substrates. The ruthenium tetraoxide can be generated on demand by reaction of ruthenium or ruthenium dioxide with an oxic gas such as oxygen or ozone. In one implementation, ruthenium tetraoxide thus generated is utilized with a strontium organometallic precursor for atomic layer deposition of strontium ruthenate films of extremely high smoothness and purity. | 08-19-2010 |
20110260132 | HIGH CONCENTRATION NITROGEN-CONTAINING GERMANIUM TELLURIDE BASED MEMORY DEVICES AND PROCESSES OF MAKING - A PCM device has the composition GexTeyNzAm deposited onto a substrate, where x is about 40% to about 60%, y is about 30% to about 49%, and z is about 5% to about 20% and more preferably about 5% to about 40%. The component represented as A is optional and representative of an element of Sb, Sn, In, Ga, or Zn, and m is up to about 15%. The composition is in the form of a film, and the nitrogen allows for the substantially conformal deposition of the film onto the substrate. A CVD process for depositing the PCM comprises delivering a Ge-based precursor and a Te-based precursor in vapor form to a CVD chamber, heating and pressurizing the chamber, and depositing the film onto a substrate. In making a phase change device using this process, the film is annealed and polished. | 10-27-2011 |
20120064719 | METHOD AND COMPOSITION FOR DEPOSITING RUTHENIUM WITH ASSISTIVE METAL SPECIES - A method of forming a ruthenium-containing film in a vapor deposition process, including depositing ruthenium with an assistive metal species that increases the rate and extent of ruthenium deposition in relation to deposition of ruthenium in the absence of such assistive metal species. An illustrative precursor composition useful for carrying out such method includes a ruthenium precursor and a strontium precursor in a solvent medium, wherein one of the ruthenium and strontium precursors includes a pendant functionality that coordinates with the central metal atom of the other precursor, so that ruthenium and strontium co-deposit with one another. The method permits incubation time for ruthenium deposition on non- metallic substrates to be very short, thereby accommodating very rapid film formation in processes such as atomic layer deposition. | 03-15-2012 |
20120108038 | AMORPHOUS GE/TE DEPOSITION PROCESS - Germanium, tellurium, and/or antimony precursors are usefully employed to form germanium-, tellurium- and/or antimony-containing films, such as films of GeTe, GST, and thermoelectric germanium-containing films. Processes for using these precursors to form amorphous films are also described. Further described is the use of [{nBuC(iPrN) | 05-03-2012 |
20150147824 | SILICON PRECURSORS FOR LOW TEMPERATURE ALD OF SILICON-BASED THIN-FILMS - A silicon precursor composition is described, including a silylene compound selected from among: silylene compounds of the formula: wherein each of R and R | 05-28-2015 |
20150251920 | FLUORINE FREE TUNGSTEN ALD/CVD PROCESS - A tungsten precursor useful for forming tungsten-containing material on a substrate, e.g., in the manufacture of microelectronic devices. The tungsten precursor is devoid of fluorine content, and may be utilized in a solid delivery process or other vapor deposition technique, to form films such as elemental tungsten for metallization of integrated circuits, or tungsten nitride films or other tungsten compound films that are useful as base layers for subsequent elemental tungsten metallization. | 09-10-2015 |
20150318108 | IN-SITU OXIDIZED NiO AS ELECTRODE SURFACE FOR HIGH k MIM DEVICE - A high dielectric constant metal-insulator structure, including an electrode comprising NiO | 11-05-2015 |
20150364537 | ALD PROCESSES FOR LOW LEAKAGE CURRENT AND LOW EQUIVALENT OXIDE THICKNESS BiTaO FILMS - A high dielectric constant (k≧40), low leakage current (≦10 | 12-17-2015 |
Patent application number | Description | Published |
20080214651 | Crystalline forms of [R-(R*, R*)]-2-(4-fluorophenyl)-beta,delta-dihydroxy-5-(1-methylethyl)-3-phenyl-4-[(phenylamino)carbonyl]-1H-pyrrole-1-heptanoic acid calcium salt (2:1) - Novel crystalline forms of [R—(R*,R*)]-2-(4-fluorophenyl)-β,δ-dihydroxy-5-(1-methylethyl)-3-phenyl-4-[(phenylamino)carbonyl]-1H-pyrrole-1-heptanoic acid hemi calcium salt designated Form V, Form VI, Form VII, Form VIII, Form IX, Form X, Form XI, Form XII, Form XIII, Form XIV, Form XV, Form XVI, Form XVII, Form XVIII, and Form XIX are characterized by their X-ray powder diffraction, solid-state NMR, and/or Raman spectroscopy are described, as well as methods for the preparation and pharmaceutical composition of the same, which are useful as agents for treating hyperlipidemia, hypercholesterolemia, osteoporosis, and Alzheimer's disease. | 09-04-2008 |
20080287521 | Crystalline Forms Of [R-(R*,R*)-2-(4-fluorophenyl)-beta,delta-dihydroxy-5-(1-methyl- Ethyl)-3-phenyl-4-[(phenylamino)carbonyl]-1H-pyrrole-1-heptanoic Acid Calcium Salt (2:1) - Novel crystalline forms of [R-(R*,R*)]-2-(4-fluorophenyl)-β,δ-dihydroxy-5-(1-methylethyl)-3-phenyl-4-[(phenylamino)carbonyl]-1H-pyrrole-1-heptanoic acid hemi calcium salt designated Form V, Form VI, Form VII, Form VIII, Form IX, Form X, Form XI, Form XII, Form XIII, Form XIV, Form XV, Form XVI, Form XVII, Form XVIII, and Form XIX are characterized by their X-ray powder diffraction, solid-state NMR, and/or Raman spectroscopy are described, as well as methods for the preparation and pharmaceutical composition of the same, which are useful as agents for treating hyperlipidemia, hypercholesterolemia, osteoporosis, and Alzheimer's disease. | 11-20-2008 |
20090018158 | CRYSTAL FORMS OF AN IMIDAZOLE DERIVATIVE - The invention relates to the essentially pure Λ/-[({2-[4-(2-Ethyl-4,6-dimethyl-1H-imidazo[4,5-c]pyridin-1 -yl)phenyl]ethyl}amino)carbonyl]-4-methylbenzenesulfonamide Polymorph Forms A and B and to processes for the preparation of, compositions containing and to the uses of, such crystal forms. | 01-15-2009 |
Patent application number | Description | Published |
20110174369 | Efficiency in Antireflective Coating Layers for Solar Cells - A method for fabricating a cell structure includes doping a substrate to form a N-region and a P-region, disposing a first anti-reflective layer on the substrate, disposing a metallic contact paste on the first anti-reflective layer, drying the metallic contact paste to form contacts, disposing a second anti-reflective layer on the first anti-reflective layer and the metallic contacts, and heating the cell structure, wherein heating the cell structure results in metallic contact material penetrating the first anti-reflective layer and contacting the substrate. | 07-21-2011 |
20110317324 | Solar Module with Overheat Protection - A photovoltaic module ( | 12-29-2011 |
20120021204 | STRUCTURE AND METHOD TO FORM NANOPORE - A method of fabricating a material having nanoscale pores is provided. In one embodiment, the method of fabricating a material having nanoscale pores may include providing a single crystal semiconductor. The single crystal semiconductor layer is then patterned to provide an array of exposed portions of the single crystal semiconductor layer having a width that is equal to the minimum lithographic dimension. The array of exposed portion of the single crystal semiconductor layer is then etched using an etch chemistry having a selectivity for a first crystal plane to a second crystal plane of 100% or greater. The etch process forms single or an array of trapezoid shaped pores, each of the trapezoid shaped pores having a base that with a second width that is less than the minimum lithographic dimension. | 01-26-2012 |
20120040512 | METHOD TO FORM NANOPORE ARRAY - A method of forming nanopore is provided that includes forming a first structure on a substrate, and forming a second structure overlying the first structure. An intersecting portion of the first and the second structures is etched to provide an opening of nanopore dimensions. The substrate may be etched with a backside substrate etch to expose the nanopore opening. | 02-16-2012 |
20120061234 | Deposition Chamber Cleaning Method Including Stressed Cleaning Layer - A method for cleaning a deposition chamber includes forming a deposited layer over an interior surface of the deposition chamber, wherein the deposited layer has a deposited layer stress and a deposited layer modulus; forming a cleaning layer over the deposited layer, wherein a material comprising the cleaning layer is selected such that the cleaning layer adheres to the deposited layer, and has a cleaning layer stress and a cleaning layer modulus, wherein the cleaning layer stress is higher than the deposited layer stress, and wherein the cleaning layer modulus is higher than the deposited layer modulus; and removing the deposited layer and the cleaning layer from the interior of the deposition chamber. | 03-15-2012 |
20120104469 | REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE - In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor. | 05-03-2012 |
20120119302 | Trench Silicide Contact With Low Interface Resistance - An electrical structure is provided that includes a dielectric layer present on a semiconductor substrate and a via opening present through the dielectric layer. | 05-17-2012 |
20120139015 | METAL SEMICONDUCTOR ALLOY CONTACT WITH LOW RESISTANCE - A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact. | 06-07-2012 |
20120174979 | Efficiency in Antireflective Coating Layers for Solar Cells - A solar cell includes a substrate having an N-region and a P-region, a first anti-reflective layer disposed on the substrate, a metallic contact disposed on the first anti-reflective layer, a second anti-reflective layer disposed on the first anti-reflective layer and the metallic contact, and a region partially defined by the first anti-reflective layer and the second anti-reflective layer having diffused metallic contact material operative to form a conductive path to the substrate through the first anti-reflective layer, the metallic contact, and the second anti-reflective layer. | 07-12-2012 |
20120187375 | Deposition On A Nanowire Using Atomic Layer Deposition - In one exemplary embodiment, a method includes: providing a semiconductor device having a substrate, a nanowire, a first structure and a second structure, where the nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate; and performing atomic layer deposition to deposit a film on at least a portion of the semiconductor device, where performing atomic layer deposition to deposit the film includes performing atomic layer deposition to deposit the film on at least a surface of the nanowire. | 07-26-2012 |
20120187460 | METHOD FOR FORMING METAL SEMICONDUCTOR ALLOYS IN CONTACT HOLES AND TRENCHES - A method of forming a semiconductor device is provided that includes forming a first metal semiconductor alloy on a semiconductor containing surface, forming a dielectric layer over the first metal semiconductor alloy, forming an opening in the dielectric layer to provide an exposed surface the first metal semiconductor alloy, and forming a second metal semiconductor alloy on the exposed surface of the first metal semiconductor alloy. In another embodiment, the method includes forming a gate structure on a channel region of a semiconductor substrate, forming a dielectric layer over at least a source region and a drain region, forming an opening in the dielectric layer to provide an exposed surface the semiconductor substrate, forming a first metal semiconductor alloy on the exposed surface of the semiconductor substrate, and forming a second metal semiconductor alloy on the first metal semiconductor alloy. | 07-26-2012 |
20120261804 | VERTICAL SUBSTRATE DIODE, METHOD OF MANUFACTURE AND DESIGN STRUCTURE - A diode structure, formed under a buried dielectric layer of a silicon on insulator (SOI), method of manufacturing the same and design structure thereof are provided. In an embodiment the p-n junction of the diode structure can be advantageously arranged in a vertical orientation. The cathode comprises an N+ epitaxial layer formed upon a P-type substrate. The anode comprises an active region of the P-substrate. Contacts to the cathode and anode are formed through the buried dielectric layer. Contact to the anode is accomplished via a deep trench filled with a conductive plug. The deep trench also provides electrical isolation for the cathode (as well as p-n junction). Advantageously, embodiments of the present invention may be formed during formation of other structures which also include trenches (for example, deep trench capacitors) in order to reduce process steps required to form the diode structure under the buried dielectric layer of the SOI substrate. | 10-18-2012 |
20120275208 | RELIABLE ELECTRICAL FUSE WITH LOCALIZED PROGRAMMING AND METHOD OF MAKING THE SAME - An electrical fuse has an anode contact on a surface of a semiconductor substrate. The electrical fuse has a cathode contact on the surface of the semiconductor substrate spaced from the anode contact. The electrical fuse has a link within the substrate electrically interconnecting the anode contact and the cathode contact. The link comprises a semiconductor layer and a silicide layer. The silicide layer extends beyond the anode contact. An opposite end of the silicide layer extends beyond the cathode contact. A silicon germanium region is embedded in the semiconductor layer under the silicide layer, between the anode contact and the cathode contact. | 11-01-2012 |
20120326125 | Deposition On A Nanowire Using Atomic Layer Deposition - A semiconductor device includes a substrate, a nanowire, a first structure, and a second structure. The nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate, where the nanowire includes a layer on a surface of the nanowire, where the layer includes at least one of silicide and carbide, where the layer has a substantially uniform shape. | 12-27-2012 |
20130093043 | ARRAY AND MOAT ISOLATION STRUCTURES AND METHOD OF MANUFACTURE - An array or moat isolation structure for eDRAM and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region. | 04-18-2013 |
20130115732 | Method to Fabricate Multicrystal Solar Cell with Light Trapping Surface Using Nanopore Copolymer - Multi-crystalline silicon processing techniques are provided. In one aspect, a method for roughening a multi-crystalline silicon surface is provided. The method includes the following steps. The multi-crystalline silicon surface is coated with a diblock copolymer. The diblock copolymer is annealed to form nanopores therein. The multi-crystalline silicon surface is etched through the nanopores in the diblock copolymer to roughen the multi-crystalline silicon surface. The diblock copolymer is removed. A multi-crystalline silicon substrate with a roughened surface having a plurality of peaks and troughs is also provided, wherein a distance from one peak to an adjacent peak on the roughened surface is from about 20 nm to about 400 nm. | 05-09-2013 |
20130164522 | STRUCTURE AND METHOD TO FORM NANOPORE - A method of fabricating a material having nanoscale pores is provided. In one embodiment, the method of fabricating a material having nanoscale pores may include providing a single crystal semiconductor. The single crystal semiconductor layer is then patterned to provide an array of exposed portions of the single crystal semiconductor layer having a width that is equal to the minimum lithographic dimension. The array of exposed portion of the single crystal semiconductor layer is then etched using an etch chemistry having a selectivity for a first crystal plane to a second crystal plane of 100% or greater. The etch process forms single or an array of trapezoid shaped pores, each of the trapezoid shaped pores having a base that with a second width that is less than the minimum lithographic dimension. | 06-27-2013 |
20130171795 | TRENCH SILICIDE CONTACT WITH LOW INTERFACE RESISTANCE - An electrical structure is provided that includes a dielectric layer present on a semiconductor substrate and a via opening present through the dielectric layer. | 07-04-2013 |
20130175641 | REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE - In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor. | 07-11-2013 |
20130180543 | DEPOSITION CHAMBER CLEANING METHOD INCLUDING STRESSED CLEANING LAYER - A method for cleaning a deposition chamber includes forming a deposited layer over an interior surface of the deposition chamber, wherein the deposited layer has a deposited layer stress and a deposited layer modulus; forming a cleaning layer over the deposited layer, wherein a material comprising the cleaning layer is selected such that the cleaning layer adheres to the deposited layer, and has a cleaning layer stress and a cleaning layer modulus, wherein the cleaning layer stress is higher than the deposited layer stress, and wherein the cleaning layer modulus is higher than the deposited layer modulus; and removing the deposited layer and the cleaning layer from the interior of the deposition chamber. | 07-18-2013 |
20130241031 | PROGRAMMABLE FUSE STRUCTURE AND METHODS OF FORMING - Methods of forming an electrically programmable fuse (e-fuse) structure and the e-fuse structure are disclosed. Various embodiments of forming the e-fuse structure include: forming a dummy poly gate structure to contact a surface of a silicon structure, the dummy poly gate structure extending only a part of a length of the silicon structure; and converting an unobstructed portion of the surface of the silicon structure to silicide to form a thinned strip of the silicide between two end regions. | 09-19-2013 |
20130277764 | Etch Stop Layer Formation In Metal Gate Process - A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor. | 10-24-2013 |
20130277767 | ETCH STOP LAYER FORMATION IN METAL GATE PROCESS - A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor. | 10-24-2013 |
20140000712 | NIOBIUM THIN FILM STRESS RELIEVING LAYER FOR THIN-FILM SOLAR CELLS | 01-02-2014 |
20140017862 | METAL SEMICONDUCTOR ALLOY CONTACT WITH LOW RESISTANCE - A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact. | 01-16-2014 |
20140117498 | Self-Aligned Silicide Bottom Plate for EDRAM Applications by Self-Diffusing Metal in CVD/ALD Metal Process - In one aspect, a memory cell capacitor is provided. The memory cell capacitor includes a silicon wafer; at least one trench in the silicon wafer; a silicide within the trench that serves as a bottom electrode of the memory cell capacitor, wherein a contact resistance between the bottom electrode and the silicon wafer is from about 1×10 | 05-01-2014 |
20140120687 | Self-Aligned Silicide Bottom Plate for EDRAM Applications by Self-Diffusing Metal in CVD/ALD Metal Process - In one aspect, a method of fabricating a memory cell capacitor includes the following steps. At least one trench is formed in a silicon wafer. A thin layer of metal is deposited onto the silicon wafer, lining the trench, using a conformal deposition process under conditions sufficient to cause at least a portion of the metal to self-diffuse into portions of the silicon wafer exposed within the trench forming a metal-semiconductor alloy. The metal is removed from the silicon wafer selective to the metal-semiconductor alloy such that the metal-semiconductor alloy remains. The silicon wafer is annealed to react the metal-semiconductor alloy with the silicon wafer to form a silicide, wherein the silicide serves as a bottom electrode of the memory cell capacitor. A dielectric is deposited into the trench covering the bottom electrode. A top electrode is formed in the trench separated from the bottom electrode by the dielectric. | 05-01-2014 |
20140124952 | ARRAY AND MOAT ISOLATION STRUCTURES AND METHOD OF MANUFACTURE - An array or moat isolation structure for eDRAM with heterogeneous deep trench fill and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method further includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method further includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method further includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method further includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region. | 05-08-2014 |
20140264482 | CARBON-DOPED CAP FOR A RAISED ACTIVE SEMICONDUCTOR REGION - After formation of a disposable gate structure, a raised active semiconductor region includes a vertical stack, from bottom to top, of an electrical-dopant-doped semiconductor material portion and a carbon-doped semiconductor material portion. A planarization dielectric layer is deposited over the raised active semiconductor region, and the disposable gate structure is replaced with a replacement gate structure. A contact via cavity is formed through the planarization dielectric material layer by an anisotropic etch process that employs a fluorocarbon gas as an etchant. The carbon in the carbon-doped semiconductor material portion retards the anisotropic etch process, and the carbon-doped semiconductor material portion functions as a stopping layer for the anisotropic etch process, thereby making the depth of the contact via cavity less dependent on variations on the thickness of the planarization dielectric layer or pattern factors. | 09-18-2014 |
20140345687 | NIOBIUM THIN FILM STRESS RELIEVING LAYER FOR THIN-FILM SOLAR CELLS - A photovoltaic device includes a thermal stress relieving layer on top of a substrate; a back ohmic contact on the thermal stress relieving layer; and a p-type semiconductor photon absorber layer on the back ohmic contact. The back ohmic contact comprises a metallic compound of the sacrificial back electrode metal layer and the absorber layer, in combination with the thermal stress relieving layer. The thermal stress relieving layer has a substantially similar thermal expansion coefficient with respect to the substrate and the absorber layer and a lower Young's modulus with respect to the sacrificial back electrode metal layer. | 11-27-2014 |
20140353589 | REPLACEMENT GATE SELF-ALIGNED CARBON NANOSTRUCTURE TRANSISTOR - A self-aligned carbon nanostructure transistor is formed by a method that includes providing a material stack including a gate dielectric material having a dielectric constant of greater than silicon oxide and a sacrificial gate material. Next, a carbon nanostructure is formed on an exposed surface of the gate dielectric material. After forming the carbon nanostructure, metal semiconductor alloy portions are formed self-aligned to the material stack. The sacrificial gate material is then replaced with a conductive metal. | 12-04-2014 |
20140353590 | REPLACEMENT GATE SELF-ALIGNED CARBON NANOSTRUCTURE TRANSISTOR - A self-aligned carbon nanostructure transistor is formed by a method that includes providing a material stack including a gate dielectric material having a dielectric constant of greater than silicon oxide and a sacrificial gate material. Next, a carbon nanostructure is formed on an exposed surface of the gate dielectric material. After forming the carbon nanostructure, metal semiconductor alloy portions are formed self-aligned to the material stack. The sacrificial gate material is then replaced with a conductive metal. | 12-04-2014 |
20140374844 | METHOD FOR FORMING METAL SEMICONDUCTOR ALLOYS IN CONTACT HOLES AND TRENCHES - A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy. | 12-25-2014 |
20140374874 | PROGRAMMABLE FUSE STRUCTURE AND METHODS OF FORMING - Methods of forming an electrically programmable fuse (e-fuse) structure and the e-fuse structure are disclosed. One embodiment of an e-fuse structure includes: a silicon structure; a pair of silicide contact regions overlying the silicon structure; and a silicide link overlying the silicon structure and connecting the pair of silicide regions, the silicide link having a depth less than a depth of each of the pair of silicide contact regions. | 12-25-2014 |
20150044845 | METHOD FOR FORMING METAL SEMICONDUCTOR ALLOYS IN CONTACT HOLES AND TRENCHES - A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy. | 02-12-2015 |
20150137269 | REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE - In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor. | 05-21-2015 |