Patent application number | Description | Published |
20080227409 | WIRELESS RECEIVER WITH NOTCH FILTER TO REDUCE EFFECTS OF TRANSMIT SIGNAL LEAKAGE - This disclosure describes techniques for reducing adverse effects of TX signal leakage in a full-duplex, wireless communication device. The techniques make use of a notch filter to reject TX signal leakage in a signal processed in the RX path of the wireless communication device. The notch filter may be constructed as a complex notch filter using passive resistor and capacitor components to produce a notch frequency that attenuates TX signal leakage components in a desired signal. The notch filter may be applied to a down-converted, baseband signal produced by a passive mixer. | 09-18-2008 |
20090174481 | MULTI-LINEARITY MODE LNA HAVING A DEBOOST CURRENT PATH - A modified derivative superposition (MDS) low noise amplifier (LNA) includes a main current path and a cancel current path. Third-order distortion in the cancel path is used to cancel third-order distortion in the main path. In one novel aspect, there is a separate source degeneration inductor for each of the two current paths, thereby facilitating tuning of one current path without affecting the other current path. In a second novel aspect, a deboost current path is provided that does not pass through the LNA load. The deboost current allows negative feedback to be increased without generating headroom problems. In a third novel aspect, the cancel current path and/or deboost current path is programmably disabled to reduce power consumption and improve noise figure in operational modes that do not require high linearity. | 07-09-2009 |
20090258624 | METHOD AND APPARATUS FOR PROCESSING A COMMUNICATION SIGNAL IN A RECEIVER - A receiver includes a jammer detector configured to detect the presence or the absence of jamming in a communication signal within a gain state. The receiver further includes an amplifier configured to amplify the communication signal in a high linearity receiving mode or a low linearity receiving mode, wherein the high linearity receiving mode corresponds with a lower gain for the gain state in the amplifier relative to that of the low linearity receiving mode. In addition, the receiver includes a processing unit coupled to the jammer detector, the processing unit being configured to control the amplifier to amplify the communication signal in either the high linearity receiving mode or the low linearity receiving mode, based on the output of the jammer detector detecting the presence or the absence of jamming in the communication signal. A method is also provided for processing a communication signal in a receiver. | 10-15-2009 |
20110037518 | AMPLIFIERS WITH IMPROVED LINEARITY AND NOISE PERFORMANCE - Amplifiers with improved linearity and noise performance are described. In an exemplary design, an apparatus includes first through sixth transistors. The first transistor receives an input signal and provides an amplified signal. The second transistor receives the amplified signal and provides signal drive for an output signal. The third transistor receives the input signal and provides an intermediate signal. The fourth transistor provides bias for the third transistor in a high linearity mode. The fifth transistor receives the intermediate signal and provides signal drive for the output signal in a low linearity mode. The third and fourth transistors form a deboost path that is enabled in the high linearity mode to improve linearity. The third and fifth transistors form a cascode path that is enabled in the low linearity mode to improve gain and noise performance. The sixth transistor generates distortion component used to cancel distortion component from the first transistor. | 02-17-2011 |
20110110463 | RECEIVER WITH BALANCED I/Q TRANSFORMER - A receiver with a balanced I/Q transformer is described. In an exemplary design, the receiver includes an LNA that amplifies a received RF signal and provides a single-ended RF signal to the balanced I/Q transformer. The balanced I/Q transformer includes at least one primary coil and first and second secondary coils. The first secondary coil is magnetically coupled to the at least one primary coil and provides a first differential RF signal to a first mixer. The second secondary coil is magnetically coupled to the at least one primary coil and provides a second differential RF signal to a second mixer. The first and second mixers downconvert the first and second differential RF signals with I and Q LO signals, respectively, and provide differential I and Q downconverted signals. The primary and secondary coils may be fabricated on two conductive layers of an integrated circuit. | 05-12-2011 |
20120327825 | SIGNAL SPLITTING CARRIER AGGREGATION RECEIVER ARCHITECTURE - A wireless communication device configured for receiving a multiple carrier signal is described. The wireless communication device includes a primary signal splitting carrier aggregation architecture. The primary signal splitting carrier aggregation architecture includes a primary antenna and a transceiver chip. The primary signal splitting carrier aggregation architecture reuses a first diversity/simultaneous hybrid dual receiver path. The wireless communication device also includes a secondary signal splitting carrier aggregation architecture. The secondary signal splitting carrier aggregation architecture includes a secondary antenna and a receiver chip. The secondary signal splitting carrier aggregation architecture reuses a second diversity/simultaneous hybrid dual receiver path. | 12-27-2012 |
20130003617 | RECEIVER WITH BYPASS MODE FOR IMPROVED SENSITIVITY - A receiver with bypass mode for improved sensitivity is disclosed. An apparatus is provided that includes a non-bypass signal path coupled to a receiver, the non-bypass signal path comprising a filter, a bypass signal path coupled to the receiver, the bypass signal path configure to bypass the filter, and a switch configured to couple an antenna to the non-bypass signal path during time intervals when signals transmitted by a related local transmitter are transmitted with a signal power that exceeds a threshold, and to couple the antenna to the bypass signal path during other time intervals. In another aspect, the switch is configured to couple the antenna to the non-bypass signal path during time intervals when a jamming signal in a selected frequency range is received with a signal power that exceeds a threshold, and to couple the antenna to the bypass signal path during other time intervals. | 01-03-2013 |
20130230080 | MULTIPLE-INPUT AND MULTIPLE-OUTPUT CARRIER AGGREGATION RECEIVER REUSE ARCHITECTURE - A wireless communication device configured for receiving a wireless multiple-input and multiple-output signal. The wireless communication device includes a first multiple-input and multiple-output carrier aggregation receiver reuse architecture. The first multiple-input and multiple-output carrier aggregation receiver reuse architecture includes a first antenna, a second antenna and a transceiver chip. The first multiple-input and multiple-output carrier aggregation receiver reuse architecture reuses a first carrier aggregation receiver path. The wireless communication device also includes a second multiple-input and multiple-output carrier aggregation receiver reuse architecture. The second multiple-input and multiple-output carrier aggregation receiver reuse architecture includes a third antenna, a fourth antenna and a receiver chip. The second multiple-input and multiple-output carrier aggregation receiver reuse architecture reuses a second carrier aggregation receiver path. | 09-05-2013 |
20130231064 | SINGLE-CHIP SIGNAL SPLITTING CARRIER AGGREGATION RECEIVER ARCHITECTURE - A wireless communication device configured for receiving a multiple carrier signal is described. The wireless communication device includes a single-chip signal splitting carrier aggregation receiver architecture. The single-chip signal splitting carrier aggregation receiver architecture includes a primary antenna, a secondary antenna and a transceiver chip. The single-chip signal splitting carrier aggregation receiver architecture reuses a simultaneous hybrid dual receiver path. | 09-05-2013 |
20140072001 | CARRIER AGGREGATION RECEIVER ARCHITECTURE - A receiver architecture for carrier aggregation is disclosed. In an exemplary design, an apparatus (e.g., a wireless device, a circuit module, etc.) includes a plurality of low noise amplifiers (LNAs), a plurality of switches, and at least one downconverter. The LNAs receive and amplify at least one input radio frequency (RF) signal and provide at least one amplified RF signal. The switches are coupled to the outputs of the plurality of LNAs. The at least one downconverter is coupled to the plurality of switches, downconverts the at least one amplified RF signal, and provides at least one downconverted signal. The switches reduce the number of downconverters needed to support reception of transmissions on multiple sets of carriers via multiple receive antennas. The LNAs and the switches may be implemented on at least one front-end module or a back-end module. The downconverter(s) are implemented on the back-end module. | 03-13-2014 |
20140113578 | AMPLIFIERS WITH NOISE SPLITTING - Amplifiers with noise splitting to improve noise figure are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes a plurality of amplifier circuits and at least one interconnection circuit. The amplifier circuits receive an input radio frequency (RF) signal. The interconnection circuit(s) are coupled between the plurality of amplifier circuits. Each interconnection circuit is closed to short the outputs or internal nodes of two amplifier circuits coupled to that interconnection circuit. The plurality of amplifier circuits may include a plurality of gain circuits coupled to a plurality of current buffers, one gain circuit and one current buffer for each amplifier circuit. Each amplifier circuit provides an output current, which may include a portion of the current from each of the plurality of gain circuits when the plurality of amplifier circuits are enabled. | 04-24-2014 |
20140171001 | RECEIVER CALIBRATION WITH LO SIGNAL FROM INACTIVE RECEIVER - Techniques for calibrating a receiver based on a local oscillator (LO) signal from another receiver are disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit) includes first and second local oscillator (LO) generators. The first LO generator generates a first LO signal used by a first receiver for frequency downconversion. The second LO generator generates a second LO signal used by a second receiver for frequency downconversion in a first operating mode. The second LO signal is used to generate a test signal for the first receiver in a second operating mode. The second LO signal may be provided as the test signal or may be amplitude modulated with a modulating signal to generate the test signal. The test signal may be used to calibrate residual sideband (RSB), second order input intercept point (IIP2), receive path gain, etc. | 06-19-2014 |
20140213209 | SINGLE-INPUT MULTIPLE-OUTPUT AMPLIFIERS WITH INDEPENDENT GAIN CONTROL PER OUTPUT - Amplifiers with multiple outputs and separate gain control per output are disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit) may include first and second amplifier circuits. The first amplifier circuit may receive and amplify an input radio frequency (RF) signal based on a first variable gain and provide a first amplified RF signal. The second amplifier circuit may receive and amplify the input RF signal based on a second variable gain and provide a second amplified RF signal. The input RF signal may include a plurality of transmitted signals being received by the wireless device. The first variable gain may be adjustable independently of the second variable gain. Each variable gain may be set based on the received power level of at least one transmitted signal being received by the wireless device. | 07-31-2014 |
20140240048 | AMPLIFIERS WITH MULTIPLE OUTPUTS AND CONFIGURABLE DEGENERATION INDUCTOR - Multi-output amplifiers with configurable source degeneration inductance and having good performance are disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit) includes a gain transistor and a configurable degeneration inductor for an amplifier. The gain transistor receives an input signal and provides an amplified signal. The amplifier provides a single output signal in a first operating mode or a plurality of output signals in a second operating mode. The configurable degeneration inductor is coupled to the gain transistor and provides a first source degeneration inductance in the first operating mode or a second source degeneration inductance in the second operating mode. The second source degeneration inductance is less than the first source degeneration inductance and may be dependent on the number of output signals generated in the second operating mode. | 08-28-2014 |
20140253242 | AMPLIFIERS WITH INDUCTIVE DEGENERATION AND CONFIGURABLE GAIN AND INPUT MATCHING - Amplifiers with inductive degeneration and configurable gain and input matching are disclosed. In an exemplary design, an apparatus includes a gain transistor, an inductor, and an input matching circuit for an amplifier. The gain transistor has a variable gain determined based on its bias current. The inductor is coupled between the gain transistor and circuit ground. The input matching circuit is selectively coupled to the gain transistor based on the variable gain of the gain transistor. For example, the input matching circuit may be coupled to the gain transistor in a low-gain mode and decoupled from the gain transistor in the high-gain mode. In an exemplary design, the input matching circuit includes a resistor, a capacitor, and a second transistor coupled in series. The resistor is used for input matching of the amplifier. The second transistor couples or decouples the resistor to or from the gain transistor. | 09-11-2014 |
20140266461 | SPLIT AMPLIFIERS WITH IMPROVED LINEARITY - Split amplifiers with configurable gain and linearization circuitry are disclosed. In an exemplary design, an apparatus includes first and second amplifier circuits and a linearization circuit, which may be part of an amplifier. The first and second amplifier circuits are coupled in parallel and to an amplifier input. The linearization circuit is also coupled to the amplifier input. The first and second amplifier circuits are enabled in a high-gain mode. One of the first and second amplifier circuits is enabled in a low-gain mode. The linearization circuit is enabled in the second mode and disabled in the first mode. The amplifier is split into multiple sections. Each section includes an amplifier circuit and is a fraction of the amplifier. High linearly may be obtained using one amplifier circuit and the linearization circuit in the low-gain mode. | 09-18-2014 |
20140300417 | AMPLIFIERS WITH BOOSTED OR DEBOOSTED SOURCE DEGENERATION INDUCTANCE - Amplifiers with boosted or deboosted source degeneration inductance are disclosed. In an exemplary design, an apparatus includes an amplifier circuit and a feedback circuit. The amplifier circuit receives an input signal and provides an output signal and includes a source degeneration inductor. The feedback circuit is coupled between a node of the amplifier circuit and the source degeneration inductor. The feedback circuit provides feedback to vary an input impedance of an amplifier including the amplifier circuit and the feedback circuit. The feedback circuit may be programmable and may be enabled to provide feedback or disabled to provide no feedback. Alternatively, the feedback circuit may always be enabled to provide feedback. In either case, the feedback circuit may have a variable gain to provide a variable input impedance for the amplifier. | 10-09-2014 |
20140302802 | ROUTING AND SHIELDING OF SIGNAL LINES TO IMPROVE ISOLATION - Techniques for routing and shielding signal lines to improve isolation between the signal lines are disclosed. In an exemplary design, an apparatus includes first, second, and third signal lines and a switch. The first, second, and third signal lines are configurable to carry first, second, and third signals, respectively. The switch is coupled between the second signal line and AC ground and is closed when the second signal line is not carrying the second signal. The second signal line isolates the first and third signal lines when the switch is closed. Adjacent signal lines are not active at the same time. A signal line may include positive and negative signal lines, which may have at least one cross over in order to cancel coupling between the positive and negative signal lines. | 10-09-2014 |
20140347142 | TRANSFORMER WITH INTEGRATED NOTCH FILTER - Techniques for providing low-cost and effective jammer rejection for a radio receiver. In an aspect, a notch filter is provided between a transformer and a differential mixer in the receiver. The notch frequency of the notch filter may be selected to correspond to an expected jammer frequency to effectively attenuate the jammer signal prior to down-conversion mixing by the mixer. The notch filter may be implemented using various techniques, e.g., an L-C combination having adjustable capacitance, and/or elliptic or Chebyshev filters. | 11-27-2014 |
20140348274 | RECEIVER FRONT END FOR CARRIER AGGREGATION - Techniques for providing a receiver front end supporting carrier aggregation with gain alignment and improved matching across modes. In an aspect, auxiliary circuitry is configurable to selectively enable or disable mutual coupling between a source degeneration inductor of an LNA input transistor and an auxiliary inductor. A negative turns ratio coupling is provided between the inductors, such that the effective inductance of the source degeneration inductor is lowered when mutually coupled to the auxiliary inductor. In a non-carrier aggregation (non-CA) mode, the auxiliary inductor is disabled, while in a carrier aggregation (CA) mode, the auxiliary inductor is enabled. In this manner, using a single transistor, gain alignment across non-CA and CA modes is achieved. Furthermore, matching is preserved across non-CA and CA modes using a single external matching component. | 11-27-2014 |
20150035600 | AMPLIFIERS WITH CONFIGURABLE MUTUALLY-COUPLED SOURCE DEGENERATION INDUCTORS - Amplifiers with configurable mutually-coupled source degeneration inductors are disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit) includes a gain transistor and a plurality of inductors, which may implement an amplifier. The gain transistor receives an input signal and provides an amplified signal. The plurality of inductors are mutually coupled, are coupled to the gain transistor, and provide a programmable source degeneration inductance for the gain transistor. The inductors may have a positive coupling coefficient and may provide a larger source degeneration inductance. Alternatively, the inductors may have a negative coupling coefficient and may provide a smaller source degeneration inductance. | 02-05-2015 |
20150070803 | ELECTRO-STATIC DISCHARGE PROTECTION FOR INTEGRATED CIRCUITS - Techniques for improving electro-static discharge (ESD) performance in integrated circuits (IC's). In an aspect, one or more protective diodes are provided between various nodes of the IC. For example, protective diode(s) may be provided between the drain and gate of an amplifier input transistor, and/or between the drain and ground, etc. In certain exemplary embodiments, the amplifier may be a cascode amplifier. Further aspects for effectively dealing with ESD phenomena are described. | 03-12-2015 |
20150084688 | BASEBAND PROCESSING CIRCUITRY - Techniques for designing baseband processing circuitry for radio IC's. In an aspect, techniques for differential-to-single-ended conversion in a baseband portion of the IC are disclosed to reduce the pin count and package size for RF IC's. In another aspect, the converter includes selectable narrowband and wideband amplifiers, wherein the wideband amplifiers may be implemented using transistor devices having smaller area than corresponding transistor devices of narrowband amplifiers. Further techniques for bypassing one or more elements, and for implementing a low-pass filter of the converter using an R-C filter network, are described. | 03-26-2015 |