| Patent application number | Description | Published |
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| 20090023208 | Cultivation of Primate Embryonic Cells - The invention relates to methods for culturing human embryonic stem cells by culturing the stem cells in an environment essentially free of mammalian fetal serum and in a stem cell culture medium including amino acids, vitamins, salts, minerals, transferring, insulin, albumin, and a fibroblast growth factor that is supplied from a source other than just a feeder layer the medium. Also disclosed are compositions capable of supporting the culture and proliferation of human embryonic stem cells without the need for feeder cells or for exposure of the medium to feeder cells. | 01-22-2009 |
| 20100173410 | Cultivation of Primate Embryonic Stem Cells - The invention relates to methods for culturing human embryonic stem cells by culturing the stem cells in an environment essentially free of mammalian fetal serum and in a stem cell culture medium including amino acids, vitamins, salts, minerals, transferrin, insulin, albumin, and a fibroblast growth factor that is supplied from a source other than just a feeder layer the medium. Also disclosed are compositions capable of supporting the culture and proliferation of human embryonic stem cells without the need for feeder cells or for exposure of the medium to feeder cells. | 07-08-2010 |
| Patent application number | Description | Published |
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| 20080209177 | Mechanism in a Multi-Threaded Microprocessor to Maintain Best Case Demand Instruction Redispatch - A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core. | 08-28-2008 |
| 20080263283 | System and Method for Tracking Changes in L1 Data Cache Directory - Method, system and computer program product for tracking changes in an L1 data cache directory. A method for tracking changes in an L1 data cache directory determines if data to be written to the L1 data cache is to be written to an address to be changed from an old address to a new address. If it is determined that the data to be written is to be written to an address to be changed, a determination is made if the data to be written is associated with the old address or the new address. If it is determined that the data is to be written to the new address, the data is allowed to be written to the new address following a prescribed delay after the address to be changed is changed. The method is preferably implemented in a system that provides a Store Queue (STQU) design that includes a Content Addressable Memory (CAM)-based store address tracking mechanism that includes early and late write CAM ports. The method eliminates time windows and the need for an extra copy of the L1 data cache directory. | 10-23-2008 |
| 20090198985 | DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING BRANCH TARGET ADDRESS CACHE WITH HASHED INDICES - In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including a branch target address cache (BTAC) including a plurality of entries for storing branch target address predictions. The BTAC includes index logic that selects an entry to access utilizing a BTAC index based upon at least a set of higher order bits of an instruction address and a set of lower order bits of the instruction address. | 08-06-2009 |
