| Patent application number | Description | Published |
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| 20090215605 | Process of producing a glass-ceramic, the glass-ceramic made therby and its uses - The process of making the glass-ceramic includes ceramicizing a starting glass at a heating or cooling rate during the ceramicization of at least 10 K/min, so that the glass-ceramic contains at least 50% by volume of ferroelectric crystallites with a maximum diameter of from 20 to 100 nm and not more than 10% by volume of nonferroelectric crystallitesis. The glass ceramic produced by the process contains no pores or not more than 0.01% by volume of the pores and a value of e′·V | 08-27-2009 |
| 20090279068 | Device and process for increasing the light transmission of optical elements for light having a wavelength close to the absorption edge - Described are a process and a device for increasing the light transmission of an optical element for light of a wavelength that is close to the absorption edge of the material constituting the optical element. The process involves cooling the optical element. The process is especially well suited for microlithography with immersion objectives. A preferred device is, for example, a stepper for producing electronic components. | 11-12-2009 |
| 20110028298 | GLASS-CERAMIC CONTAINING NANOSCALE BARIUM TITANATE AND PROCESS FOR THE PRODUCTION THEREOF - A process for the production of a glass-ceramic comprises the following steps:
| 02-03-2011 |
| 20110062393 | SINTERED GLASS CERAMIC AND METHOD FOR PRODUCING THE SAME - The invention provides a method for producing a glass ceramic comprising the steps of melting a starting glass that is free from alkali, except for incidental contamination, and that contains at least one garnet-forming agent and at least one oxide of a lanthanoid; grinding the starting glass to produce a glass frit; molding by pressing and sintering the glass frit until at least one garnet phase containing lanthanoids is formed. A glass ceramic produced in this way may contain 5-50% by weight of SiO | 03-17-2011 |
| 20110317329 | CAPACITOR AND METHOD OF MAKING SAME - A capacitor having a dielectric consisting of a glass layer with an alkali metal oxide content of at most 2 wt % and a thickness of at most 50 μm is provided. The capacitor includes at least two metal layers which are separated by the glass layer. The glass layer is preferably produced by a down-draw method or by an overflow down-draw fusion method. | 12-29-2011 |
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| 20080270573 | Method and Data Processing System for Providing XML Data - A method and systems for providing XML data is disclosed. In accordance with an embodiment of the invention, a second data processing system, which is connected to a first data processing system via a network, receives a first request over the network from the first data processing system. The first request comprises specifications for subsequent transfers of XML data from the second data processing system to the first data processing system. The specifications specify for which type of XML documents to be transferred in subsequent transfers to the first data processing system which excerpts of XML data shall be sent. An acknowledge message, sent to the first data processing system from the second data processing system, indicates the latter's ability to provide the excerpts of XML data for the types of XML documents in the subsequent data transfers. | 10-30-2008 |
| 20090063829 | Method, System, computer program product and data processing program for verifying a processor Design - An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model comprises at least one execution unit for executing at least one instruction of a test file. The method comprises tracking each execution of each of the at least one instruction, monitoring relevant signals in each simulation cycle, maintaining information about the execution of the at least one instruction, wherein said maintained information comprises a determination of an execution length of a completely executed instruction, matching said maintained information about said completely executed instruction against a set of trap elements provided by the user through a trap file, and collecting the maintained information about the completely executed instruction in a monitor file in response to a match found between the maintained information and at least one of the trap elements. | 03-05-2009 |
| 20110113234 | User Device, Computer Program Product and Computer System for Secure Network Storage - A technique for providing secure network storage by a user device that includes one or multiple network interfaces, a driver configuration component comprising a volume mapping schema and a connection mapping schema, and a driver operable to map I/O requests for logical data blocks to one or multiple network storage volumes as specified by the volume mapping schema, the data transfer between the user device and the one or multiple network storage volumes being mapped to one or multiple network connections as specified by the connection mapping schema, the driver thereby being operable to provide the user device with a logical storage volume. | 05-12-2011 |
| 20110154110 | Verifying a Register-Transfer Level Design of an Execution Unit - A mechanism is provided for verifying a register-transfer level design of an execution unit a set of instruction records associated with a test case are generated and stored in a buffer. For each instruction record in the set of instruction records associated with the test case: the instruction record is retrieved from the buffer and sent to both a reference model and an execution unit in the data processing system. Separately, the reference model and the execution unit execute the instruction record and send results of the execution of the instruction record to a result checker in the data processing system. The result checker compares the two results and, responsive to a mismatch in the results, a failure of the test case is indicted, the verification of the test case is stopped, and all data associated with the test case is output from the buffer for analysis, | 06-23-2011 |
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| 20090032961 | SEMICONDUCTOR DEVICE HAVING A LOCALLY ENHANCED ELECTROMIGRATION RESISTANCE IN AN INTERCONNECT STRUCTURE - By forming an alloy in a highly localized manner at a transition or contact area between a via and a metal line, the probability of forming an electromigration-induced shallow void may be significantly reduced, while not unduly affecting the overall electrical resistivity of the metal line. In one illustrative embodiment, an electroless deposition process may provide the alloy-forming species on the exposed metal region on the basis of an electroless plating process. | 02-05-2009 |
| 20090085145 | SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICALLY CONDUCTIVE FEATURE AND METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A semiconductor structure comprises a semiconductor substrate. A layer of an electrically insulating material is formed over the semiconductor substrate. An electrically conductive feature is formed in the layer of electrically insulating material. A first layer of a semiconductor material is formed between the electrically conductive feature and the layer of electrically insulating material. | 04-02-2009 |
| 20090139543 | REDUCING COPPER DEFECTS DURING A WET CHEMICAL CLEANING OF EXPOSED COPPER SURFACES IN A METALLIZATION LAYER OF A SEMICONDUCTOR DEVICE - By exposing a wet chemical cleaning solution, such as hydrofluoric acid, to a pressurized inert gas ambient prior to applying the solution to patterned dielectric materials of semiconductor devices, the incorporation of oxygen into the liquid during storage and application may be significantly reduced. For instance, by generating a substantially saturated state in the pressurized inert gas ambient, a substantially oversaturated state may be achieved during the application of the liquid in ambient air, thereby enhancing efficiency of the treatment, for instance, by reducing the amount of material removal of exposed copper surfaces after trench patterning, without requiring sophisticated modifications of process chambers. | 06-04-2009 |
| 20100079959 | SEMICONDUCTOR DEVICE COMPRISING AN IN-CHIP ACTIVE HEAT TRANSFER SYSTEM - By providing thermoelectric elements, such as Peltier elements, in a semiconductor device, the overall heat management may be increased. In some illustrative embodiments, the corresponding active cooling/heating systems may be used in a stacked chip configuration to establish an efficient thermally conductive path between temperature critical circuit portions and a heat sink of the stacked chip configuration. | 04-01-2010 |
| 20100164123 | LOCAL SILICIDATION OF VIA BOTTOMS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES - Electromigration behavior in complex metallization systems of semiconductor devices may be enhanced at critical areas between a metal line and a via by locally forming a copper/silicon compound. In some illustrative embodiments, the formation of the copper/silicon compound may be combined with other treatments for cleaning the exposed surface areas and/or modifying the molecular structure thereof. | 07-01-2010 |
| 20100244028 | TEST SYSTEM AND METHOD OF REDUCING DAMAGE IN SEED LAYERS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES - During the formation of a complex metallization system, the influence of a manufacturing environment on sensitive barrier/seed material systems may be monitored or controlled by using an appropriate test pattern and applying an appropriate test strategy. For example, actual probe and reference substrates may be prepared and may be processed with and without exposure to the manufacturing environment of interest, thereby enabling an efficient evaluation of one or more parameters of the environment. Furthermore, an “optimized” manufacturing environment may be obtained on the basis of the test strategy disclosed herein. | 09-30-2010 |
| 20100248463 | ENHANCING ADHESION OF INTERLAYER DIELECTRIC MATERIALS OF SEMICONDUCTOR DEVICES BY SUPPRESSING SILICIDE FORMATION AT THE SUBSTRATE EDGE - Adhesion of dielectric layer stacks to be formed after completing the basic configuration of transistor elements may be increased by avoiding the formation of a metal silicide in the edge region of the substrate. For this purpose, a dielectric protection layer may be selectively formed in the edge region prior to a corresponding pre-clean process or immediately prior to deposition of the refractory metal. Hence, non-reacted metal may be efficiently removed from the edge region without creating a non-desired metal silicide. Hence, the further processing may be continued on the basis of enhanced process conditions for forming interlayer dielectric materials. | 09-30-2010 |
| 20100289125 | ENHANCED ELECTROMIGRATION PERFORMANCE OF COPPER LINES IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES BY SURFACE ALLOYING - In sophisticated semiconductor devices, the electromigration performance of copper metal lines at the top interface thereof may be enhanced by forming a copper alloy that is locally restricted to the interface. To this end, an appropriate alloy-forming species, such as aluminum, may be provided on the basis of a non-masked deposition process and may be subsequently removed by a non-masked etch process, wherein the characteristic of the resulting alloy may be adjusted during an intermediate heat treatment. | 11-18-2010 |
