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| 20090046423 | Internal access mechanism for a server rack - The rear panel of an electronics enclosure includes one or more heat exchangers. The rear panel can be cooling door configured to provide access to the cables and equipment located within the electronics enclosure. Such access can be provided by swinging the door open on hinges like a standard door. In the case where there are multiple heat exchangers, the door can be configured into segments, one segment per heat exchanger, and each segment includes hinges so as to be opened independently from the other segments. In some embodiments, each segment swivels open like a standard door. In other embodiments, each segment is configured to swivel up or down about a horizontal axis. In still other embodiments, each segment is configured to be disconnected from the electronics enclosure and moved out of the way, in which case each heat exchanger is connected using either flexible tubing that can be bent out of the way or quick disconnects. In other embodiments, the entire rear door, or each segment of the rear door, can be configured to slide open and closed like a drawer. | 02-19-2009 |
| 20100032143 | MICROHEAT EXCHANGER FOR LASER DIODE COOLING - A microheat exchanging assembly is configured to cool one or more heat generating devices, such as integrated circuits or laser diodes. The microheat exchanging assembly includes a first ceramic assembly thermally coupled to a first surface, and in cases, a second ceramic assembly thermally coupled to a second surface. The ceramic assembly includes one or more electrically and thermally conductive pads to be thermally coupled to a heat generating device, each conductive pad is electrically isolated from each other. The ceramic assembly includes a ceramic layer to provide this electrical isolation. A top surface and a bottom surface of the ceramic layer are each bonded to a conductive layer, such as copper, using an intermediate joining material. A brazing process is performed to bond the ceramic layer to the conductive layer via a joining layer. The joining layer is a composite of the joining material, the ceramic layer, and the conductive layer. | 02-11-2010 |
| 20110073292 | FABRICATION OF HIGH SURFACE AREA, HIGH ASPECT RATIO MINI-CHANNELS AND THEIR APPLICATION IN LIQUID COOLING SYSTEMS - The present invention provides methods and apparatuses which achieve high heat transfer in a fluid cooling system, and which do so with a small pressure drop across the system. The present invention teaches the use of wall features on the fins of a heat exchanger to cool fluid in a fluid cooling system. The present invention also discloses high aspect ratio, high surface area structures applicable in micro-heat exchangers for fluid cooling systems and cost effective methods for manufacturing the same. | 03-31-2011 |
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| 20090138119 | Chip Handler with a Buffer Traveling between Roaming Areas for Two Non-Colliding Robotic Arms - Two robotic arms roam in separate, non-overlapping areas of a test station, avoiding collisions. A traveling buffer moves along x-tracks between a front position and a back position. In the front position, a first robotic arm loads IC chips from an input tray or stacker into buffer cavities in the traveling buffer. The traveling buffer then moves along the x-tracks to the back position, where a second robotic arm moves chips from the traveling buffer to test boards for testing. After testing, the second robotic arm moves chips to a second traveling buffer, which then moves along tracks to a front position for unloading by the first robotic arm. Two traveling buffers may move on the same tracks in a loop. The buffer cavities in the traveling buffer move on internal tracks to expand and contract spacing and pitch between the front and back positions to match test-board pitch. | 05-28-2009 |
| 20100274517 | Chip Handler with a Buffer Traveling between Roaming Areas for Two Non-Colliding Robotic Arms - Two robotic arms roam in separate, non-overlapping areas of a test station, avoiding collisions. A traveling buffer moves along x-tracks between a front position and a back position. In the front position, a first robotic arm loads IC chips from an input tray or stacker into buffer cavities in the traveling buffer. The traveling buffer then moves along the x-tracks to the back position, where a second robotic arm moves chips from the traveling buffer to test boards for testing. After testing, the second robotic arm moves chips to a second traveling buffer, which then moves along tracks to a front position for unloading by the first robotic arm. Two traveling buffers may move on the same tracks in a loop. The buffer cavities in the traveling buffer move on internal tracks to expand and contract spacing and pitch between the front and back positions to match test-board pitch. | 10-28-2010 |
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| 20080284047 | Chip Package with Stiffener Ring - Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices in the first side. A polymeric stiffener ring is formed on the first side. The stiffener ring embeds the first plurality of passive devices without covering a central portion of the first surface of the substrate. A semiconductor chip is mounted on the central portion of the first surface of the substrate. | 11-20-2008 |
| 20090200659 | Chip Package with Channel Stiffener Frame - Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate. | 08-13-2009 |
| 20100276799 | Semiconductor Chip Package with Stiffener Frame and Configured Lid - Various semiconductor chip packages and methods of assembling and making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a stiffener frame to a first side of a substrate. The stiffener frame has a central opening to accommodate a semiconductor chip and an outer edge surface. A semiconductor chip is coupled to the first side in the opening. A lid is coupled to the stiffener frame with an adhesive. The lid has a first edge surface set back from the outer edge surface of the stiffener frame. The adhesive is set back from the outer edge surface of the stiffener frame. | 11-04-2010 |
| 20110241161 | CHIP PACKAGE WITH CHANNEL STIFFENER FRAME - Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate. | 10-06-2011 |
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| 20100105013 | String dispenser having an adhesive therein - A string dispenser kit is described. The string dispenser kit includes a string dispenser and a peg board. The string dispenser is formed as a string pen having a string storing element, an elongated barrel, and a tip element. The string pen is formed to store string and dispense string through the elongated barrel and from the tip element of the string dispenser. An adhesive substance is contained in the elongated barrel to douse the string. The peg board has a first plate with pegs and a second plate with corresponding holes. The second plate is formed to be positioned over the first plate. Once the string is positioned over the pegs in a desired form and the adhesive substance is dry, the second plate can be removed from the first plate to pull the string from the pegs and maintain the string in the desired form. | 04-29-2010 |
| 20100330873 | TOY VEHICLE LAUNCHER - Described is a cartridge-loaded toy vehicle launcher track set capable of launching multiple toy vehicles across a variety of tracks. The launcher includes a cartridge for holding a plurality of toy vehicles. A launching mechanism is affixed with a launching body of the launcher for receiving a toy vehicle from the cartridge and launching the toy vehicle from the launching body. Additionally, a track connector is connected with the launching body such that a toy vehicle can be launched from the housing and onto the toy vehicle track when the track is connected with the track connector. In one aspect, a string spool is connected with the launching body such that a toy vehicle can be launched from the housing and onto a string when the string is pulled taut in front of the housing. | 12-30-2010 |
| 20110003532 | Stunt figure for attaching with a mobile toy to allow for performance of a stunt - A mobile toy and a stunt figure attachable with the mobile toy are described. In a desired aspect, the mobile toy is a skateboard-shaped toy having a skateboard deck with a flywheel positioned within the skateboard deck. The stunt figure is detachably attachable with the skateboard-shaped toy through snap-fit connection mechanisms on the skateboard-shaped toy. In a desired aspect, the stunt figure comprises at least one appendage and the stunt figure is attached with the skateboard-shaped toy through at least one appendage. The stunt figure can be formed in a variety of shapes to alter the form and center of gravity of the toy to provide for a variety of stunts. | 01-06-2011 |
| 20120058706 | CORE WITH FINGER INDENTATION AND FORMED TO EXPEL AN OBJECT CONCEALED THEREIN - A rotatable core is described. The core includes a cylindrically-shaped housing having an indentation area. The indentation area is formed to guide a user where to place their finger for launching, such that by pressing down on the indentation area, the core is forced against a ground surface, which causes it to spin away from the user. Additionally, the core includes a housing with a cavity therein for receiving the object. A release mechanism is attached with the housing. The release mechanism includes a connector for connecting with a corresponding connector on the object and an expelling mechanism for expelling the object. Upon activation of the release mechanism, the connector releases the object and the expelling mechanism forces the object from the housing. | 03-08-2012 |
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| 20090125669 | PREVENTING DATA LOSS IN A STORAGE SYSTEM - Storage servers use a fast, non-volatile or persistent memory to store data until it can be written to slower mass storage devices such as disk drives. If the server crashes before a write can complete, the data remains safely stored in non-volatile memory. If the data cannot be committed to disk when the server reboots (e.g. because the destination mass storage device is unavailable), it is stored in a file. When the disk reappears, the data in the file may be used to restore a file or file system on the disk to a consistent state. | 05-14-2009 |
| 20090222829 | METHOD AND APPARATUS FOR DECOMPOSING I/O TASKS IN A RAID SYSTEM - A data access request to a file system is decomposed into a plurality of lower-level I/O tasks. A logical combination of physical storage components is represented as a hierarchical set of objects. A parent I/O task is generated from a first object in response to the data access request. A child I/O task is generated from a second object to implement a portion of the parent I/O task. The parent I/O task is suspended until the child I/O task completes. The child I/O task is executed in response to an occurrence of an event that a resource required by the child I/O task is available. The parent I/O task is resumed upon an event indicating completion of the child I/O task. Scheduling of any child I/O task is not conditional on execution of the parent I/O task, and a state diagram regulates the child I/O tasks. | 09-03-2009 |
| 20110191780 | METHOD AND APPARATUS FOR DECOMPOSING I/O TASKS IN A RAID SYSTEM - A data access request to a file system is decomposed into a plurality of lower-level I/O tasks. A logical combination of physical storage components is represented as a hierarchical set of objects. A parent I/O task is generated from a first object in response to the data access request. A child I/O task is generated from a second object to implement a portion of the parent I/O task. The parent I/O task is suspended until the child I/O task completes. The child I/O task is executed in response to an occurrence of an event that a resource required by the child I/O task is available. The parent I/O task is resumed upon an event indicating completion of the child I/O task. Scheduling of any child I/O task is not conditional on execution of the parent I/O task, and a state diagram regulates the child I/O tasks. | 08-04-2011 |
| 20120079322 | PREVENTING DATA LOSS IN A STORAGE SYSTEM - Storage servers use a fast, non-volatile or persistent memory to store data until it can be written to slower mass storage devices such as disk drives. If the server crashes before a write can complete, the data remains safely stored in non-volatile memory. If the data cannot be committed to disk when the server reboots (e.g. because the destination mass storage device is unavailable), it is stored in a file. When the disk reappears, the data in the file may be used to restore a file or filesystem on the disk to a consistent state. | 03-29-2012 |
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| 20100168027 | BPC-1: A SECRETED BRAIN-SPECIFIC PROTEIN EXPRESSED AND SECRETED BY PROSTATE AND BLADDER CANCER CELLS - Described is a novel gene and its encoded secreted tumor antigen, termed BPC-1, and to diagnostic and therapeutic methods and compositions useful in the management of various cancers which express BPC-1, particularly including prostate cancer and bladder cancer. In human normal tissues, BPC-1 is only expressed in certain tissues of the brain. However, BPC-1 is expressed at high levels in prostate cancer cells and is also expressed in bladder cancer cells. The structure of BPC-1 includes a signal sequence and a CUB domain. BPC-1 protein is secreted. Preliminary experimental evidence suggests that BPC-1 is directly involved in oncogenesis or maintenance of the transformed phenotype of cancer cells expressing BPC-1. BPC-1 also appears to bind specifically to a cellular protein expressed in prostate cancer cells and other cells. | 07-01-2010 |
| 20100173297 | NOVEL SERPENTINE TRANSMEMBRANE ANTIGENS EXPRESSED IN HUMAN CANCERS AND USES THEREOF - Described is a novel family of cell surface serpentine transmembrane antigens. Two of the proteins in this family are exclusively or predominantly expressed in the prostate, as well as in prostate cancer, and thus members of this family have been termed “STEAP” (Six Transmembrane Epithelial Antigens of the Prostate). Four particular human STEAPs are described and characterized herein. The prototype member of the STEAP family, STEAP-1, appears to be a type IIIa membrane protein expressed predominantly in prostate cells in normal human tissues. Structurally, STEAP-1 is a 339 amino acid protein characterized by a molecular topology of six transmembrane domains and intracellular N- and C-termini, suggesting that it folds in a “serpentine” manner into three extracellular and two intracellular loops. STEAP-1 protein expression is maintained at high levels across various stages of prostate cancer. Moreover, STEAP-1 is highly over-expressed in certain other human cancers. | 07-08-2010 |
| 20100190962 | NOVEL SERPENTINE TRANSMEMBRANE ANTIGENS EXPRESSED IN HUMAN CANCERS AND USES THEREOF - Described is a novel family of cell surface serpentine transmembrane antigens. Two of the proteins in this family are exclusively or predominantly expressed in the prostate, as well as in prostate cancer, and thus members of this family have been termed “STEAP” (Six Transmembrane Epithelial Antigens of the Prostate). Four particular human STEAPs are described and characterized herein. The prototype member of the STEAP family, STEAP-1, appears to be a type IIIa membrane protein expressed predominantly in prostate cells in normal human tissues. Structurally, STEAP-1 is a 339 amino acid protein characterized by a molecular topology of six transmembrane domains and intracellular N- and C-termini, suggesting that it folds in a “serpentine” manner into three extracellular and two intracellular loops. STEAP-1 protein expression is maintained at high levels across various stages of prostate cancer. Moreover, STEAP-1 is highly over-expressed in certain other human cancers. | 07-29-2010 |
| 20110318371 | Novel serpentine transmembrane antigens expressed in human cancers and uses thereof - Described is a novel family of cell surface serpentine transmembrane antigens. Two of the proteins in this family are exclusively or predominantly expressed in the prostate, as well as in prostate cancer, and thus members of this family have been termed “STEAP” (Six Transmembrane Epithelial Antigens of the Prostate). Four particular human STEAPs are described and characterized herein. The prototype member of the STEAP family, STEAP-1, appears to be a type IIIa membrane protein expressed predominantly in prostate cells in normal human tissues. Structurally, STEAP-1 is a 339 amino acid protein characterized by a molecular topology of six transmembrane domains and intracellular N- and C-termini, suggesting that it folds in a “serpentine” manner into three extracellular and two intracellular loops. STEAP-1 protein expression is maintained at high levels across various stages of prostate cancer. Moreover, STEAP-1 is highly over-expressed in certain other human cancers. | 12-29-2011 |
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| 20090161462 | CONTROLLING AC DISTURBANCE WHILE PROGRAMMING - A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation. | 06-25-2009 |
| 20100103732 | CONTROLLING AC DISTURBANCE WHILE PROGRAMMING - A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation. | 04-29-2010 |
| 20110235412 | CONTROLLING AC DISTURBANCE WHILE PROGRAMMING - A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation. | 09-29-2011 |
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| 20090135835 | ASYMMETRIC PACKET SWITCH AND A METHOD OF USE - The present invention relates to a packet switch and a packet switching method. An example embodiment of the present invention comprises at least three network ports, at least one instrument port, a mux-switch, a packet switch fabric, and an address table. The embodiment updates the address table to include the source address of each ingress packet of each network port and associate the source address with that network port. The mux-switch routes the ingress packet traffic of each network port according to the identity of the network port so that at least a copy of the packet traffic of one of the network ports is routed to an instrument port. The packet switch fabric routes the packets from the instrument ports to the network ports according the destination address of the packet and the identity of the network port that is associated with the destination address as recorded in the address table. | 05-28-2009 |
| 20090262745 | State-based filtering on a packet switch appliance - A packet switch appliance includes a plurality of ports. One of the plurality of ports is configured to operate as a network port connected to a packet-switching network. Another of the plurality of ports is configured to operate as a first instrument port connected to a network instrument. To filter packets, one or more packets or copies of packets received through the first network port are examined prior to the packets or copies of packets being sent out the first instrument port to determine a current state of a state-based protocol, which includes a plurality of potential states. A filter is created or modified for the first network port or the first instrument port based on the determined current state of the state-based protocol. | 10-22-2009 |
| 20100135323 | INTELLIGENT PACKET SLICING - Packets can be intelligently sliced by removing irrelevant portions of a packet, while retaining relevant portions. For a series of network packets, a packet is obtained from the network. The packet includes at least a header, one or more packet fields, and a first data payload. The protocol of the packet is determined. Once the protocol is known, the packet header is parsed to determine the position of the first data payload. Based on the determine positions of the first data payload, a modified packet is created by removing or masking the first data payload. | 06-03-2010 |
| 20100325178 | CREATING AND/OR MANAGING META-DATA FOR DATA STORAGE DEVICES USING A PACKET SWITCH APPLIANCE - A first instrument port of a packet switch appliance is connected to a first data storage device. A second port is configured as a first network port. A first meta-data tag is created for a first block of packets received through the first network port. The first block is sent to the first data storage device through the first instrument port. The first meta-data tag or copy is sent to the first data storage device and/or a storage management server. A second instrument port of the packet switch appliance is connected to a second data storage device. A second meta-data tag is created for a second block of packets received through the first network port. The second block is sent to the second data storage device through the second instrument port. The second meta-data tag or copy is sent to the second data storage device and/or the storage management server. | 12-23-2010 |
| 20110044349 | PACKET SWITCH AND METHOD OF USE - The present invention relates to a packet switch and a packet switching method. An example embodiment of the present invention comprises at least three network ports, at least one instrument port, a mux-switch, a packet switch fabric, and an address table. The embodiment updates the address table to include the source address of each ingress packet of each network port and associate the source address with that network port. The mux-switch routes the ingress packet traffic of each network port according to the identity of the network port so that at least a copy of the packet traffic of one of the network ports is routed to an instrument port. The packet switch fabric routes the packets from the instrument ports to the network ports according the destination address of the packet and the identity of the network port that is associated with the destination address as recorded in the address table. | 02-24-2011 |
| 20110058566 | PACKET SWITCH APPLIANCE WITH A PACKET SWITCHING AND PACKET PROCESSING DAUGHTER BOARD - A packet switch appliance for connection to a packet switching network, the packet switch appliance has a motherboard that includes a processor, a network switch chip, and a connector. The packet switch appliance also includes a daughter board configured to be removably connected to the motherboard through the connector. The daughter board may include one or more of a network switch chip and a processor unit. | 03-10-2011 |
| 20110205912 | PACKET TIMING MEASUREMENT - A method and apparatus for performing packet time measurements. In one embodiment, the method comprises transmitting a packet in the network from a sender to a receiver through a plurality of devices; creating a plurality of packets by copying the packet at each of the plurality of devices as the packet is being transmitted through the plurality of devices, including adding a time stamp to each packet in the plurality of packets, wherein time stamps of plurality of packets are generated with data from time stamp engines synchronized to a global clock; sending the plurality of packets with their time stamps to a tool; and performing analysis on the plurality of packets using the tool. | 08-25-2011 |
| 20110206055 | METHOD AND PACKET SWITCH APPLIANCE FOR PERFORMING PACKET DEDUPLICATION - A packet switch appliance and method for performing packet deduplication are described. In one embodiment, the packet switch appliance comprises a first network switch chip to receive packets from the network and a processor coupled to the first network switch chip and operable to perform a method comprising receiving the packets, identifying a packet as a duplicate packet if at least a portion of the packet is identical to a corresponding portion of another packet received within a predetermined period of time, and discarding the packet if the packet is the duplicate packet. | 08-25-2011 |
| 20110211443 | NETWORK SWITCH WITH BY-PASS TAP - A network switch apparatus includes a first network port, a second network port, a first inline port, a second inline port, wherein the first and second inline ports are for communication with a pass-through device, a packet switch, and a by-pass device configured to operate in a first mode of operation, wherein in the first mode of operation, the by-pass device is configured to pass a first packet received at the first network port to the packet switch. The by-pass device is configured to switch from the first mode of operation to a second mode of operation upon an occurrence of a condition, and wherein in the second mode of operation, the by-pass device is configured to transmit a second packet received at the first network port to the second network port without passing the second packet to the packet switch. | 09-01-2011 |
| 20110216771 | ASYMMETRIC PACKET SWITCH AND A METHOD OF USE - The present invention relates to a packet switch and a packet switching method. An example embodiment of the present invention comprises at least three network ports, at least one instrument port, a mux-switch, a packet switch fabric, and an address table. The embodiment updates the address table to include the source address of each ingress packet of each network port and associate the source address with that network port. The mux-switch routes the ingress packet traffic of each network port according to the identity of the network port so that at least a copy of the packet traffic of one of the network ports is routed to an instrument port. The packet switch fabric routes the packets from the instrument ports to the network ports according the destination address of the packet and the identity of the network port that is associated with the destination address as recorded in the address table. | 09-08-2011 |
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| 20090098147 | Antibody fragment-polymer conjugates and uses of same - Described are conjugates formed by an antibody fragment covalently attached to a non-proteinaceous polymer, wherein the apparent size of the conjugate is at least about 500 kD. The conjugates exhibit substantially improved half-life, mean residence time, and/or clearance rate in circulation as compared to the underivatized parental antibody fragment. Also described are conjugates directed against human vascular endothelial growth factor (VEGF), human p185 receptor-like tyrosine kinase (HER2), human CD20, human CD18, human CD11a, human IgE, human apoptosis receptor-2 (Apo-2), human tumor necrosis factor-α (TNF-α), human tissue factor (TF), human α | 04-16-2009 |
| 20110104185 | ANTIBODY FRAGMENT-POLYMER CONJUGATES AND USES OF SAME - Described are conjugates formed by an antibody fragment covalently attached to a non-proteinaceous polymer, wherein the apparent size of the conjugate is at least about 500 kD. The conjugates exhibit substantially improved half-life, mean residence time, and/or clearance rate in circulation as compared to the underivatized parental antibody fragment. Also described are conjugates directed against human vascular endothelial growth factor (VEGF), human p185 receptor-like tyrosine kinase (HER2), human CD20, human CD18, human CD11a, human IgE, human apoptosis receptor-2 (Apo-2), human tumor necrosis factor-α (TNF-α), human tissue factor (TF), human α | 05-05-2011 |
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| 20080264472 | Volume compensation within a photovoltaic device - A photovoltaic device having (i) an outer transparent casing, (ii) a substrate, the substrate and the outer transparent casing defining an inner volume, (iii) at least one solar cell on the substrate, (iv) a filler layer sealing the at least one solar cell and (v) a container within the inner volume is provided. The container decreases in volume when the filler layer expands, and increases in volume when the filler layer contracts. In some instances, the container is sealed and has a plurality of ridges. In some instances, the container has an opening that is sealed by a spring loaded seal. In some instances, the container has a first opening and a second opening, where the first opening is sealed by a first spring loaded seal and the second opening is sealed by a second spring loaded seal. In some instances, the container has an elongated asteroid shape. | 10-30-2008 |
| 20080264473 | Volume compensation within a photovoltaic device - Volume compensation in photovoltaic device is provided. The photovoltaic device has an outer transparent casing and a substrate that, together, define an inner volume. At least one solar cell is on the substrate. A filler layer seals the at least one solar cell within the inner volume. A container within the inner volume has an opening in fluid communication with the filler layer. A diaphragm is affixed to the opening thereby sealing the interior of the container from the filler layer. The diaphragm is configured to decrease the volume within the container when the filler layer thermally expands and to increase the volume within the container when the filler layer thermally contracts. In some instances, the substrate is hollowed and the container is formed within this hollow. The container can have multiple openings, each sealed with a diaphragm. There can be multiple containers within the photovoltaic device. | 10-30-2008 |
| 20100147367 | Volume Compensation Within a Photovoltaic Device - A photovoltaic device having (i) an outer transparent casing, (ii) a substrate, the substrate and the outer transparent casing defining an inner volume, (iii) at least one solar cell on the substrate, (iv) a filler layer sealing the at least one solar cell and (v) a container within the inner volume is provided. The container decreases in volume when the filler layer expands, and increases in volume when the filler layer contracts. In some instances, the container is sealed and has a plurality of ridges. In some instances, the container has an opening that is sealed by a spring loaded seal. In some instances, the container has a first opening and a second opening, where the first opening is sealed by a first spring loaded seal and the second opening is sealed by a second spring loaded seal. In some instances, the container has an elongated asteroid shape. | 06-17-2010 |
| 20110168230 | APPARATUS AND METHODS FOR CONNECTING MULTIPLE PHOTOVOLTAIC MODULES - In some embodiments, an apparatus for electrically connecting a plurality of photovoltaic modules in a solar panel includes a first electrically conductive line engageable with and capable of electrically connecting a plurality of first output contacts of the photovoltaic modules along a common axis. | 07-14-2011 |
