Patent application number | Description | Published |
20100264497 | Multiple Vt Field-Effect Transistor Devices - Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate. | 10-21-2010 |
20110049645 | STRUCTURE WITH REDUCED FRINGE CAPACITANCE - A structure includes a substrate and a gate stack disposed on the substrate. The structure also includes a nitride encapsulation layer disposed on a side wall of the gate stack and which has been exposed to a plasma source. The structure also includes at least one other element contacting the nitride encapsulation layer in a region where the nitride encapsulation layer contacts the side wall of the gate stack. | 03-03-2011 |
20110051482 | CONTENT ADDRESSABLE MEMORY ARRAY PROGRAMMED TO PERFORM LOGIC OPERATIONS - A memory device for performing logical operations on two or more input variables includes a match line and first and second memory cells. The first and second memory cells collectively include a first, second, third and fourth memory element. The first, second, third and fourth memory elements may have either a first value or a second value programmed therein and wherein the first, second, third and fourth memory elements are programmed to either the high or low resistive values based on a particular logic function to be performed. | 03-03-2011 |
20110051485 | CONTENT ADDRESSABLE MEMORY ARRAY WRITING - A memory system for storing one or more addresses includes a transposable memory having word lines, bit lines, transposed word lines and transposed bit lines and that receives and stores an input array having dimensions M by N and a content addressable memory (CAM) that reads the transposed word lines of the transposable memory to form input words and that stores the input words in an N by M array. | 03-03-2011 |
20110051486 | CONTENT ADDRESSABLE MEMORY REFERENCE CLOCK - A memory system includes a content addressable memory (CAM) including a plurality of match lines, each match line having a plurality of memory cells coupled thereto. The system also includes a match detector coupled to the CAM and a reference match line having a plurality of reference memory cells coupled thereto, the reference memory cells being of the same type and the memory cells. The system also includes a match line sensor coupled to the reference match line and the match detector that determines a characteristic of the reference match line and provides a timing signal to the match detector based on the characteristic. | 03-03-2011 |
20110063019 | DUAL DIELECTRIC TRI-GATE FIELD EFFECT TRANSISTOR - A dual dielectric tri-gate field effect transistor, a method of fabricating a dual dielectric tri-gate field effect transistor, and a method of operating a dual dielectric tri-gate effect transistor are disclosed. In one embodiment, the dual dielectric tri-gate transistor comprises a substrate, an insulating layer on the substrate, and at least one semiconductor fin. A first dielectric having a first dielectric constant extends over sidewalls of the fin, and a metal layer extends over the first dielectric, and a second dielectric having a second dielectric constant is on a top surface of the fin. A gate electrode extends over the fin and the first and second dielectrics. The gate electrode and the first dielectric layer form first and second gates having a threshold voltage Vt | 03-17-2011 |
20110065244 | ASYMMETRIC FINFET DEVICE WITH IMPROVED PARASITIC RESISTANCE AND CAPACITANCE - A method for forming a fin field effect transistor (finFET) device includes, forming a fin structure in a substrate, forming a gate stack structure perpendicular to the fin structure, and implanting ions in the substrate at an angle (θ) to form a source region and a drain region in the substrate, wherein the angle (θ) is oblique relative to the source region. | 03-17-2011 |
20110073958 | ASYMMETRIC SILICON-ON-INSULATOR SRAM CELL - A memory cell having N transistors including at least one pair of access transistors, one pair of pull-down transistors, and one pair of pull-up transistors to form a memory cell, wherein N is an integer at least equal to six, wherein each of the access transistors and each of the pull-down transistors is a same one of an n-type or a p-type transistor, and each of the pull-up transistors is the other of an n-type or a p-type transistor, wherein at least one of the pair of the pull down transistors and the pair of the pull up transistors are asymmetric. | 03-31-2011 |
20110108900 | BI-DIRECTIONAL SELF-ALIGNED FET CAPACITOR - A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack. | 05-12-2011 |
20110171792 | BACK-GATED FULLY DEPLETED SOI TRANSISTOR - A fully depleted semiconductor-on-insulator (FDSOI) transistor structure includes a back gate electrode having a limited thickness and aligned to a front gate electrode. The back gate electrode is formed in a first substrate by ion implantation of dopants through a first oxide cap layer. Global alignment markers are formed in the first substrate to enable alignment of the front gate electrode to the back gate electrode. The global alignment markers enable preparation of a virtually flat substrate on the first substrate so that the first substrate can be bonded to a second substrate in a reliable manner. | 07-14-2011 |
20110191737 | GENERATION OF ASYMMETRIC CIRCUIT DEVICES - A method, system and computer program product are disclosed for creating the appropriate block level shapes to manufacture asymmetric field effect transistors (FETs). In one embodiment, the method comprises obtaining an integrated circuit design having an active region level (RX) and a gate region level (PC), each of the RX and PC levels having a multitude of shapes representing semiconductor regions; and defining a new level SD having a multitude of SD level shapes from the RX and the PC level shapes. This method further comprises identifying which ones of the new shapes are source regions and which ones are drain regions; determining which ones of the source regions are pointing up and which ones are pointing down; and copying the shapes of source regions that are pointing up and the shapes of the source regions that are pointing down onto additional, defined levels. | 08-04-2011 |
20120292678 | BI-DIRECTIONAL SELF-ALIGNED FET CAPACITOR - A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack. | 11-22-2012 |