Lee, VT
Byung Suk Lee, Essex Junction, VT US
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20110313977 | Systems and Methods for Reservoir Sampling of Streaming Data and Stream Joins - Algorithms and concepts for maintaining uniform random samples of streaming data and stream joins. These algorithms and concepts are used in systems and methods, such as wireless sensor networks and methods for implementing such networks, that generate and handle such streaming data and/or stream joins. The algorithms and concepts directed to streaming data allow one or more sample reservoirs to change size during sampling. When multiple reservoirs are maintained, some of the algorithms and concepts periodically reallocate memory among the multiple reservoirs to effectively utilize limited memory. The algorithms and concepts directed to stream joins allow reservoir sampling to proceed as a function of the probability of a join sampling operation. In memory limited situations wherein memory contains the sample reservoir and a join buffer, some of the stream join algorithms and concepts progressively increase the size of the sampling reservoir and reallocate memory from the join buffer to the reservoir. | 12-22-2011 |
Gie Lee, Essex Junction, VT US
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20110077916 | Method of Distributing a Random Variable Using Statistically Correct Spatial Interpolation Continuously With Spatially Inhomogeneous Statistical Correlation Versus Distance, Standard Deviation, and Mean - Methods for modeling a random variable with spatially inhomogenous statistical correlation versus distance, standard deviation, and mean by spatial interpolation with statistical corrections. The method includes assigning statistically independent random variable to a set of seed points in a coordinate frame and defining a plurality of test points at respective spatial locations in the coordinate frame. A equation for a random variable is determined for each of the test points by spatial interpolation from one or more of the random variable assigned to the seed points. The method further includes adjusting the equation of the random variable at each of the test point with respective correction factor equations. | 03-31-2011 |
Gie Lee, Colchester, VT US
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20090112352 | EQUIVALENT GATE COUNT YIELD ESTIMATION FOR INTEGRATED CIRCUIT DEVICES - A storage medium including a method of modeling yield for semiconductor products includes determining expected faults for each of a plurality of library elements by running a critical area analysis on each of the library elements, and assessing, from the critical area analysis, an expected number of faults per unit area, and comparing the same to actual observed faults on previously manufactured semiconductor products. Thereafter, the expected number of faults for each library element is updated in response to observed yield. A database is established, which includes the die size and expected faults for each of the library elements. Integrated circuit product die size is estimated, and library elements to be used to create the integrated circuit die are selected. Fault and size data for each of the selected library elements are obtained, the adjusted estimated faults for each of the library elements are summed, and estimated yield is calculated. | 04-30-2009 |
Koonhee Lee, South Burlington, VT US
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20080237587 | Method and circuit for stressing upper level interconnects in semiconductor devices - A device or method for effectively stressing an interconnect in a test current path of a semiconductor device, which test current path is other than a current path used during normal operation of the semiconductor device. An operational voltage is adjusted to a test voltage, the test current path is opened and the test voltage is supplied to the test current path. | 10-02-2008 |
20090006887 | System and method for addressing errors in a multiple-chip memory device - A multiple-chip memory device, comprising: a volatile memory element configured to store a plurality of bits of information, and later access the plurality of bits of information; a non-volatile memory element configured to store initial repair information identifying one or more errors in the volatile memory element; and a master memory controller configured to read the initial repair information, and to provide processed repair information and volatile memory control signals to the volatile memory element, wherein the volatile memory element is configured to store and access the plurality of bits of information based on the processed repair information and logical address information. | 01-01-2009 |
20100306605 | Apparatus and Method for Manufacturing a Multiple-Chip Memory Device - A method for manufacturing a multiple-chip memory device includes making a volatile memory element on a semiconductor substrate, examining the volatile memory element for one or more initial errors, correcting the one or more initial errors on the semiconductor substrate, incorporating the volatile memory element into the multiple-chip memory device, and incorporating a non-volatile memory element into the multiple-chip memory device. The volatile memory element is examined for one or more secondary errors, after incorporating the volatile memory element and the non-volatile memory element into the multiple-chip memory device. Repair information is stored in a non-volatile memory element, the repair information identifying the one or more secondary errors. | 12-02-2010 |
Raymond Lee, Montpelier, VT US
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20090265373 | Method and Apparatus for Rapid Tagging of Elements in a Facet Tree - A tagging application (TA) is disclosed that comprises a web interface program (WIP) and a tagging program (TP). The WIP presents the facet tree by displaying elements of the facet tree selected by the user along with a known activation method for the user to select a facet element and to assign a value to the selected facet or facet element. The user may proceed to manually tag each facet and facet element by selecting a value representing the facet element to be tagged. The user may also eliminate manual selection of many of the facets and facet elements by choosing a tagging scenario and then applying the tagging scenario. Once the user has selected a tagging scenario, and has indicated that it is to be applied to the facet element, the TP takes the selected value and applies the selected tagging scenario to populate the tagging for the user in accordance with the tagging scenario. Once the tagging has been populated, the tagging program returns the tagged facet tree to the user at the user interface. Explanatory notes may be provided to the user along with the tagged tree. | 10-22-2009 |
Sungjae Lee, Burlington, VT US
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20090057742 | CMOS VARACTOR - A varactor and method of fabricating the varactor. The varactor includes a silicon body in a silicon layer of an SOI substrate; a polysilicon electrode comprising a gate region and a plate region separated from the body by a gate dielectric layer, the gate and plate regions contiguous, the electrode electrically connected to a first pad; and a source formed in the body on a first side of the gate region, a drain formed in the body on a second and opposite side of the gate region, and a body contact formed in the body on a side of the plate region away from the gate region, the source, drain and body contact, separated from each other by regions of the body under the electrode, the source, drain and body contact electrically connected to each other and to a second pad. | 03-05-2009 |
20090108349 | HIGH-PERFORMANCE FET DEVICE LAYOUT - A fast FET, a method and system for designing the fast FET and a design structure of the fast FET. The method includes: selecting a reference design for a field effect transistor, the field effect transistor including a source, a drain, a channel between the source and drain, a gate electrode over the channel, at least one source contact to the source and at least one contact to the drain, the at least one source contact spaced a first distance from the gate electrode and the at least one drain contact spaced a second distance from the gate electrode; and adjusting the first distance and the second distance to maximize a performance parameter of the field effect transistor to create a fast design for the field effect transistor. | 04-30-2009 |