| Patent application number | Description | Published |
| 20110175789 | RF MODULE AND ANTENNA SYSTEMS - Architectures and implementations of a transceiver system for wireless communications are presented, the system including one or more antennas supporting a single frequency band or multiple frequency bands, a transmit circuit, a receive circuit, and an isolation circuit that is coupled to the one or more antennas and the transmit and receive circuits and provides adequate isolation between the transmit circuit and the receive circuit. | 07-21-2011 |
| 20110210787 | SWITCHLESS BAND SEPARATION FOR TRANSCEIVERS - A system includes a plurality of band pass filters to pass signals in separated frequency bands to or from an antenna. A matching network provides characteristic impedances. The system is designed such that the configuration of the matching network and BPFs provides high impedance to the band pass filters for those routing paths other than the band pass path as these routing paths do not transmit or receive the signals at this particular pass band. The system is further designed such that the configuration of the matching network and BPFs provides minimal insertion loss for the band pass path of for transmission and receipt of signals at this particular pass band, where each routing path has a corresponding pass band. The matching network is for coupling to an amplifier, when frequency separation is needed at the output of the amplifier to the BPFs. In one embodiment an impedance network tunes the impedance by using varying length transmission lines. | 09-01-2011 |
| 20110267244 | MULTI-FUNCTIONAL CRLH ANTENNA DEVICE - This application relates to a multi-functional Composite Right and Left Handed CRLH antenna device. A conductive element of a wireless device is incorporated into the antenna structure for reuse. In one embodiment a peripheral feature, such as a key dome, is incorporated into the antenna device. In this way, the antenna structure includes portions which are multi-functional. | 11-03-2011 |
| 20120313830 | MULTI-BAND ANTENNA - Methods and systems for extending a bandwidth of a multi-band antenna of a user device are described. A multi-band antenna includes a single radio frequency (RF) input coupled to a first antenna, the first antenna configured to provide a first resonant mode. The multi-band antenna also includes a second antenna parasitically coupled to the first antenna to provide additional resonant modes of the multi-band antenna. | 12-13-2012 |
| Patent application number | Description | Published |
| 20090016118 | NON-VOLATILE DRAM WITH FLOATING GATE AND METHOD OF OPERATION - A non-volatile capacitor-less 1T DRAM has a semiconductor substrate of a first conducting type with a surface. A first region of a second conductivity type is in the substrate on the surface. A second region of the second conductivity type is in the substrate on the surface, spaced apart from the first region. A body region of the first conductivity type is in the substrate between the first region and the second region. The body region is bound by the surface, one or more insulating regions and the first and second regions. The DRAM further has a floating gate insulated from the surface and is positioned between the first region and the second region. A control gate is capacitively coupled to the floating gate. | 01-15-2009 |
| 20090061547 | Landing Pad for Use As a Contact to a Conductive Spacer - A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure. The contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure. | 03-05-2009 |
| 20090096507 | Integrated Semiconductor Metal-Insulator-Semiconductor Capacitor - An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration. A capacitor which has high capacitance densities, low process complexity, ambipolar operation, low voltage and temperature coefficient, low external parasitic resistance and capacitance and good matching characteristics for use in analog designs that can be integrated with existing semiconductor processes results. | 04-16-2009 |
| 20100322015 | Split Gate NAND Flash Memory Structure and Array, Method of Programming, Erasing and Reading Thereof, and Method of Manufacturing - A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto. | 12-23-2010 |
| Patent application number | Description | Published |
| 20120029411 | CARPAL TUNNEL DRAINAGE - A procedure for treating carpal tunnel syndrome can involve aspirating one or more of the flexor tendons running through the carpal tunnel to reduce swelling, and hence reduce the cross-sectional area of those flexor tendons. As a result, the median nerve also running through the carpal tunnel is less constricted, and the CTS symptoms associated with such constriction can be relieved. Such relief can be enhanced by delivery of one or more therapeutic substances to the area to provide additional or supplemental symptom treatment. | 02-02-2012 |
| 20120029543 | TISSUE STRUCTURE PERFORATION SYSTEM AND METHOD - A surgical treatment can involve creating a pattern of perforations in a tissue structure to allow lengthening of that tissue structure. For example, a pattern of perforations can be created in the transverse carpal ligament of a patient suffering from carpal tunnel syndrome (CTS) that allows the carpal ligament to lengthen slightly. This lengthening can relieve pressure on the median nerve, thereby reducing the symptoms of CTS while maintaining the structural integrity of the wrist. A surgical instrument for use in perforating a tissue structure (such as the transverse ligament) can be an elongate structure with one or more retractable blades. Such a tool can be used in either an open or minimally invasive procedure to create a desired pattern of perforations in the tissue structure. | 02-02-2012 |
| 20120100125 | LOCAL DEHYDRATION FOR CARPAL TUNNEL SYNDROME - A procedure for treating carpal tunnel syndrome can involve delivering a dehydrating agent into and/or near the carpal tunnel. The dehydrating agent can reduce swelling of the flexor tendons and/or the carpal ligament in the region, thereby reducing pressure on the median nerve that also runs through the carpal tunnel. Through the use of a dehydrating agent that affects proteoglycans without affecting collagen, localized dehydration can be induced without weakening the flexor tendons, carpal ligament, and any other structures in the carpal tunnel region. | 04-26-2012 |
| 20120101325 | LOCALLY TARGETED ANTI-FIBROTIC AGENTS AND METHODS OF USE - Effective devices and methods using an antifibrotic agent are provided for treating fibrosis or treating normal fibrous tissue. The devices and methods comprise an antifibrotic agent to degrade shrink, relax or stretch at least a portion of the fibrotic tissue. In some embodiments, the methods and devices are configured to immediately release an effective amount of the antifibrotic agent within 24 hours. In some embodiments, when the device comes in contact directly or indirectly with an activator, the antifibrotic agent will be immediately released from the depot. In some embodiments, the depot provides sustained release of the antifibrotic agent over a period of up to one year to treat fibrous tissue. | 04-26-2012 |
| 20120101577 | ACTIVATABLE DEVICES CONTAINING A CHEMONUCLEOLYSIS AGENT - Effective devices and methods using a chemonucleolysis agent are provided for treating an intervertebral disc or treating spinal arachnoiditis. The devices and methods comprise a chemonucleolysis agent to degrade or to shrink at least a portion of the intervertebral disc. In some embodiments, the methods and devices are configured to immediately release an effective amount of the chemonucleolysis agent within 24 hours when the device comes in contact directly or indirectly with an activator and provide sustained release of the chemonucleolysis agent over a period of up to one year to treat the intervertebral disc. In some embodiments, the chemonucleolysis agent in the device is administered in or near the intrathecal space and/or thecal sac to treat spinal arachnoiditis. | 04-26-2012 |
| 20120101578 | DEVICES CONTAINING A CHEMONUCLEOLYSIS AGENT AND METHODS FOR TREATING AN INTERVERTEBRAL DISC OR SPINAL ARACHNOIDITIS - Effective devices and methods using a chemonucleolysis agent are provided for treating an intervertebral disc or treating spinal arachnoiditis. The devices and methods comprise a chemonucleolysis agent to degrade or to shrink at least a portion of the intervertebral disc. In some embodiments, the methods and devices are configured to immediately release an effective amount of the chemonucleolysis agent within 24 hours and provide sustained release of the chemonucleolysis agent over a period of up to one year to treat the intervertebral disc. In some embodiments, the chemonucleolysis agent in the device is administered in or near the intrathecal space and/or thecal sac to treat spinal arachnoiditis. | 04-26-2012 |
| 20120158099 | LOW LEVEL LASER THERAPY FOR LOW BACK PAIN - The invention provides an energy source emitting, such as a low level laser light, catheter having a throughbore, an energy emitting surface disposed near the distal end of the catheter that is connected, directly or indirectly, to the energy source, which allows for the application of therapeutic energy to treat internal areas of a patient that have been accessed by way of a catheter. | 06-21-2012 |
| 20120253466 | METHODS AND DEVICES FOR THE TREATMENT OF INTERVERTEBRAL DISCS DISORDERS - Devices for the treatment of intervertebral discs are described. The devices, when implanted into the nucleus pulposus of an intervertebral disc, are specifically configured with an inert outer layer and an inner layer containing at least one chemonucleolysis agent so as to provide a delayed and controlled release of the chemonucleolysis agent from the inner layer into the disc. The implant can be an elongated solid body having a tapered or rounded insertion end having at least one therapeutic agent in the inner layer of the implant surrounded by an outer layer of inert material. | 10-04-2012 |
| Patent application number | Description | Published |
| 20080202588 | METHOD AND APPARATUS FOR CONTROLLING GAS FLOW TO A PROCESSING CHAMBER - A method and apparatus for delivering gases to a semiconductor processing system are provided. In one embodiment, an apparatus for delivering gases to a semiconductor processing system includes a plurality of gas input and output lines having inlet and outlet ports. Connecting lines couple respective pairs of the gas input and gas output lines. Connecting valves are arranged to control flow through the respective connecting lines. Mass gas flow controllers are arranged to control flow into respective inlet ports. In another embodiment, a method includes providing a manifold having at least a plurality of inlet that may be selectively coupled to at least one of a plurality of outlets, flowing one or more gases through the manifold to a vacuum environment by-passing the processing chamber prior to processing or to a calibration circuit, and flowing the one or more gases into the processing chamber during substrate processing. | 08-28-2008 |
| 20080202609 | METHOD AND APPARATUS FOR CONTROLLING GAS FLOW TO A PROCESSING CHAMBER - A method and apparatus for delivering gases to a semiconductor processing system are provided. In one embodiment, an apparatus for delivering gases to a semiconductor processing system includes a plurality of gas input and output lines having inlet and outlet ports. Connecting lines couple respective pairs of the gas input and gas output lines. Connecting valves are arranged to control flow through the respective connecting lines. Mass gas flow controllers are arranged to control flow into respective inlet ports. In another embodiment, a method includes providing a manifold having at least a plurality of inlet that may be selectively coupled to at least one of a plurality of outlets, flowing one or more gases through the manifold to a vacuum environment by-passing the processing chamber prior to processing or to a calibration circuit, and flowing the one or more gases into the processing chamber during substrate processing. | 08-28-2008 |
| 20080202610 | METHOD AND APPARATUS FOR CONTROLLING GAS FLOW TO A PROCESSING CHAMBER - A method and apparatus for delivering gases to a semiconductor processing system are provided. In one embodiment, an apparatus for delivering gases to a semiconductor processing system includes a plurality of gas input and output lines having inlet and outlet ports. Connecting lines couple respective pairs of the gas input and gas output lines. Connecting valves are arranged to control flow through the respective connecting lines. Mass gas flow controllers are arranged to control flow into respective inlet ports. In another embodiment, a method includes providing a manifold having at least a plurality of inlet that may be selectively coupled to at least one of a plurality of outlets, flowing one or more gases through the manifold to a vacuum environment by-passing the processing chamber prior to processing or to a calibration circuit, and flowing the one or more gases into the processing chamber during substrate processing. | 08-28-2008 |
| 20090272717 | METHOD AND APPARATUS OF A SUBSTRATE ETCHING SYSTEM AND PROCESS - Embodiments of the invention relate to a substrate etching system and process. In one embodiment, a method may include depositing material on the substrate during a deposition process, etching a first layer of the substrate during a first etch process, and etching a second layer of the substrate during a second etch process, wherein a first bias power is applied to the substrate during the first process, and wherein a second bias power is applied to the substrate during the second etch process. In another embodiment, a system may include a gas delivery system containing a first gas panel for supplying a first gas to a chamber, a second gas panel for supplying a second gas to the chamber, and a plurality of flow controllers for directing the gases to the chamber to facilitate rapid gas transitioning between the gases to and from the chamber and the panels. | 11-05-2009 |
| 20100251828 | METHOD AND APPARATUS FOR GAS FLOW MEASUREMENT - A method and apparatus for measuring gas flow are provided. In one embodiment, a calibration circuit for gas control may be utilized to verify and/or calibrate gas flows utilized for backside cooling, process gas delivery, purge gas delivery, cleaning agent delivery, carrier gases delivery and remediation gas delivery, among others. | 10-07-2010 |
| 20110265831 | METHODS AND APPARATUS FOR PROVIDING A GAS MIXTURE TO A PAIR OF PROCESS CHAMBERS - A method and apparatus for supplying a gas mixture to a load lock chamber is described. In one embodiment, the apparatus supplies a gas mixture to a pair of process chambers, comprising a first ozone generator to provide a first gas mixture to a first process chamber, a second ozone generator to provide a second gas mixture to a second process chamber, a first gas source coupled to the first ozone generator via a first mass flow controller and a first gas line, and coupled to the second ozone generator via a second mass flow controller and a second gas line, and a second gas source coupled to the first ozone generator via a third mass flow controller and a third gas line and coupled to the second ozone generator via fourth mass flow controller and a fourth gas line. | 11-03-2011 |
| 20110265883 | METHODS AND APPARATUS FOR REDUCING FLOW SPLITTING ERRORS USING ORIFICE RATIO CONDUCTANCE CONTROL - Methods and apparatus for gas delivery to a process chamber are provided herein. In some embodiments, an apparatus for processing substrates may include a mass flow controller to provide a desired total fluid flow; a first flow control manifold comprising a first inlet, a first outlet, and a first plurality of orifices selectably coupled therebetween, wherein the first inlet is coupled to the mass flow controller; and a second flow control manifold comprising a second inlet, a second outlet, and a second plurality of orifices selectably coupled therebetween, wherein the second inlet is coupled to the mass flow controller; wherein a desired flow ratio between the first outlet and the second outlet is selectably obtainable when causing the fluid to flow through one or more of the first plurality of orifices of the first manifold and one or more of the second plurality of orifices of the second manifold. | 11-03-2011 |
| 20110265887 | APPARATUS FOR RADIAL DELIVERY OF GAS TO A CHAMBER AND METHODS OF USE THEREOF - Apparatus for the delivery of a gas to a chamber and methods of use thereof are provided herein. In some embodiments, a gas distribution system for a process chamber may include a body having a first surface configured to couple the body to an interior surface of a process chamber, the body having a opening disposed through the body; a flange disposed proximate a first end of the opening opposite the first surface of the body, the flange extending inwardly into the opening and configured to support a window thereon; and a plurality of gas distribution channels disposed within the body and fluidly coupling a channel disposed within the body and around the opening to a plurality of holes disposed in the flange, wherein the plurality of holes are disposed radially about the flange. | 11-03-2011 |
| 20110265899 | SYSTEM AND METHOD FOR CALIBRATING PRESSURE GAUGES IN A SUBSTRATE PROCESSING SYSTEM - Systems and methods for calibrating pressure gauges in one or more process chambers coupled to a transfer chamber having a transfer volume is disclosed herein. The method includes providing a first pressure in the transfer volume and in a first inner volume of a first process chamber coupled to the transfer chamber, wherein the transfer volume and the first inner volume are fluidly coupled, injecting a calibration gas into the transfer volume to raise a pressure in the transfer volume and in the first inner volume to a second pressure, measuring the second pressure using each of a reference pressure gauge coupled to the transfer chamber and a first pressure gauge coupled to the first process chamber while the transfer volume and the first inner volume are fluidly coupled, and calibrating the first pressure gauge based on a difference in the measured second pressure between the reference pressure gauge and the first pressure gauge. | 11-03-2011 |
| 20110265951 | TWIN CHAMBER PROCESSING SYSTEM - Methods and apparatus for twin chamber processing systems are disclosed, and, in some embodiments, may include a first process chamber and a second process chamber having independent processing volumes and a plurality of shared resources between the first and second process chambers. In some embodiments, the shared resources include at least one of a shared vacuum pump, a shared gas panel, or a shared heat transfer source. | 11-03-2011 |
| 20110269314 | PROCESS CHAMBERS HAVING SHARED RESOURCES AND METHODS OF USE THEREOF - Process chambers having shared resources and methods of use are provided. In some embodiments, substrate processing systems may include a first process chamber having a first substrate support disposed within the first process chamber, wherein the first substrate support has a first heater and a first cooling plate to control a temperature of the first substrate support; a second process chamber having a second substrate support disposed within the second process chamber, wherein the second substrate support has a second heater and a second cooling plate to control a temperature of the second substrate support; and a shared heat transfer fluid source having an outlet to provide a heat transfer fluid to the first cooling plate and the second cooling plate and an inlet to receive the heat transfer fluid from the first cooling plate and the second cooling plate. | 11-03-2011 |
| 20110304078 | METHODS FOR REMOVING BYPRODUCTS FROM LOAD LOCK CHAMBERS - Methods for removing process byproducts from a load lock chamber are provided herein. In some embodiments, a method for removing process byproducts from a load lock chamber may include: performing a process on a substrate disposed within a process chamber; transferring the substrate from the process chamber to a load lock chamber; and providing an inert gas to the load lock chamber via at least one gas line while transferring the substrate from the process chamber to the load lock chamber to remove process byproducts from the load lock chamber. | 12-15-2011 |
| 20120222699 | METHOD FOR REMOVING HALOGEN-CONTAINING RESIDUES FROM SUBSTRATE - Methods for removing halogen-containing residues from a substrate are provided. By combining the heat-up and plasma abatement steps, the manufacturing throughput can be improved. Further, by appropriately controlling the pressure in the abatement chamber, the removal efficiency can be improved as well. | 09-06-2012 |
| 20120222752 | METHOD EXTENDING THE SERVICE INTERVAL OF A GAS DISTRIBUTION PLATE - Methods for reducing the contamination of a gas distribution plate are provided. In one embodiment, a method for processing a substrate includes transferring the substrate into a chamber, performing a treating process on the substrate, and providing a purge gas into the chamber before or after the treating process to pump out a residue gas relative to the treating process from the chamber. The treating process includes distributing a reactant gas into the chamber through a gas distribution plate. | 09-06-2012 |
| 20120222813 | VACUUM CHAMBERS WITH SHARED PUMP - Embodiments of the present disclosure generally relate to vacuum processing chambers having different pumping requirements and connected to a shared pumping system through a single foreline. In one embodiment, the vacuum processing chambers include a high conductance pumping conduit and a low conductance pumping conduit coupled to a single high conductance foreline. In another embodiment, a plurality of unbalanced chamber groups may be connected to a common pumping system by a final foreline. | 09-06-2012 |
| Patent application number | Description | Published |
| 20100102999 | CODING SYSTEM FOR MEMORY SYSTEMS EMPLOYING HIGH-SPEED SERIAL LINKS - A method, apparatus and system employing a coder is disclosed. The coder to receive an incoming stream including a first code block and a second code block, and partition the first code block into first small code blocks, and partition the second code block into second small code blocks. The coder is further to code a memory that uses one or more serial lines for communication is performed, wherein coding includes coding the first small code blocks of the first code block and the second small code blocks of the second code block, wherein the coding of the first and second blocks is performed such that a maximum run length is maintained. | 04-29-2010 |
| 20100103929 | METHOD, APPARATUS, AND SYSTEM FOR AUTOMATIC DATA ALIGNER FOR MULTIPLE SERIAL RECEIVERS - A method, apparatus and system for employing an automatic data aligner for multiple serial receivers in serial link technologies is provided. In one embodiment, converting a transmission data path of a single bit into a parallel bit via a data aligner, wherein the data is being transmitted via one or more ports. Further, binding data transmission channels to reduce latency in transmission of the data, wherein the binding of the data transmission channels further includes inserting delay to match latency via the one or more ports. | 04-29-2010 |
| 20100295711 | 17B/20B CODING SYSTEM - A method, apparatus and system employing a 17 B/20 B coder is disclosed. The 17 B/20 B coder to receive an incoming stream including a 17 B block and a 20 B block, and partition the 17 B block into first blocks, and partitioning the 20 B into second blocks. The coder is further to code 17 B to 20 B of memory using one or more serial lines for communication is performed, wherein coding includes coding the first blocks of the 17 B block and the second blocks of the 20 B block, wherein the coding of the first and second blocks is performed such that a maximum run length is maintained. | 11-25-2010 |
| Patent application number | Description | Published |
| 20110025700 | Using a Texture Unit for General Purpose Computing - An interpolation unit, such as may be found in a texture unit or texture sampler, may be used utilized to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to an interpolation unit. The interpolation unit may use linear interpolators in order to perform the dot product calculations. | 02-03-2011 |
| 20110066806 | System and method for memory bandwidth friendly sorting on multi-core architectures - In some embodiments, the invention involves utilizing a tree merge sort in a platform to minimize cache reads/writes when sorting large amounts of data. An embodiment uses blocks of pre-sorted data residing in “leaf nodes” residing in memory storage. A pre-sorted block of data from each leaf node is read from memory and stored in faster cache memory. A tree merge sort is performed on the nodes that are cache resident until a block of data migrates to a root node. Sorted blocks reaching the root node are written to memory storage in an output list until all pre-sorted data blocks have been moved to cache and merged upward to the root. The completed output list in memory storage is a list of the fully sorted data. Other embodiments are described and claimed. | 03-17-2011 |
| 20110134137 | Texture Unit for General Purpose Computing - A texture unit may be used utilized to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to the texture unit. The texture unit may use linear interpolators in order to perform the dot product calculations. | 06-09-2011 |
| 20110148896 | Grouping Pixels to be Textured - A region or group of pixels may be textured as a unit, using a range specifier and one or more anchor pixels to define the group. In some embodiments, processing grouped pixels improves efficiency. | 06-23-2011 |
| 20110320913 | RELIABILITY SUPPORT IN MEMORY SYSTEMS WITHOUT ERROR CORRECTING CODE SUPPORT - Methods and apparatuses for error correction. A N-bit block data to be stored in a memory device is received. The memory device does not perform any error correction code (ECC) algorithm nor provide designated error correction code storage for the N-bit block of data. Data compression is applied to the N-bit data to compress the block of data to generate a M-bit compressed block of data. A K-bit ECC is computed for the M-bit compressed data, wherein M+K is less than or equal to N. The M-bit compressed data and the K-bit ECC are stored together in the memory device. | 12-29-2011 |
| 20120137074 | METHOD AND APPARATUS FOR STREAM BUFFER MANAGEMENT INSTRUCTIONS - A method and system to perform stream buffer management instructions in a processor. The stream buffer management instructions facilitate the creation and usage of a dedicated memory space or stream buffer of the processor in one embodiment of the invention. The dedicated memory space is a contiguous memory space and has a sequential or linear addressing scheme in one embodiment of the invention. The processor has logic to execute a stream buffer management instruction to copy data from a source memory address to a destination memory address that is specified with a desired level of memory hierarchy. | 05-31-2012 |
| 20120254589 | SYSTEM, APPARATUS, AND METHOD FOR ALIGNING REGISTERS - Embodiments of systems, apparatuses, and methods for performing an align instruction in a computer processor are described. In some embodiments, the execution of an align instruction causes the selective storage of data elements of two concatenated sources to be stored in a destination. | 10-04-2012 |
| 20120254592 | SYSTEMS, APPARATUSES, AND METHODS FOR EXPANDING A MEMORY SOURCE INTO A DESTINATION REGISTER AND COMPRESSING A SOURCE REGISTER INTO A DESTINATION MEMORY LOCATION - Embodiments of systems, apparatuses, and methods for performing an expand and/or compress instruction in a computer processor are described. In some embodiments, the execution of an expand instruction causes the selection of elements from a source that are to be sparsely stored in a destination based on values of the writemask and store each selected data element of the source as a sparse data element into a destination location, wherein the destination locations correspond to each writemask bit position that indicates that the corresponding data element of the source is to be stored. | 10-04-2012 |