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| 20100058099 | HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILITY OF PROGRAMMABLE LOGIC DEVICES - High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates. | 03-04-2010 |
| 20100215086 | Multi-protocol channel-aggregated configurable transceiver in an integrated circuit - Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications corresponding to a select one of a plurality of high-speed communication protocols. Another more particular embodiment disclosed includes a configurable data path through link-wide Physical Coding Sub-layer (“PCS”) circuitry including link-wide clock compensation, encoding/decoding, and scrambling/descrambling circuitry and lane striping/de-striping circuitry; the configurable data path further includes lane-wide circuitry including clock compensation, encoding/decoding, receive block sync, and Physical Medium Access sub-layer (“PMA”) circuitry, and further includes bit muxing/de-muxing circuitry coupled to Physical Medium Dependent (“PMD”) sub-layer circuitry. | 08-26-2010 |
| 20100277201 | EMBEDDED DIGITAL IP STRIP CHIP - An integrated circuit (IC) is provided. The IC includes a first region having an array of programmable logic cells. The IC also includes a second region incorporated into the IC and in communication with the first region. The second region includes standard logic cells and base cells. In one embodiment, the standard logic cells are assembled or interconnected to accommodate known protocols. The base cells include configurable logic to adapt to modifications to emerging communication protocols, which are supported by the base cells. The second region can be embedded in the first region in one embodiment. In another embodiment, the second region is defined around a perimeter of the first region. The configurable logic may be composed of hybrid logic elements that have metal mask programmable interconnections so that as emerging communication protocols evolve and are modified, the IC can be modified to accommodate to the changes in the protocol. In another embodiment, a generic device can be customized by replacing the original function with a completely new function targeting a specific application space, e.g., replacing the original function such as a PCI Express, used for computing based applications, with 40 G/100 G Ethernet and Interlaken, used in wireline applications. A method of designing an integrated circuit is also provided. | 11-04-2010 |
| 20110090101 | DIGITAL PHASE LOCKED LOOP CIRCUITRY AND METHODS - Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons. | 04-21-2011 |
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| 20080204739 | Process Excursion Detection - A method for analyzing defect information on a substrate, including logically dividing the substrate into zones, and detecting defects on the substrate to produce the defect information. The defect information from the substrate is analyzed on a zone by zone basis to produce defect level classifications for the defects within each zone. The zonal defect level classifications are analyzed according to at least one analysis method. The defect level classifications are preferably selected from a group of defect level classifications that is specified by a recipe. Preferably, the at least one analysis method includes at least one of zonal defect distribution, automatic defect classification, spatial signature analysis, and excursion detection. The defect level classifications preferably include at least one of individual defect, defect cluster, and spatial signature analysis signature. In one embodiment the defect information is logically divided into configurable zones after the defects on the substrate have been detected. | 08-28-2008 |
| 20100067781 | Process Excursion Detection - A method for analyzing defect information on a substrate, including logically dividing the substrate into zones, and detecting defects on the substrate to produce the defect information. The defect information from the substrate is analyzed on a zone by zone basis to produce defect level classifications for the defects within each zone. The zonal defect level classifications are analyzed according to at least one analysis method. The defect level classifications are preferably selected from a group of defect level classifications that is specified by a recipe. Preferably, the at least one analysis method includes at least one of zonal defect distribution, automatic defect classification, spatial signature analysis, and excursion detection. The defect level classifications preferably include at least one of individual defect, defect cluster, and spatial signature analysis signature. In one embodiment the defect information is logically divided into configurable zones after the defects on the substrate have been detected. | 03-18-2010 |
| 20110137576 | Process Excursion Detection - A method for analyzing defect information on a substrate, including logically dividing the substrate into zones, and detecting defects on the substrate to produce the defect information. The defect information from the substrate is analyzed on a zone by zone basis to produce defect level classifications for the defects within each zone. The zonal defect level classifications are analyzed according to at least one analysis method. The defect level classifications are preferably selected from a group of defect level classifications that is specified by a recipe. Preferably, the at least one analysis method includes at least one of zonal defect distribution, automatic defect classification, spatial signature analysis, and excursion detection. The defect level classifications preferably include at least one of individual defect, defect cluster, and spatial signature analysis signature. In one embodiment the defect information is logically divided into configurable zones after the defects on the substrate have been detected. | 06-09-2011 |
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| 20100181617 | Method for Forming a Patterned Thick Metallization atop a Power Semiconductor Chip - A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK | 07-22-2010 |
| 20110037120 | Shielded gate trench MOSFET device and fabrication - A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode. | 02-17-2011 |
| 20110039383 | Shielded gate trench MOSFET device and fabrication - A method for fabricating a semiconductor device includes forming a plurality of trenches, including applying a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask, forming a second polysilicon region in the at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region, including applying a fourth mask. | 02-17-2011 |
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| 20080221582 | PULMONARY STENT REMOVAL DEVICE - A removal tool for an implanted device, including pulmonary stents, occlusive devices, valved devices, and flow-restrictive devices, is provided. The removal tool includes an elongate tube having a central passage, a slideable inner member within the passage, and a coupling member disposed on the distal end of the inner member. The coupling member of the removal tool includes a distal tip configured to pierce a membrane of the implanted device. The coupling member also includes a coil or a hook configured to engage a support element of the implanted device. A method of removing implanted devices is also provided. A removal tool is placed adjacent to the device, the distal end of the tool is moved to pierce its membrane, a portion of the tool engages the support member, and the distal end of the tool is retracted along with the implanted device. | 09-11-2008 |
| 20080221703 | LOADING A DEVICE FOR A PULMONARY IMPLANT - Devices for loading a collapsible implant onto a delivery catheter. In one aspect, a loading device comprises an outer tubular structure and an inner tubular structure. The outer tubular structure comprises a narrowing passage configured to receive a catheter at one end and a collapsible implant at another end. The inner tubular structure is configured to move slidably and co-axially within the outer tubular structure. The inner tubular structure comprises a carrier pin configured to move within the narrowing passage as the inner tubular structure slides into the outer tubular structure. The sliding of the inner tubular structure into the outer tubular structure causes an implant mounted on the carrier pin to collapse as the implant moves through the narrowing passage and into the distal end of a catheter. In an optional aspect, the outer tubular structure further comprises a grasper to stabilize the catheter for receipt of the collapsible implant, and the internal diameter of the inner tubular structure varies to cause the grasper to first contract and stabilize the catheter, and then expand and release the catheter, as the grasper moves into the inner tubular structure. | 09-11-2008 |
