Patent application number | Description | Published |
20100058099 | HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILITY OF PROGRAMMABLE LOGIC DEVICES - High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates. | 03-04-2010 |
20100215086 | Multi-protocol channel-aggregated configurable transceiver in an integrated circuit - Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications corresponding to a select one of a plurality of high-speed communication protocols. Another more particular embodiment disclosed includes a configurable data path through link-wide Physical Coding Sub-layer (“PCS”) circuitry including link-wide clock compensation, encoding/decoding, and scrambling/descrambling circuitry and lane striping/de-striping circuitry; the configurable data path further includes lane-wide circuitry including clock compensation, encoding/decoding, receive block sync, and Physical Medium Access sub-layer (“PMA”) circuitry, and further includes bit muxing/de-muxing circuitry coupled to Physical Medium Dependent (“PMD”) sub-layer circuitry. | 08-26-2010 |
20100277201 | EMBEDDED DIGITAL IP STRIP CHIP - An integrated circuit (IC) is provided. The IC includes a first region having an array of programmable logic cells. The IC also includes a second region incorporated into the IC and in communication with the first region. The second region includes standard logic cells and base cells. In one embodiment, the standard logic cells are assembled or interconnected to accommodate known protocols. The base cells include configurable logic to adapt to modifications to emerging communication protocols, which are supported by the base cells. The second region can be embedded in the first region in one embodiment. In another embodiment, the second region is defined around a perimeter of the first region. The configurable logic may be composed of hybrid logic elements that have metal mask programmable interconnections so that as emerging communication protocols evolve and are modified, the IC can be modified to accommodate to the changes in the protocol. In another embodiment, a generic device can be customized by replacing the original function with a completely new function targeting a specific application space, e.g., replacing the original function such as a PCI Express, used for computing based applications, with 40 G/100 G Ethernet and Interlaken, used in wireline applications. A method of designing an integrated circuit is also provided. | 11-04-2010 |
20110090101 | DIGITAL PHASE LOCKED LOOP CIRCUITRY AND METHODS - Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons. | 04-21-2011 |
20110211621 | HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILITY OF PROGRAMMABLE LOGIC DEVICES - High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates. | 09-01-2011 |
20120307878 | MULTI-PROTOCOL MULTIPLE-DATA-RATE AUTO-SPEED NEGOTIATION ARCHITECTURE FOR A DEVICE - An interface for use in a local device includes a transmitter portion programmably configurable to at least three data rates, a receiver portion programmably configurable to those at least three data rates, and an automatic speed negotiation module operatively connected to the transmitter portion and the receiver portion to configure the transmitter portion and the receiver portion for communication with a remote device at a single data rate that is a best available one of those at least three data rates. The date rate can be adjusted by adjusting transmitter data path width and receiver data path width, adjusting a frequency of said transmitter data path and said receiver data path, and oversampling. Byte serialization or deserialization can be enabled or disabled to alter the width of the data, depending on the data rate, for transfer to/from the remainder of the local device. | 12-06-2012 |
20130265179 | DIGITAL PHASE LOCKED LOOP CIRCUITRY AND METHODS - Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons. | 10-10-2013 |
20150127856 | CONFIGURABLE MULTI-LANE SCRAMBLER FOR FLEXIBLE PROTOCOL SUPPORT - Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide. | 05-07-2015 |
Patent application number | Description | Published |
20080204739 | Process Excursion Detection - A method for analyzing defect information on a substrate, including logically dividing the substrate into zones, and detecting defects on the substrate to produce the defect information. The defect information from the substrate is analyzed on a zone by zone basis to produce defect level classifications for the defects within each zone. The zonal defect level classifications are analyzed according to at least one analysis method. The defect level classifications are preferably selected from a group of defect level classifications that is specified by a recipe. Preferably, the at least one analysis method includes at least one of zonal defect distribution, automatic defect classification, spatial signature analysis, and excursion detection. The defect level classifications preferably include at least one of individual defect, defect cluster, and spatial signature analysis signature. In one embodiment the defect information is logically divided into configurable zones after the defects on the substrate have been detected. | 08-28-2008 |
20100067781 | Process Excursion Detection - A method for analyzing defect information on a substrate, including logically dividing the substrate into zones, and detecting defects on the substrate to produce the defect information. The defect information from the substrate is analyzed on a zone by zone basis to produce defect level classifications for the defects within each zone. The zonal defect level classifications are analyzed according to at least one analysis method. The defect level classifications are preferably selected from a group of defect level classifications that is specified by a recipe. Preferably, the at least one analysis method includes at least one of zonal defect distribution, automatic defect classification, spatial signature analysis, and excursion detection. The defect level classifications preferably include at least one of individual defect, defect cluster, and spatial signature analysis signature. In one embodiment the defect information is logically divided into configurable zones after the defects on the substrate have been detected. | 03-18-2010 |
20110137576 | Process Excursion Detection - A method for analyzing defect information on a substrate, including logically dividing the substrate into zones, and detecting defects on the substrate to produce the defect information. The defect information from the substrate is analyzed on a zone by zone basis to produce defect level classifications for the defects within each zone. The zonal defect level classifications are analyzed according to at least one analysis method. The defect level classifications are preferably selected from a group of defect level classifications that is specified by a recipe. Preferably, the at least one analysis method includes at least one of zonal defect distribution, automatic defect classification, spatial signature analysis, and excursion detection. The defect level classifications preferably include at least one of individual defect, defect cluster, and spatial signature analysis signature. In one embodiment the defect information is logically divided into configurable zones after the defects on the substrate have been detected. | 06-09-2011 |
Patent application number | Description | Published |
20100181617 | Method for Forming a Patterned Thick Metallization atop a Power Semiconductor Chip - A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK | 07-22-2010 |
20110037120 | Shielded gate trench MOSFET device and fabrication - A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode. | 02-17-2011 |
20110039383 | Shielded gate trench MOSFET device and fabrication - A method for fabricating a semiconductor device includes forming a plurality of trenches, including applying a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask, forming a second polysilicon region in the at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region, including applying a fourth mask. | 02-17-2011 |
20120034775 | Method for Forming a Patterned Thick Metallization atop a Power Semiconductor Chip - A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK | 02-09-2012 |
20120037981 | Power Semiconductor Chip with a Formed Patterned Thick Metallization Atop - A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK | 02-16-2012 |
20120205737 | SHIELDED GATE TRENCH MOSFET DEVICE AND FABRICATION - A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode. | 08-16-2012 |
20140091386 | MOSFET DEVICE AND FABRICATION - A semiconductor device includes a substrate, an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; and a body region in the substrate. The top surface of the polysilicon electrode is below the bottom of the body region. | 04-03-2014 |
Patent application number | Description | Published |
20120155859 | DETERMINING METROPOLITAN OPTICAL TRANSPORT NETWORK ARCHITECTURES OPTIMIZED FOR LONG TERM EVOLUTION (LTE) NETWORKS - A device receives Long Term Evolution (LTE) architecture information, Internet protocol (IP) network architecture information, and transport network information, and determines traffic patterns of a LTE network based on the LTE architecture information. The device also generates proposed LTE metropolitan optical transport networks (OTNs) based on the determined traffic patterns and one or more of the LTE architecture information, the IP network architecture information, and the transport network information. The device further determines transit switching for the proposed LTE metropolitan OTNs, and selects, from the proposed LTE metropolitan OTNs, a metropolitan OTN optimized for the LTE network. | 06-21-2012 |
20120155872 | OPTICAL TRANSPORT NETWORK DECOUPLING USING OPTICAL DATA UNIT AND OPTICAL CHANNEL LINK AGGREGATION GROUPS (LAGS) - A network device establishes first and second Ethernet link aggregation groups (LAGs) at a first access site of an optical transport network (OTN), and creates a first optical channel (OCh) LAG subpath from the first Ethernet LAG, via a second access site of the OTN, to an Ethernet LAG at a third access site of the OTN. The network device also creates a second OCh LAG subpath from the first Ethernet LAG, via a distribution site of the OTN, to the Ethernet LAG at the third access site, and creates a first optical data unit (ODUk) LAG subpath from the second Ethernet LAG to an Ethernet LAG at the second access site. The network device further creates a second ODUk LAG subpath from the second Ethernet LAG, via the distribution site and the third access site, to the Ethernet LAG at the second access site. | 06-21-2012 |
Patent application number | Description | Published |
20080221582 | PULMONARY STENT REMOVAL DEVICE - A removal tool for an implanted device, including pulmonary stents, occlusive devices, valved devices, and flow-restrictive devices, is provided. The removal tool includes an elongate tube having a central passage, a slideable inner member within the passage, and a coupling member disposed on the distal end of the inner member. The coupling member of the removal tool includes a distal tip configured to pierce a membrane of the implanted device. The coupling member also includes a coil or a hook configured to engage a support element of the implanted device. A method of removing implanted devices is also provided. A removal tool is placed adjacent to the device, the distal end of the tool is moved to pierce its membrane, a portion of the tool engages the support member, and the distal end of the tool is retracted along with the implanted device. | 09-11-2008 |
20080221703 | LOADING A DEVICE FOR A PULMONARY IMPLANT - Devices for loading a collapsible implant onto a delivery catheter. In one aspect, a loading device comprises an outer tubular structure and an inner tubular structure. The outer tubular structure comprises a narrowing passage configured to receive a catheter at one end and a collapsible implant at another end. The inner tubular structure is configured to move slidably and co-axially within the outer tubular structure. The inner tubular structure comprises a carrier pin configured to move within the narrowing passage as the inner tubular structure slides into the outer tubular structure. The sliding of the inner tubular structure into the outer tubular structure causes an implant mounted on the carrier pin to collapse as the implant moves through the narrowing passage and into the distal end of a catheter. In an optional aspect, the outer tubular structure further comprises a grasper to stabilize the catheter for receipt of the collapsible implant, and the internal diameter of the inner tubular structure varies to cause the grasper to first contract and stabilize the catheter, and then expand and release the catheter, as the grasper moves into the inner tubular structure. | 09-11-2008 |
Patent application number | Description | Published |
20140155936 | TWIST-GRIP ANCHORS AND METHODS OF USE - Devices, systems and methods are provided for anchoring implantable medical devices to maintain an implanted position. In particular, twist-grip anchors are provided. In some embodiments, the twist-grip anchor comprises a first support having a first lumen, a second support having a second lumen, and a sleeve having a first end fixedly attached to the first support and a second end fixedly attached to the second support, wherein the first and second supports and the sleeve are aligned to allow the passage of the elongate device through the first lumen, second lumen and sleeve, and wherein rotation of at least the first support twists the sleeve so that the sleeve engages the elongate device in a manner that resists movement of the elongate device in relation to the sleeve. The anchor is then attached to the tissue, such as by suturing. | 06-05-2014 |
20140155973 | TISSUE-CAPTURED ANCHORS AND METHODS OF USE - Devices, systems and methods are provided for anchoring implantable medical devices to maintain an implanted position. In some embodiments, the medical devices are stimulation leads which are implanted near a portion of the neural anatomy for providing stimulation thereto. To maintain position of the lead, the lead is anchored with the use of a tissue-captured anchor which is attached to the lead at a desired point of anchoring. The anchor maintains position of the lead by resisting movement of the anchor between tissue layers at the point of anchoring. | 06-05-2014 |
Patent application number | Description | Published |
20110151670 | METHOD OF CONTROLLING ETCH MICROLOADING FOR A TUNGSTEN-CONTAINING LAYER - A method for etching features of different aspect ratios in a tungsten containing layer is provided. An etch gas is provided containing a tungsten etch component and a deposition component. A plasma is formed from the provided etch gas. A tungsten containing layer patterned with wide and narrow features is etched with the provided plasma. | 06-23-2011 |
20110281438 | PULSED BIAS PLASMA PROCESS TO CONTROL MICROLOADING - A method for etching a conductive layer through a mask with wider and narrower features is provided. A steady state etch gas is flowed. A steady state RF power is provided to form a plasma from the etch gas. A pulsed bias voltage is provided during the steady state etch gas flow, wherein the pulsed bias voltage has a frequency between 1 to 10,000 Hz. Wider and narrower features are etched into the conductive layer using the plasma formed from the etch gas. | 11-17-2011 |
20130029491 | METHOD OF HARD MASK CD CONTROL BY AR SPUTTERING - A method for etching features into a silicon based etch layer through a patterned hard mask in a plasma processing chamber is provided. A silicon sputtering is provided to sputter silicon from the silicon based etch layer onto sidewalls of the patterned hard mask to form sidewalls on the patterned hard mask. The etch layer is etched through the patterned hard mask. | 01-31-2013 |
20130084708 | ETCH WITH PULSED BIAS - A method for etching features into an etch layer through a patterned mask in a plasma processing chamber is provided. A main etch gas is flowed into the plasma processing chamber. The main etch gas is formed into a main etch plasma. A bias greater than 600 volts is provided. The bias is pulsed at a frequency between 1 Hz and 20 kHz with a duty cycle less than 45%. | 04-04-2013 |
20140167228 | ETCH PROCESS WITH PRE-ETCH TRANSIENT CONDITIONING - A method for etching features with different aspect ratios in an etch layer is provided. A plurality of cycles is provided wherein each cycle comprises a pre-etch transient conditioning of the etch layer, which provides a transient condition of the etch layer, wherein the transient condition has a duration and etching the etch layer for a duration, wherein the duration of the etching with respect to the duration of the transient condition is controlled to control etch aspect ratio dependence. | 06-19-2014 |
20140329391 | CONTINUOUS PLASMA ETCH PROCESS - A method for etching features with a continuous plasma is provided. A first plasma process is provided, comprising providing a flow of a first process gas into a process chamber, maintaining the continuous plasma, and stopping the flow of the first process gas into the process chamber. A transition process is provided, comprising providing a flow of a transition gas into the process chamber, maintaining the continuous plasma, and stopping the flow of the transition gas into the process chamber. A second plasma process is provided, comprising providing a flow of a second process gas into the process chamber, maintaining the continuous plasma, and stopping the second process gas into the process chamber. | 11-06-2014 |
20150348792 | CONTINUOUS PLASMA ETCH PROCESS - A method for processing a substrate in a process chamber is provided. A plurality of cycles is provided to process the substrate, wherein each cycle comprises the steps of providing a flow of a first process gas into the process chamber, stopping the flow of the first process gas into the process chamber, providing a flow of a first transition gas into the process chamber, wherein the first transition gas neutralizes a component of the first process gas, stopping the flow of the first transition gas into the process chamber, providing a flow of a second process gas into the process chamber, stopping the second process gas into the process chamber, and maintaining a continuous plasma during the cycle. | 12-03-2015 |
20150380264 | ETCH PROCESS WITH PRE-ETCH TRANSIENT CONDITIONING - A method for etching features with different aspect ratios in an etch layer is provided. A plurality of cycles is provided wherein each cycle comprises a pre-etch transient conditioning of the etch layer, which provides a transient condition of the etch layer, wherein the transient condition has a duration and etching the etch layer for a duration, wherein the duration of the etching with respect to the duration of the transient condition is controlled to control etch aspect ratio dependence. | 12-31-2015 |