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| 20090138534 | Microprocessor Shifter Circuits Utilizing Butterfly and Inverse Butterfly Routing Circuits, and Control Circuits Therefor - Microprocessor shifter circuits utilizing butterfly and inverse butterfly circuits, and control circuits therefor, are provided. The same shifter circuits can also perform complex bit manipulations at high speeds, including butterfly and inverse butterfly operations, parallel extract and deposit operations, group operations, mix operations, permutation operations, as well as instructions executed by existing microprocessors, including shift right, shift left, rotate, extract, deposit and multimedia mix operations. The shifter circuits can be provided in various combinations to provide microprocessor functional units which perform a plurality of bit manipulation operations. | 05-28-2009 |
| 20100042824 | HARDWARE TRUST ANCHORS IN SP-ENABLED PROCESSORS - A trust system and method is disclosed for use in computing devices, particularly portable devices, in which a central Authority shares secrets and sensitive data with users of the respective devices. The central Authority maintains control over how and when shared secrets and data are used. In one embodiment, the secrets and data are protected by hardware-rooted encryption and cryptographic hashing, and can be stored securely in untrusted storage. The problem of transient trust and revocation of data is reduced to that of secure key management and keeping a runtime check of the integrity of the secure storage areas containing these keys (and other secrets). These hardware-protected keys and other secrets can further protect the confidentiality and/or integrity of any amount of other information of arbitrary size (e.g., files, programs, data) by the use of strong encryption and/or keyed-hashing, respectively. In addition to secrets the Authority owns, the system provides access to third party secrets from the computing devices. In one embodiment, the hardware-rooted encryption and hashing each use a single hardware register fabricated as part of the computing device's processor or System-on-Chip (SoC) and protected from external probing. The secret data is protected while in the device even during operating system malfunctions and becomes non-accessible from storage according to various rules, one of the rules being the passage of a certain time period. The use of the keys (or other secrets) can be bound to security policies that cannot be separated from the keys (or other secrets). The Authority is also able to establish remote trust and secure communications to the devices after deployment in the field using a special tamper-resistant hardware register in the device, to enable, disable or update the keys or secrets stored securely by the device. | 02-18-2010 |
| 20100180083 | Cache Memory Having Enhanced Performance and Security Features - A cache memory having enhanced performance and security feature is provided. The cache memory includes a data array storing a plurality of data elements, a tag array storing a plurality of tags corresponding to the plurality of data elements, and an address decoder which permits dynamic memory-to-cache mapping to provide enhanced security of the data elements, as well as enhanced performance. The address decoder receives a context identifier and a plurality of index bits of an address passed to the cache memory, and determines whether a matching value in a line number register exists. The line number registers allow for dynamic memory-to-cache mapping, and their contents can be modified as desired. Methods for accessing and replacing data in a cache memory are also provided, wherein a plurality of index bits and a plurality of tag bits at the cache memory are received. The plurality of index bits are processed to determine whether a matching index exists in the cache memory and the plurality of tag bits are processed to determine whether a matching tag exists in the cache memory, and a data line is retrieved from the cache memory if both a matching tag and a matching index exist in the cache memory. A random line in the cache memory can be replaced with a data line from a main memory, or evicted without replacement, based on the combination of index and tag misses, security contexts and protection bits. User-defined and/or vendor-defined replacement procedures can be utilized to replace data lines in the cache memory. | 07-15-2010 |
| 20100228939 | Parallel Read Functional Unit for Microprocessors - A functional unit for a microprocessor is provided, which allows for fast, parallel data read, write, and manipulation operations in the microprocessor that are useful for a number of software applications, such as cryptography. The functional unit includes first and second source registers for receiving first and second data items to be processed by the functional unit, first and second banks of memory tables, a combinational logic circuit, and a decoder. The first and second banks of memory tables are in communication with the first source register, and each of the tables is indexed by an index comprising a portion of the first data item received by the first source register. Each index points to a lookup result in a respective one of the memory tables. The combinational logic circuit is in communication with the first and second banks of memory tables and the second source register, receives the lookup results, and processes the lookup results and the second data item in the second source register to produce a result data item. The decoder circuit is in communication with the combinational logic circuit, and extracts an operational code from an instruction supplied to the functional unit, decodes the operational code, and controls the combinational logic circuit in accordance with the operational code. | 09-09-2010 |
| 20100281273 | System and Method for Processor-Based Security - A system and method for processor-based security is provided, for on-chip security and trusted computing services for software applications. A processor is provided having a processor core, a cache memory, a plurality of registers for storing at least one hash value and at least one encryption key, a memory interface, and at least one on-chip instruction for creating a secure memory area in a memory external to the processor, and a hypervisor program executed by the processor. The hypervisor program instructs the processor to execute the at least one on-chip instruction to create a secure memory area for a software area for a software module, and the processor encrypts data written to, and decrypts data read from, the external memory using the at least one encryption key and the verifying data read from the external memory using the at least one hash value. Secure module interactions are provided, as well as the generation of a power-on key which can be used to protect memory in the event of a re-boot event. Lightweight, run-time attestation reports are generated which include selected information about software modules executed by the processors, for use in determining whether the processor is trusted to provide secure services. | 11-04-2010 |
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| 20100184768 | Isoprenyl Compounds and Methods Thereof - Among other things, the present invention provides novel isoprenyl compounds capable of effectively modulating inflammatory responses and pharmaceutical, cosmetic, cosmeceutical and topical compositions comprising these isoprenyl compounds. Anti-inflammatory compounds of the present invention are useful in treating or preventing diseases or conditions associated with inflammation. Proinflammatory compounds of the present invention are useful in treating or preventing diseases or conditions associated with suppression of inflammatory responses. Thus, the present invention also provides methods useful in the treatment or prevention of diseases or conditions associated with inflammation as well as methods useful in the treatment or prevention of diseases or conditions associated with suppression of inflammatory responses. | 07-22-2010 |
| 20100247461 | ANTI-INFLAMMATORY COMPLEXES - Disclosed are certain complexes of AFC compounds and binding agents. Such complexes are useful, among other things, in the treatment of inflammatory diseases or disorders. | 09-30-2010 |
| 20110053901 | ACETYL MIMIC COMPOUNDS FOR THE INHIBITION OF ISOPRENYL-S-CYSTEINYL METHYLTRANSFERASE - Among other things, the present invention provides novel compounds capable of effectively inhibiting inflammatory responses that are mediated by G-proteins or GPCRs in neutrophils, macrophages and platelets. In particular, compounds of the present invention act as inhibitors of edema, inhibitors of erythema and inhibitors of MPO (myeloperoxidase), pharmaceutical compositions containing the same compounds and the use thereof for the treatment of diseases that may benefit from edema, erythema and MPO inhibition, such as inflammation (acute or chronic), asthma, autoimmune diseases, and chronic obstructive pulmonary disease (COPD) (e.g., emphysema, chronic bronchitis and small airways disease, etc.), inflammatory responses of the immune system, skin diseases (e.g., reducing acute skin irritation for patients suffering from rosacea, atopic dermatitis, seborrheic dermatitis, psoriasis), irritable bowel syndrome (e.g., Chron's disease and ulcerative colitis, etc.), and central nervous system disorders (e.g., Parkinson's disease). | 03-03-2011 |
