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| 20110079374 | Heat Dissipating System - A heat dissipating system includes a housing having a compartment divided into first and second air channels by a partitioning board. The partitioning board includes an opening through which the first air channel is in communication with the second air channel. A driving unit is mounted in the first air channel. The driving unit includes a rotating shaft extending through the opening into the second air channel. A first impeller is mounted in the first air channel, coupled to the rotating shaft, and aligned with the opening. A second impeller is mounted in the second air channel, coupled to the rotating shaft, and aligned with the opening. The first and second impellers mounted in the first and second air channels are driven by the driving unit to simultaneously dissipate heat generated by electronic elements in the first and second air channels while having a simplified structure. | 04-07-2011 |
| 20110097195 | Heat Dissipating Fan - A heat dissipating fan includes a housing having a base and a sidewall coupled to the base. The sidewall defines a compartment. The housing further includes an air inlet, an air outlet, and a dust channel. The air inlet, the air outlet, and the dust channel are in communication with the compartment. A stator is coupled to the base of the housing. An impeller is rotatably coupled to the stator. A control element includes a driving circuit electrically connected to the stator and a rotating direction control circuit electrically connected to the driving circuit. In another embodiment, the heat dissipating fan includes a housing having a base and a lateral wall coupled to the base. The lateral wall defines a compartment. The lateral wall includes an air inlet and an air outlet both in communication with the compartment. The air inlet also acts as a dust channel. | 04-28-2011 |
| 20110110774 | Blower Fan - A blower fan includes a housing having a lateral wall defining a compartment. The housing includes an air inlet and an air outlet both in communication with the compartment. An impeller mounted in the compartment includes a hub and blades mounted on the hub. A first plane including opposite first and second end edges in the air outlet is parallel to and spaced from a second plane including a center of the hub. The compartment of the housing includes an air outlet section and a pressure accumulating section on opposite sides of the second plane. The air outlet section is located between the first and second planes. The lateral wall of the housing includes at least one air guiding hole located in the pressure accumulating section. At least one air guiding tube includes an outlet end and an inlet end coupled to the at least one air guiding hole. | 05-12-2011 |
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| 20090146884 | INTEGRATED ANTENNA FOR WORLDWIDE INTEROPERABILITY FOR MICROWAVE ACCESS (WIMAX) AND WLAN - The invention relates to an integrated antenna for worldwide interoperability for microwave access (WiMax) and wireless local area network (WLAN), which comprises a substrate, a grounding metal strip, a first radiating metal strip, and a second radiating metal strip. The first radiating metal strip is disposed on the substrate and is not connected to the grounding metal strip. The first radiating metal strip has a first portion and a second portion on two ends thereof. The first portion and the second portion are used to induce a first resonance mode and a second resonance mode, respectively. The second radiating metal strip is disposed on the substrate and is connected to the grounding metal strip. The second radiating metal strip is not connected to the first radiating metal strip. The second radiating metal strip is coupled to the first radiating metal strip to induce a third resonance mode. Therefore, the integrated antenna of the present invention is adapted to the frequencies of WiMax and WLAN. | 06-11-2009 |
| 20090167609 | ANTENNA FOR WWAN - An antenna for WWAN is disclosed, which includes a first radiating metal strip, a second radiating metal strip, a first ground strip, a connecting metal strip and a second ground strip. The first radiating metal strip has a first portion and a second portion. The second radiating metal strip is independent. The first portion is coupled with the second radiating metal strip to induce a first resonance. The second portion cooperates with the second radiating metal strip to induce a second resonance. The connecting metal strip connects the first radiating metal strip to the first ground strip. The second ground strip is independent. The ground strips are used for grounding effect and can be selectively connected to a ground end of a wireless electronic device. Therefore, the antenna can be mounted in any place of the wireless electronic device, and has stable electrical characteristic. | 07-02-2009 |
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| 20100086871 | PHOTOSENSITIVE POLYIMIDES - The invention pertains to an epoxy-modified photosensitive polyimide, which possesses excellent heat resistance, chemistry resistance, and flexibility, and can be used in a liquid photo resist or dry film resist, or used in a solder resist, coverlay film, or printed circuit board. | 04-08-2010 |
| 20100086874 | Photosensitive polymides - The invention pertains to an isocyanate-modified photosensitive polyimide. The photosensitive polyimide of the invention possesses excellent heat resistance, chemical resistance and flexibility, and can be used in a liquid photo resist composition or dry film photo resist composition, or used in a solder resist, coverlay film, or printed wiring board. | 04-08-2010 |
| 20110212402 | PHOTOSENSITIVE RESIN COMPOSITION AND ITS APPLICATION - A photosensitive resin composition comprising:
| 09-01-2011 |
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| 20080230814 | Methods for fabricating a semiconductor device - A method for fabricating a semiconductor device comprises providing a silicon-containing substrate with first, second, and third regions. First, second, and third gate stacks respectively overlie a portion of the silicon-containing substrate in the first, second, and third regions. A spacer is formed on opposing sidewalls of each of the first, second, and third gate stacks, the spacer overlying a portion of the silicon-containing substrate in the first, second, and third regions, respectively. A source/drain region is formed in a portion of the silicon-containing substrate in the first, second, and third regions, with the source/drain region adjacent to the first, second, and third gate stacks, respectively. The first, second, and third gate stacks have first, second, and third gate dielectric layers of various thicknesses and at least one thereof with a relatively thin thickness is treated by NH | 09-25-2008 |
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| 20090263361 | HUMAN TROPHOBLAST STEM CELLS AND USE THEREOF - Existence of human trophoblast stem (hTS) cells has been suspected but unproved. The isolation of hTS cells is reported in the early stage of chorionic villi by expressions of FGF4, FGFR-2, Oct4, Thy-1, and stage-specific embryonic antigens distributed in different compartments of the cell. hTS cells are able to derive into specific cell phenotypes of the three primitive embryonic layers, produce chimeric reactions in mice, and retain a normal karyotype and telomere length. In hTS cells, Oct4 and fgfr-2 expressions can be knockdown by bFGF. These facts suggest that differentiation of the hTS cells play an important role in implantation and placentation. hTS cells could be apply to human cell differentiation and for gene and cell-based therapies. | 10-22-2009 |
| 20110165682 | Human Trophoblast Stem Cells and Use Thereof - Existence of human trophoblast stem (hTS) cells has been suspected but unproved. The isolation of hTS cells is reported in the early stage of chorionic villi by expressions of FGF4, FGFR-2, Oct4, Thy-1, and stage-specific embryonic antigens distributed in different compartments of the cell. hTS cells are able to derive into specific cell phenotypes of the three primitive embryonic layers, produce chimeric reactions in mice, and retain a normal karyotype and telomere length. In hTS cells, Oct4 and fgfr-2 expressions can be knockdown by bFGF. These facts suggest that differentiation of the hTS cells play an important role in implantation and placentation. hTS cells could be apply to human cell differentiation and for gene and cell-based therapies. | 07-07-2011 |
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| 20080238720 | System And Method For Intelligent Traffic Control Using Wireless Sensor And Actuator Networks - Disclosed is a system and method for intelligent traffic control using wireless sensor and actuator networks. The system comprises a control center, M regional gateways, and N sensor and actuator nodes. The N sensor and actuator nodes and L cluster heads form L clusters. Each cluster includes a cluster head and at least a sensor and actuator node. The control center, the M regional gateways, and the N sensor and actuator nodes form a multi-layer structure. Each N sensor and actuator node may real-time detect traffic states, and exchange information with other nodes via a wireless communication having a self-recovery function. The system and method applies a distributed computing strategy to automatically adjust the traffic control on each traffic flow, thereby achieving an efficient traffic control. | 10-02-2008 |
| 20090147767 | System and method for locating a mobile node in a network - Disclosed is a system and method for locating a mobile node in a network. The system comprises a plurality of beacon nodes, at least a router, a location host, and at least a mobile node. Each beacon node broadcasts at least a beacon signal at a first channel. A mobile node receives a plurality of beacon signals, and sends a corresponding packet's information to the location host at a second channel through a router. According to the packet's information, the location host may compute the location for the mobile node. This system distributes the communication loading to different groups and channels, which may estimate the locations for lots of mobile nodes at the same time, and gives a high communication quality and a good location estimation result. | 06-11-2009 |
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| 20090134504 | Semiconductor package and packaging method for balancing top and bottom mold flows from window - A window-type semiconductor package to balance top and bottom moldflows and its method are revealed. The package primarily comprises a substrate having a slot, a chip, and an encapsulant. After die attaching, an input opening and an output opening are formed and exposed from both ends of the slot. The slot is off-center designed so that the dimension of the input opening is smaller than the one of the output opening. The encapsulant has a top molding portion formed on the top surface of the substrate and a smaller bottom molding portion formed on the bottom surface of the substrate. The mold-flowing speeds between the top molding portion and the bottom molding portion are balanced to eliminate trapped air bubbles in the top mold and to avoid the flooding of the molding compound in the bottom mold. | 05-28-2009 |
| 20090166891 | Cutting and molding in small windows to fabricate semiconductor packages - A method for cutting and molding in small windows of a window-type semiconductor package and the semiconductor package fabricated from the same are revealed. According to the method, a substrate strip has a plurality of small windows disposed at the sides or at the corners of the substrate strip. The external surface of the substrate strip includes a plurality of window molding areas surrounding the small windows and extending to the scribe lines. A plurality of chips are disposed on the substrate strip. Then, an encapsulant is formed in the small windows to encapsulate the electrical connecting components and formed on the window molding areas so that the encapsulant extends to the scribe lines. Therefore, the mold flashes at the small windows can be effectively reduced. Additionally, the encapsulnat on the window molding areas is cut when singulating the substrate units so that the adhesion area of the encapsulant to the substrate strip is increased to prevent the delamination of traces and solder mask of the substrate units. | 07-02-2009 |
| 20090294792 | CARD TYPE MEMORY PACKAGE - A card-type memory package is revealed, primarily comprising a substrate, a plurality of gold fingers, at least a memory chip, an LED chip, and an encapsulant. The memory chip and the LED chip are disposed on an encapsulated surface of the substrate with the LED chip adjacent to a rear side of the substrate. The gold fingers are attached to the substrate adjacent to a front side of the substrate. The encapsulant is formed on the encapsulated surface to encapsulate the memory chip and the LED chip with the gold fingers exposed. Therefore, the card-type memory package has the LED indication of reading and writing information with simplified assembling processes. | 12-03-2009 |
| 20090302446 | SEMICONDUCTOR PACKAGE FABRICATED BY CUTTING AND MOLDING IN SMALL WINDOWS - A method for cutting and molding in small windows of a window-type semiconductor package and the semiconductor package fabricated from the same are revealed. According to the method, a substrate strip has a plurality of small windows disposed at the sides or at the corners of the substrate strip. The external surface of the substrate strip includes a plurality of window molding areas surrounding the small windows and extending to the scribe lines. A plurality of chips are disposed on the substrate strip. Then, an encapsulant is formed in the small windows to encapsulate the electrical connecting components and formed on the window molding areas so that the encapsulant extends to the scribe lines. Therefore, the mold flashes at the small windows can be effectively reduced. Additionally, the encapsulant on the window molding areas is cut when singulating the substrate units so that the adhesion area of the encapsulant to the substrate strip is increased to prevent the delamination of traces and solder mask of the substrate units. | 12-10-2009 |
| 20100219521 | WINDOW TYPE SEMICONDUCTOR PACKAGE - A window-type semiconductor package is revealed, primarily comprising a substrate with an interconnection channel, a chip on the substrate, a die-attach adhesive between the chip and the substrate, and an encapsulant filling the interconnection channel. A first solder mask formed on the top surface of the substrate has a specific pattern. The die-attach adhesive bonds the active surface of the chip to the first solder mask with the bonding pads of the chip aligned inside the interconnection channel. The first solder mask has an opening to expose the interconnection channel and further to form an indentation from the interconnection channel to expose the top surface to prevent damaging of the active surface of the chip adjacent to the edges of the interconnection channel to ensure the integrity and yield of the final products. | 09-02-2010 |
| 20120077312 | FLIP-CHIP BONDING METHOD TO REDUCE VOIDS IN UNDERFILL MATERIAL - Disclosed is a flip-chip bonding method to reduce voids in underfill material. A substrate with connecting pads is provided. At least a chip with a plurality of bumps is bonded on the substrate and then an underfill material is formed between the chip and the substrate. Finally, the substrate is placed in a pressure oven in which a positive pressure greater than one atm is provided, meanwhile, the underfill material is thermally cured with exerted pressures to reduce bubbles or voids trapped inside the underfill material to avoid popcorn issues due to CTE mismatch between the chip and the substrate. In one embodiment, another underfill material is further formed between a plurality of chips and bubbles or voids trapped between the chips are also reduced by the pressurized curing. | 03-29-2012 |
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| 20100289133 | Stackable Package Having Embedded Interposer and Method for Making the Same - The present invention relates to a stackable package having an embedded interposer and a method for making the same. The package includes a substrate, a chip, a first embedded interposer, a circuit layer and a solder mask. The substrate has an upper surface, a bottom surface and at least one connecting pad. The connecting pad is disposed adjacent to the upper surface. The chip is disposed adjacent to the upper surface of the substrate, and is electrically connected to the substrate. The first embedded interposer encapsulates the upper surface of the substrate and the chip. The to first embedded interposer includes at least one plating through hole. The plating through hole penetrates through the first embedded interposer, and is connected to the connecting pad of the substrate. The circuit layer is disposed adjacent to the first embedded interposer, and the plating through hole is connected to the circuit layer. The circuit layer includes at least one pad. The solder mask is disposed adjacent to the circuit layer, and exposes the pad. Therefore, the package has more pads for inputting/outputting, more flexibility for stacking a top package, and a reduced total thickness. | 11-18-2010 |
| 20110156204 | Semiconductor Package and Method for Making the Same - The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a base material, a first metal layer, a first dielectric layer, a first upper electrode and a first protective layer. The first metal layer is disposed on a first surface of the base material, and includes a first inductor and a first lower electrode. The first dielectric layer is disposed on the first lower electrode. The first upper electrode is disposed on the first dielectric layer, and the first upper electrode, the first dielectric layer and the first lower electrode form a first capacitor. The first protective layer encapsulates the first inductor and the first capacitor. Whereby, the first inductor and the first lower electrode of the first capacitor are disposed on the same layer, so that the thickness of the product is reduced. | 06-30-2011 |
| 20110156246 | Semiconductor Package and Method for Making the Same - The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first capacitor, a first protective layer, a first metal layer and a second protective layer. The substrate has at least one via structure. The first capacitor is disposed on a first surface of the substrate. The first protective layer encapsulates the first capacitor. The first metal layer is disposed on the first protective layer, and includes a first inductor. The second protective layer encapsulates the first inductor. Whereby, the first inductor, the first capacitor and the via structure are integrated into the semiconductor package, so that the size of the product is reduced. | 06-30-2011 |
| 20110156247 | Semiconductor Package and Method for Making the Same - The present invention relates to a semiconductor package and a method for making the same. The semiconductor package comprises a substrate, a first metal layer, a first dielectric layer, a first upper electrode, a first protective layer, a second metal layer and a second protective layer. The substrate has at least one via structure. The first metal layer is disposed on a first surface of the substrate, and comprises a first lower electrode. The first dielectric layer is disposed on the first lower electrode. The first upper electrode is disposed on the first dielectric layer, and the first upper electrode, the first dielectric layer and the first lower electrode form a first capacitor. The first protective layer encapsulates the first capacitor. The second metal layer is disposed on the first protective layer, and comprises a first inductor. The second protective layer encapsulates the first inductor. Whereby, the first inductor, the first capacitor and the via structure are integrated into the semiconductor package, so that the size of the product is reduced. | 06-30-2011 |
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| 20090066367 | INPUT OUTPUT DEVICE FOR MIXED-VOLTAGE TOLERANT - An input output device coupled between a core circuit and a pad and including an output cell, an input cell, and a pre-driver. The output cell includes an output stage and a voltage level converter. The output stage includes a first transistor and a second transistor connected to the first transistor in serial between a first supply voltage and a second voltage. The voltage level converter generates a first gate voltage to the first transistor according to the first voltage and a data signal. When the first supply voltage is increased, the first gate voltage is increased. When the data signal is at a high level, the first transistor is turned on. The input cell includes a pull unit and a first N-type transistor. The pre-driver turns off the first and the second transistors. | 03-12-2009 |
| 20090108870 | I/O BUFFER CIRCUIT - An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit ( | 04-30-2009 |
| 20100097117 | Mixed-voltage I/O buffer - A mixed-voltage input/output (I/O) buffer includes an output buffer circuit. The output buffer circuit includes an output stage circuit, a gate-tracking circuit and a floating N-well circuit. The output stage circuit includes stacked pull-up P-type transistors and stacked pull-down N-type transistors, in which a first P-type transistor of the stacked pull-up P-type transistors and a first N-type transistor of the stacked pull-down N-type transistors are coupled to an I/O pad. The gate-tracking circuit controls gate voltage of the first P-type transistor in accordance with a voltage of the I/O pad to prevent leakage current. The floating N-well circuit provides N-well voltages for an N-well of the first P-type transistor and an N-well of a second P-type transistor, controlling gate voltage of the first P-type transistor, of the gate-tracking circuit to prevent leakage current. | 04-22-2010 |
| 20100141324 | Mixed-Voltage Tolerant I/O Buffer and Output Buffer Circuit Thereof - An output buffer circuit includes a high voltage detecting circuit, a dynamic gate bias generating circuit, an output stage circuit and a pad voltage detector. The high voltage detecting circuit detects a power supply voltage and generates a first and a second determining signals and a first and a second bias voltages according to the power supply voltage. The dynamic gate bias generating circuit is biased by the first and the second bias voltages and receives the first and the second determining signals, for converting logic control signals into corresponding gate bias voltages according to the first and the second determining signals. The pad voltage detector detects a voltage of an I/O pad and provides a pad voltage detecting signal for the output stage circuit to modify an output signal outputted to an I/O pad. A mixed-voltage input/output (I/O) buffer is disclosed herein. | 06-10-2010 |
| 20100168828 | IMPLANTABLE BIOMEDICAL CHIP WITH MODULATOR FOR A WIRELESS NEURAL STIMULATION SYSTEM - The invention relates to an implantable biomedical chip with modulator for a wireless neural stimulating system. The implantable biomedical chip comprises a power regulator, a demodulator, a baseband circuit, a D/A converter, an instrumentation amplifier, an A/D converter and a modulator. According to the invention, the modulator is mounted on the implantable biomedical chip, and can achieve full-duplex communication to improve the controllability and observability. Besides, the power consumption and area occupation is reduced as compared with using discrete components. Therefore, the integration of the implantable biomedical chip can be easily accomplished. | 07-01-2010 |
| 20100277216 | I/O Buffer Circuit - An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit ( | 11-04-2010 |
| 20110241752 | Mixed-voltage I/O buffer - A mixed-voltage I/O buffer includes an input buffer circuit. The input buffer circuit includes a first inverter, a first voltage level limiting circuit, a first voltage level pull-up circuit, an input stage circuit, and a logic calibration circuit. The first inverter inverts an input signal to generate a first control signal. The first voltage level limiting circuit limits voltage level of an external signal to generate the input signal transmitted to the first inverter to prevent electrical overstress of the first inverter. The first voltage level pull-up circuit is controlled by the first control signal to pull up voltage level of the input signal inputted into the first inverter. The input stage circuit receives the first control signal to generate corresponding digital signals inputted into a core circuit. The logic calibration circuit calibrates voltage level of the first control signal when the first inverter mis-operates due to the input signal having a low voltage level. | 10-06-2011 |
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| 20090263361 | HUMAN TROPHOBLAST STEM CELLS AND USE THEREOF - Existence of human trophoblast stem (hTS) cells has been suspected but unproved. The isolation of hTS cells is reported in the early stage of chorionic villi by expressions of FGF4, FGFR-2, Oct4, Thy-1, and stage-specific embryonic antigens distributed in different compartments of the cell. hTS cells are able to derive into specific cell phenotypes of the three primitive embryonic layers, produce chimeric reactions in mice, and retain a normal karyotype and telomere length. In hTS cells, Oct4 and fgfr-2 expressions can be knockdown by bFGF. These facts suggest that differentiation of the hTS cells play an important role in implantation and placentation. hTS cells could be apply to human cell differentiation and for gene and cell-based therapies. | 10-22-2009 |
| 20110165682 | Human Trophoblast Stem Cells and Use Thereof - Existence of human trophoblast stem (hTS) cells has been suspected but unproved. The isolation of hTS cells is reported in the early stage of chorionic villi by expressions of FGF4, FGFR-2, Oct4, Thy-1, and stage-specific embryonic antigens distributed in different compartments of the cell. hTS cells are able to derive into specific cell phenotypes of the three primitive embryonic layers, produce chimeric reactions in mice, and retain a normal karyotype and telomere length. In hTS cells, Oct4 and fgfr-2 expressions can be knockdown by bFGF. These facts suggest that differentiation of the hTS cells play an important role in implantation and placentation. hTS cells could be apply to human cell differentiation and for gene and cell-based therapies. | 07-07-2011 |
