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Lee, ID
Brady D. Lee, Idaho Falls, ID US
| Patent application number | Description | Published |
|---|---|---|
| 20090215168 | Transcriptional control in alicyclobacillus acidocaldarius and associated genes, proteins, and methods - Isolated and/or purified polypeptides and nucleic acid sequences encoding polypeptides from | 08-27-2009 |
| 20090269827 | Thermophilic and thermoacidophilic metabolism genes and enzymes from alicyclobacillus acidocaldadarius and related organisms, methods - Isolated and/or purified polypeptides and nucleic acid sequences encoding polypeptides from | 10-29-2009 |
| 20110275135 | Genetic elements, proteins, and associated methods including application of additional genetic information to gram (+) thermoacidophiles - Isolated and/or purified polypeptides and nucleic acid sequences encoding polypeptides from | 11-10-2011 |
Che-Chi Lee, Boise, ID US
| Patent application number | Description | Published |
|---|---|---|
| 20120040507 | METHODS OF FORMING A PLURALITY OF CAPACITORS - A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes, an elevationally inner insulative retaining material received laterally about the capacitor electrodes, an elevationally outer insulative retaining material received laterally about the capacitor electrodes, a first material received laterally about the capacitor electrodes elevationally inward of the inner insulative retaining material, and a second material received laterally about the capacitor electrodes elevationally between the inner and outer insulative retaining materials. Openings are anisotropically etched to extend through the outer insulative retaining material and the second material. After the anisotropic etching, remaining of the second material is isotropically etched through the openings from being received laterally about the capacitor electrodes between the inner and outer insulative retaining materials. The isotropic etching of the second material is conducted selectively relative to the capacitor electrodes and the inner and outer insulative retaining materials. The capacitor electrodes are ultimately incorporated into a plurality of capacitors. | 02-16-2012 |
Chris Lee, Boise, ID US
| Patent application number | Description | Published |
|---|---|---|
| 20090037904 | Firmware Installation - A firmware bundle is download to a non-operational storage area without changing a live copy of firmware in a device. The firmware bundle is downloaded in order to reboot the device to deploy one or more downloaded firmware packages from the non-operational storage area to the device, launch an Early Boot Installer manager to spawn and monitor the status of one or more Early Boot Installer processes contained in the firmware bundle download, determine in parallel whether a firmware install to one or more subsystems of the device is desire, and install the downloaded firmware package in parallel to one or more subsystems of the device. | 02-05-2009 |
Derek Lee, Boise, ID US
| Patent application number | Description | Published |
|---|---|---|
| 20080251887 | SERIAL SYSTEM FOR BLOWING ANTIFUSES - A serial system and method for blowing antifuses are disclosed. One embodiment of antifuse system includes a plurality of latch devices connected in series from input to output. The system also includes a plurality of antifuses. The antifuses are configured to receive an output signal from a corresponding one of the latch devices. The plurality of latch devices includes a plurality of D flip-flops connected in series. Each of the D flip-flops is configured to receive an output signal from an immediately previous D flip-flop in the serial data flow and to provide an output signal to an immediately subsequent D flip-flop in the flow. In addition, the serial system provides self-detective antifuses, thus creating reliable electrical paths while saving antifuse blowing current resources and time. | 10-16-2008 |
Hong-Wei Lee, Meridian, ID US
| Patent application number | Description | Published |
|---|---|---|
| 20090127442 | Anti-resonant reflecting optical waveguide for imager light pipe - An anti-resonant reflecting optical waveguide structure for reducing optical crosstalk in an image sensor and method of forming the same. The method includes forming a trench within a plurality of material layers and over a photo-conversion device. The trench is vertically aligned with the photo-conversion device and is filled with materials of varying refractive indices to form an anti-resonant reflecting optical waveguide structure. The anti-resonant reflecting optical waveguide structure has a core and at least two cladding structures. The cladding structure in contact with the core has a refractive index that is higher than the refractive index of the core and the refractive index of the other cladding structure. The cladding structures act as Fabry-Perot cavities for light propagating in the transverse direction, such that light entering the anti-resonant reflecting optical waveguide structure remains confined to the core. This reduces the chance of photons impinging upon neighboring photo-conversion devices. | 05-21-2009 |
| 20110006193 | ANTI-RESONANT REFLECTING OPTICAL WAVEGUIDE FOR IMAGER LIGHT PIPE - An anti-resonant reflecting optical waveguide structure for reducing optical crosstalk in an image sensor and method of forming the same. The method includes forming a trench within a plurality of material layers and over a photo-conversion device. The trench is vertically aligned with the photo-conversion device and is filled with materials of varying refractive indices to form an anti-resonant reflecting optical waveguide structure. The anti-resonant reflecting optical waveguide structure has a core and at least two cladding structures. The cladding structure in contact with the core has a refractive index that is higher than the refractive index of the core and the refractive index of the other cladding structure. The cladding structures act as Fabry-Perot cavities for light propagating in the transverse direction, such that light entering the anti-resonant reflecting optical waveguide structure remains confined to the core. This reduces the chance of photons impinging upon neighboring photo-conversion devices. | 01-13-2011 |
Ji Soo Lee, Boise, ID US
| Patent application number | Description | Published |
|---|---|---|
| 20090141145 | ANTI-ECLIPSING CIRCUIT FOR IMAGE SENSORS - An anti-eclipse circuit of an image pixel includes a clamping circuit for pulling up a voltage of a reset signal output by the pixel and an eclipse detection circuit for controllably coupling the clamping circuit output to the output of the pixel. The clamping circuit includes a source follower transistor and a switching transistor. The eclipse detection circuit includes a comparator that is operated to detect an eclipse condition. The eclipse detection circuit outputs a control signal to cause the switching transistor to conduct only when a eclipse condition is detected while the pixel is outputting a reset signal. | 06-04-2009 |
John K. Lee, Boise, ID US
| Patent application number | Description | Published |
|---|---|---|
| 20110223761 | METHODS FOR FABRICATING CONTACTS OF SEMICONDUCTOR DEVICE STRUCTURES AND METHODS FOR DESIGNING SEMICONDUCTOR DEVICE STRUCTURES - Methods for fabricating contacts of semiconductor device structures include forming a dielectric layer over a semiconductor substrate with active-device regions spaced at a first pitch, forming a first plurality of substantially in-line apertures over every second active-device region of the active-device regions, and forming a second plurality of substantially in-line apertures laterally offset from apertures of the first plurality over active-device regions over which apertures of the first plurality are not located. Methods for designing semiconductor device structures include forming at least two laterally offset sets of contacts over a substrate including active-device regions at a first pitch, the contacts being formed at a second pitch that is about twice the first pitch. | 09-15-2011 |
June Lee, Boise, ID US
| Patent application number | Description | Published |
|---|---|---|
| 20090300311 | SELECTIVE REGISTER RESET - The present disclosure includes methods, devices, modules, and systems for storing selective register reset. One method embodiment includes receiving an indication of a die and a plane associated with at least one address cycle. Such a method can also include selectively resetting a particular register of a number of registers, the particular register corresponding to the plane and the die. | 12-03-2009 |
Roger Lee, Eagle, ID US
| Patent application number | Description | Published |
|---|---|---|
| 20110291190 | System and method for integrated circuits with cylindrical gate structures - A system and method for integrated circuits with surrounding gate structures are disclosed. The integrated circuits system includes a transistor having a gate all around cylindrical (GAAC) nanowire channel with an interposed dielectric layer. The cylindrical nanowire channel being in a middle section of a semiconductor wire pattern connects the source and drain region positioned at the two opposite end sections of the same wire pattern. A method is provided for manufacturing the integrate circuits system with a GAAC transistor including forming an SOI layer wire pattern on the buried oxide layer of an SOI wafer; forming a cavity underneath the middle section of the wire pattern and shaping the middle section to cylindrically shaped channel; forming a gate electrode surrounding the cylindrical channel region with an interposed gate dielectric layer, the gate electrode being positioned on the buried oxide layer vertically towards the wire pattern; forming the source/drain regions at the two opposite end sections of the wire pattern on either sides of the gate electrode and channel. | 12-01-2011 |
| 20120032732 | HYBRID INTEGRATED SEMICONDUCTOR TRI-GATE AND SPLIT DUAL-GATE FINFET DEVICES AND METHOD FOR MANUFACTURING - A method for making an integrated circuit includes at least a tri-gate FinFET and a dual-gate FinFET. The method includes providing a semiconductor on insulator (SOI) substrate. The method also includes implanting impurities into the substrate for adjusting a threshold voltage. The method provides a nitride film overlying a surface region of the substrate and selectively etches the silicon nitride film to form a nitride cap region. The method etches the silicon layer to form a first and a second silicon fin regions. The nitride cap region is maintained on a portion of a surface region of the first silicon fin region. The method includes forming a gate dielectric, depositing a polysilicon film, and planarizing the polysilicon film by chemical mechanical polishing (CMP) using the nitride cap region as a polish stop. The method etches the polysilicon film to form gate electrodes. The method forms elevated source and drain regions. | 02-09-2012 |
Roger R. Lee, Boise, ID US
| Patent application number | Description | Published |
|---|---|---|
| 20090311843 | CONTAINER CAPACITOR STRUCTURE AND METHOD OF FORMATION THEREOF - Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via. | 12-17-2009 |