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Lee, Ichon-Si
Hye Ran Lee, Ichon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090212419 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OVERHANG FILM - An integrated circuit package system includes: connecting a first interconnect between a carrier and a bottom integrated circuit thereover; forming a film, having an overhang portion, over the bottom integrated circuit with the overhang portion over the first interconnect; mounting a top integrated circuit over the film; connecting a second interconnect between the top integrated circuit and the carrier with the overhang portion between the first interconnect and the second interconnect; and forming an encapsulation over the carrier covering the top integrated circuit, the film, the first interconnect, and the second interconnect. | 08-27-2009 |
| 20100244236 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SPREADER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package substrate; mounting an integrated circuit die on the package substrate; and attaching a heat spreader assembly, having a thermal adhesive layer formed therein, to the package substrate and the integrated circuit die. | 09-30-2010 |
Hye Young Lee, Ichon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100171537 | DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME - A delay locked loop (DLL) circuit includes a first feedback loop configured to delay a reference clock signal with a delay line, wherein the first feedback loop is further configured to generate a correction clock signal by correcting a duty cycle of the reference clock signal by adjusting a delay of the delay line; and a second feedback loop configured to generate an output clock signal by detecting a phase of the reference clock signal and delaying the correction clock signal with a delay according to the detection result. | 07-08-2010 |
| 20110291718 | CLOCK GENERATION CIRCUIT AND DELAY LOCKED LOOP USING THE SAME - A clock generation circuit includes a plurality of variable delay units configured to control a delay of an input clock signal under the control of delay control signals assigned thereto among a plurality of delay control signals, and output a plurality of delayed clock signals; a phase comparison unit configured to compare a phase of a reference clock signal which has a predetermined phase difference from the input clock signal and a phase of a delayed clock signal which is outputted from any one variable delay unit among the plurality of variable delay units; and a delay control unit configured to generate the plurality of delay control signals based on a comparison result from the phase comparison unit. | 12-01-2011 |
Hyung Dong Lee, Ichon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110024743 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a multi-chip package having a plurality of semiconductor chips. The semiconductor integrated circuit includes a signal line; and a signal loading compensation section in a semiconductor chip among the plurality of semiconductor chips, configured to apply a designed signal loading to the signal line in response to activation of a test signal. Here, the designed signal loading has a value corresponding to a signal loading component of another semiconductor chip among the plurality of semiconductor chips to the signal line. | 02-03-2011 |
| 20110074369 | SEMICONDUCTOR APPARATUS AND CALIBRATION METHOD THEREOF - A semiconductor apparatus includes a reference voltage generation unit, a comparison voltage generation unit, and a calibration unit. The reference voltage generation unit is disposed in a reference die and configured to generate a reference voltage. The comparison voltage generation unit is disposed in a die stacked on the reference die and configured to generate a comparison voltage in response to a calibration control signal. The calibration unit is configured to compare a level of the reference voltage with a level of the comparison voltage and generate the calibration control signal. | 03-31-2011 |
Jeong Woo Lee, Ichon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090257300 | FUSE INFORMATION CONTROL DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME, AND CONTROL METHOD THEREOF - A fuse information control device having a delay circuit to delay an active signal, includes a fuse circuit that outputs fuse information in response to a fuse information control signal, and a fuse information control signal generating unit that generates the fuse information control signal in response to one of the active signal and internal delay signals of the delay circuit. | 10-15-2009 |
| 20110024743 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a multi-chip package having a plurality of semiconductor chips. The semiconductor integrated circuit includes a signal line; and a signal loading compensation section in a semiconductor chip among the plurality of semiconductor chips, configured to apply a designed signal loading to the signal line in response to activation of a test signal. Here, the designed signal loading has a value corresponding to a signal loading component of another semiconductor chip among the plurality of semiconductor chips to the signal line. | 02-03-2011 |
Ji Wang Lee, Ichon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100064163 | DOMAIN CROSSING CIRCUIT OF A SEMICONDUCTOR MEMORY APPARATUS - A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal. | 03-11-2010 |
| 20100117702 | DUTY CYCLE CORRECTION APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME - A duty cycle correction apparatus includes a fixed delay unit configured to set a fixed delay time to a DLL clock signal and generate a delay rising clock signal; a variable delay unit configured to delay the DLL clock signal in response to a control signal and generate a delay falling clock signal; a duty cycle correction unit configured to generate a correction rising clock signal and a correction falling clock signal that are toggled in conformity with edge timing of the delay rising clock signal and the delay falling clock signal; and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal and generate the control signal. | 05-13-2010 |
Jong-Dae Lee, Ichon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120044767 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a plurality of unit cells. Each unit cell includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier. A read operation is performed when an input voltage is in a first voltage range. A first write operation is performed when the input voltage is in a second voltage range higher than the first voltage range. A second write operation is performed when the input voltage is in a third voltage range higher than the second voltage range. An erase operation is performed when the input voltage is higher than the third voltage range. | 02-23-2012 |
Jun Gyu Lee, Ichon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120001604 | VOLTAGE REGULATION CIRCUIT - A voltage regulation circuit includes: a first voltage divider that divides a regulation voltage with a predetermined division ratio to generate a division voltage; a first current driving force control unit configured to compare a reference voltage with the division voltage and generate a first control signal; a current driving unit configured to generate a driving current with a variable driving force based on the first control signal and a second control signal, and generate the regulation voltage; and a second current driving force control unit configured to generate the second control signal in accordance with a level variation of the regulation voltage. | 01-05-2012 |
Kang Seol Lee, Ichon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100232239 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a row path activating unit configured to generate a line connection control signal according to a received address and active command. The semiconductor memory apparatus also includes a cell array circuit unit including an input/output line switch for connecting a first input/output line in a cell block and a second input/output line extending to the outside of the cell block. The cell array also including a bit line switch for connecting a bit line pair to each other. The input/output line switch and the bit line switch are further controlled by the line connection control signal from the row path activating unit. | 09-16-2010 |
Kang Youl Lee, Ichon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100124129 | DATA WRITING APPARATUS AND METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT - A data writing apparatus includes a distributed transmission unit configured to transmit first data and second data, having been aligned to have the same timing, to data lines at mutually different timings, and a data writing unit configured to synchronize the first data and the second data having been transmitted through the data lines and to write the synchronized data in a memory area. | 05-20-2010 |
Keun Lee, Ichon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120007032 | PHASE-CHANGE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A phase-change memory device with improved deposition characteristic and a method of fabricating the same are provided. The phase-change memory device includes a semiconductor substrate having a phase-change area, a first material-rich first phase-change layer forming an inner surface of the phase-change area and comprised of a hetero compound of the first material and a second material, and a second phase-change layer formed on a surface of the first phase-change layer to fill the phase-change area. | 01-12-2012 |
| 20120009731 | METHOD OF MANUFACTURING PHASE-CHANGE RANDOM ACCESS MEMORY - A method of a phase-change random access memory (PCRAM) device is provided. The method includes forming a heat pad on a substrate, forming a phase-change material layer by injecting a deposition gas for a phase-change material and a reaction gas on the heat pad, where the phase-change material includes tellurium (Te), forming an upper electrode electrically connected to the phase-change material layer, where the tellurium (Te) is added at a ratio smaller than a normal chemical stoichiometric ratio of materials constituting the phase-change material layer. | 01-12-2012 |
Ki Hong Lee, Ichon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100099243 | METHOD FOR FORMING DIODE IN PHASE CHANGE RANDOM ACCESS MEMORY DEVICE - A method for forming a diode of a phase change random access memory device includes preparing a semiconductor substrate having a dopant area formed thereon. An insulating layer on the semiconductor substrate is formed and a contact hole is formed by etching a part of the insulating layer such that a specific region of the dopant area is exposed. A silicon layer doped with a first-type dopant is formed in the contact hole. A part of the silicon layer is doped with a second-type dopant source gas through a gas cluster ion beam process. | 04-22-2010 |
Moon Hee Lee, Ichon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090045507 | Flip chip interconnection - Methods for forming flip chip interconnection, in which the bump interconnect is defined at least in part by an underfill. The underfill includes a material that is thermally cured; that is, raising the temperature of the underfill material can result in progressive curing of the underfill through stages including a gel stage and a fully cured stage. According to the invention, during at least an early stage in the process the semiconductor chip is carried by a thermode, which is employed to control the temperature of the assembly in a specified way. Also, flip chip interconnections and flip chip packages made according to the methods of invention. | 02-19-2009 |
Myoung Jin Lee, Ichon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110051543 | SENSE AMPLIFIER AND SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME - A semiconductor integrated circuit having a sense amplifier includes first and second inverters each having an output terminal coupled to an input terminal of the other inverter. The first inverter is configured to be activated in response to a first and a third activation signals, and the second inverter is configured to be activated in response to a second and a fourth activation signals. The first and third activation signals and the second and fourth activation signals are provided through separate signal sources from each other. | 03-03-2011 |
| 20110075495 | SEMICONDUCTOR MEMORY APPARATUS AND DRIVING METHOD USINGTHE SAME - Various embodiments of a semiconductor memory apparatus and a related driving method are disclosed. According to one exemplary embodiment, a semiconductor memory apparatus may include a switching unit and a switching control unit. The switching unit couples or decouples a cell plate voltage line to or from a cell plate electrode in response to a control signal. The switching control unit is configured to enable the control signal at a first timing and disable the control signal at a second timing. | 03-31-2011 |
Myung Suk Lee, Ichon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110161727 | SOLID STATE STORAGE SYSTEM FOR CONTROLLING RESERVED AREA AND METHOD OF CONTROLLING THE SAME - A solid state storage system includes a flash memory region comprising a plurality of memory blocks and a plurality of replacement blocks corresponding to error-occurred blocks when errors occur in the memory blocks; and a memory controller configured to perform a control operation to replace the error-occurred blocks with the replacement blocks, wherein the error-occurred blocks comprise correctable blocks and uncorrectable blocks, and wherein the memory controller determines whether the error-occurred blocks are the correctable blocks or the uncorrectable blocks and controls zones of the replacement blocks, replaced in correspondence to the correctable blocks, to be allocated a plurality of times. | 06-30-2011 |
Tae Keun Lee, Ichon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080211111 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH UNDERFILL - An integrated circuit package system includes: providing a package carrier; forming a first channel in the package carrier; mounting a first integrated circuit device over the package carrier and adjacent to the first channel; mounting a second integrated circuit device over the package carrier and adjacent to the first channel; and forming a contiguous underfill fillet with the first channel and under both the first integrated circuit device and the second integrated circuit device. | 09-04-2008 |
| 20090174064 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SLUG - An integrated circuit package system is provided including providing a substrate having a die attached and electrically bonded thereto. The system includes forming heat slug pillars on the substrate, positioning a heat slug on the heat slug pillars, and encapsulating the substrate, the die, the heat slug pillars, and the heat slug in a mold compound. The system includes singulating the substrate, the die, the heat slug, and the mold compound. | 07-09-2009 |
| 20100038804 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOLD GATE - An integrated circuit package system includes: providing a substrate; forming a conductive layer over the substrate; forming a mold gate layer having an organic material without polymerization over the conductive layer; and attaching an integrated circuit over the substrate adjacent the mold gate layer. | 02-18-2010 |
| 20100171228 | INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes forming a substrate with a device thereover, forming an encapsulation having a planar top surface to cover the device and the substrate spanning to an extraction side of the encapsulation, and forming a recess in the encapsulation from the planar top surface. | 07-08-2010 |
| 20100176503 | SEMICONDUCTOR PACKAGE SYSTEM WITH THERMAL DIE BONDING - A semiconductor package system includes providing a substrate having a plurality of thermal vias extending through the substrate. A solder mask is positioned over the plurality of thermal vias. A plurality of thermally conductive bumps is formed on at least some of the plurality of thermal vias using the solder mask. An integrated circuit die is attached to the plurality of thermally conductive bumps. An encapsulant encapsulates the integrated circuit die. | 07-15-2010 |
| 20100327418 | INTEGRATED CIRCUIT PACKAGE SYSTEM USING HEAT SLUG - An integrated circuit package system includes a substrate having an integrated circuit die thereon; a heat slug having a tie bar, the tie bar having characteristics of singulation from an adjacent heat slug; and an encapsulant molded on the substrate, the heat slug, and the integrated circuit die includes the encapsulant which fills all of the space between the integrated circuit die and the heat slug. | 12-30-2010 |