Lee, Ichon-Shi
Chong-Won Lee, Ichon-Shi KR
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20080318570 | METHOD AND APPARATUS FOR INTERFACING AMONG MOBILE TERMINAL, BASE STATION AND CORE NETWORK IN MOBILE TELECOMMUNICATIONS SYSTEM - A method, apparatus and a computer readable record media storing instructions for executing the same method for interfacing among a hybrid type synchronous or asynchronous terminal to a core network in a next generation mobile telecommunications system. The hybrid type synchronous or asynchronous radio network determines the operating type of the core network when the core network has a connection thereto, and sends the determined core network operating type information and information related to the core network to the hybrid type synchronous or asynchronous terminal, thereby allowing the synchronous or asynchronous terminal to smoothly perform a data interfacing operation with the core network. | 12-25-2008 |
20090196222 | Method and apparatus for interfacing synchronous core network with asynchronous radio network - A method and apparatus for interfacing a synchronous core network with an asynchronous radio network in a next-generation mobile telecommunications system is disclosed. The method for mapping a message in order to interface a synchronous core network with an asynchronous radio network, the radio network having a base station (BS), the base station having a radio resource controller, a radio link controller, a medium access controller and a physical controller, the method comprising the steps of: a) selecting a function necessary to map a synchronous message to an asynchronous message; b) determining whether the synchronous message is to be transmitted to the mobile station or not; c) storing information necessary to map the synchronous message to the asynchronous message if the synchronous message is to transmitted to the mobile station, d) mapping parameters in the synchronous message to those in the asynchronous message, thereby generating the asynchronous message; e) discarding the message not to be transmitted to the mobile station after storing parameters included in the message not to be transmitted onto a predetermined device; and f) transmitting the asynchronous message to the radio resource controller. | 08-06-2009 |
20120202534 | METHOD AND APPARATUS FOR INTERFACING SYNCHRONOUS CORE NETWORK WITH ASYNCHRONOUS RADIO NETWORK - A method and apparatus for interfacing a synchronous core network with an asynchronous radio network in a next-generation mobile telecommunications system is disclosed. The method includes: a) selecting a function necessary to map a synchronous message to an asynchronous message; b) determining whether the synchronous message is to be transmitted to the mobile station or not; c) storing information necessary to map the synchronous message to the asynchronous message if the synchronous message is to transmitted to the mobile station, d) mapping parameters in the synchronous message to those in the asynchronous message, thereby generating the asynchronous message; e) discarding the message not to be transmitted to the mobile station after storing parameters included in the message not to be transmitted onto a predetermined device; and f) transmitting the asynchronous message to the radio resource controller. | 08-09-2012 |
20120329453 | METHOD AND APPARATUS FOR INTERFACING AMONG MOBILE TERMINAL, BASE STATION AND CORE NETWORK IN MOBILE TELECOMMUNICATIONS SYSTEM - A method, apparatus and a computer readable record media storing instructions for executing the same method for interfacing among a hybrid type synchronous or asynchronous terminal to a core network in a next generation mobile telecommunications system. The hybrid type synchronous or asynchronous radio network determines the operating type of the core network when the core network has a connection thereto, and sends the determined core network operating type information and information related to the core network to the hybrid type synchronous or asynchronous terminal, thereby allowing the synchronous or asynchronous terminal to smoothly perform a data interfacing operation with the core network. | 12-27-2012 |
20130225187 | METHOD AND APPARATUS FOR INTERFACING AMONG MOBILE TERMINAL, BASE STATION AND CORE NETWORK IN MOBILE TELECOMMUNICATIONS SYSTEM - A method, apparatus and a computer readable record media storing instructions for executing the same method for interfacing among a hybrid type synchronous or asynchronous terminal to a core network in a next generation mobile telecommunications system. The hybrid type synchronous or asynchronous radio network determines the operating type of the core network when the core network has a connection thereto, and sends the determined core network operating type information and information related to the core network to the hybrid type synchronous or asynchronous terminal, thereby allowing the synchronous or asynchronous terminal to smoothly perform a data interfacing operation with the core network. | 08-29-2013 |
20140313977 | METHOD AND APPARATUS FOR INTERFACING AMONG MOBILE TERMINAL, BASE STATION AND CORE NETWORK IN MOBILE TELECOMMUNICATIONS SYSTEM - A method, apparatus and a computer readable record media storing instructions for executing the same method for interfacing among a hybrid type synchronous or asynchronous terminal to a core network in a next generation mobile telecommunications system. The hybrid type synchronous or asynchronous radio network determines the operating type of the core network when the core network has a connection thereto, and sends the determined core network operating type information and information related to the core network to the hybrid type synchronous or asynchronous terminal, thereby allowing the synchronous or asynchronous terminal to smoothly perform a data interfacing operation with the core network. | 10-23-2014 |
Hyeng Ouk Lee, Ichon-Shi KR
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20120106274 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a data input enable signal generation block configured to sequentially delay a data strobe signal to generate a first delayed data strobe signal, a second delayed data strobe signal, a third delayed data strobe signal and a fourth delayed data strobe signal, and generate a data strobe enable signal in response to a CAS write signal, a CAS write latency signal and the first to fourth delayed data strobe signals, a latch control signal generation block configured to output the data strobe signal as a latch control signal during an enable period of the data strobe enable signal, and a data latch block configured to latch data in response to the latch control signal and output latched data. | 05-03-2012 |
Hye Young Lee, Ichon-Shi KR
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20110267123 | CLOCK DUTY CORRECTION CIRCUIT - A clock duty correction circuit includes a first current sourcing unit that sources a current to a current path in response to a clock signal, a first current sinking unit that sinks the current of the current path in response to the clock signal, a second current sourcing unit that sources a current to the current path in response to a delay clock signal obtained by delaying the clock signal by a predetermined time, a second current sinking unit that sinks the current of the current path in response to the delay clock signal, a current adjustment unit that adjusts an amount of the current flowing through the current path according to a voltage level of a control voltage, and a clock output unit that outputs an output clock signal having a voltage level corresponding to the amount of the current flowing through the current adjustment unit. | 11-03-2011 |
20120105122 | DUTY CYCLE CORRECTION CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A duty cycle correction circuit of a semiconductor memory apparatus includes a duty correction unit configured to determine a duty correction range in response to a duty correction range control signal, correct a duty of an inputted clock in response to duty correction codes to fall in the determined duty correction range, and generate a duty corrected clock; a duty detection unit configured to detect a duty of the duty corrected clock and output duty information; and a duty correction code generation unit configured to generate the duty correction codes based on the duty information. | 05-03-2012 |
Hyung Dong Lee, Ichon-Shi KR
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20110242869 | THREE-DIMENSIONAL STACKED SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD THEREOF - A three-dimensional stacked semiconductor integrated circuit including a plurality of stacked chips. The semiconductor integrated circuit is configured to simultaneously select the plurality of chips in response to an external command and an address, and to activate one of memory banks which are aligned on the same line in a vertical direction, among a plurality of memory banks included in the plurality of chips. | 10-06-2011 |
20120057413 | SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD THEREOF - A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal. | 03-08-2012 |
Ihl-Ho Lee, Ichon-Shi KR
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20080212389 | SDRAM with Reset Function - A synchronous dynamic random access memory (SDRAM) integrated circuit (IC) configured to receive an external Reset signal for resetting the IC includes a low voltage MOS input buffer configured to generate a buffered reset signal RST from the external Reset signal. The SDRAM IC further includes a reset circuit is configured to generate an internal reset signal Reset_En from (a) the RST signal, (b) a clock enable signal CKE which indicates a time when the SDRAM is ready to receive an external command, and (c) a mode register programming signal MRS | 09-04-2008 |
In-Chan Lee, Ichon-Shi KR
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20090102065 | BONDING PAD FOR ANTI-PEELING PROPERTY AND METHOD FOR FABRICATING THE SAME - A bonding pad includes an insulation layer with a trench, and a conductive pattern one portion of which is buried into the trench and the other portion of which is formed in a plate shape over the insulation layer. | 04-23-2009 |
Jae-Kyun Lee, Ichon-Shi KR
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20090130841 | METHOD FOR FORMING CONTACT IN SEMICONDUCTOR DEVICE - A method for forming a contact in a semiconductor device, comprises providing a substrate, forming a plurality of conductive patterns and a passivation layer surrounding the conductive patterns over the substrate, forming an insulation layer covering the conductive patterns and passivation layer, forming a mask pattern for a contact over the insulation layer, forming a first opening by performing an isotropic etch process on the insulation layer using the mask pattern as an etch mask, wherein the isotropic etch process is performed until the insulation layer meets the passivation layer, forming a barrier layer over a resultant structure of the first opening, exposing the insulation layer by performing an anisotropic etch process using the mask pattern as an etch mask, and forming a second opening exposing the substrate by performing a self aligned contact (SAC) process using the mask pattern and barrier layer as an etch mask. | 05-21-2009 |
Jeong Woo Lee, Ichon-Shi KR
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20110156034 | REPAIR CIRCUIT AND REPAIR METHOD OF SEMICONDUCTOR APPARATUS - A repair circuit of a semiconductor apparatus includes a plurality of through-silicon vias including repeated sets of one repair through-silicon via and an M number of normal through-silicon vias; a transmission unit configured to multiplex input data at a first multiplexing rate based on control signals, and transmit the multiplexed data to the plurality of through-silicon vias; a reception unit configured to multiplex signals transmitted through the plurality of through-silicon vias at a second multiplexing rate based on the control signals, and generate output data; and a control signal generation unit configured to generate sets of the control signals based on an input number of a test signal. | 06-30-2011 |
Jin-Ku Lee, Ichon-Shi KR
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20090061602 | METHOD FOR DOPING POLYSILICON AND METHOD FOR FABRICATING A DUAL POLY GATE USING THE SAME - A method for doping polysilicon improves a doping profile during plasma doping and includes forming a silicon layer using two separate operations. After forming a first silicon layer, thermal annealing is performed to crystallize the first silicon layer, such that the uniformity of a doping concentration according to the depth of a layer inside is improved during plasma doping. Additionally, a doping concentration at the interface between a polysilicon layer and a gate oxide layer is increased. A by-product deposition layer is reduced, which is formed on the surface of a polysilicon layer due to the increase of a doping concentration in a polysilicon layer. As a result, the dopant loss, which is caused by the removing and cleansing of an ion implantation barrier used during doping, is reduced. | 03-05-2009 |
Ji Wang Lee, Ichon-Shi KR
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20100090736 | DELAY LOCKED LOOP CIRCUIT AND MEMORY DEVICE HAVING THE SAME - A DLL circuit includes a multiphase clock signal generating unit configured to produce a plurality of multiphase clock signals by delaying a reference clock signal for a unit delay time and to produce an enable signal that is enabled when one of the plurality of the multiphase clock signals synchronizes with the reference clock signal at a frequency, and a multiphase clock signal selecting unit configured to delay one of the plurality of the multiphase clock signals for a predetermined time in response to a first control signal, to compare a phase of a delayed multiphase clock signal with a phase of the reference clock signal, and to output one of the plurality of the multiphase clock signals as a delayed clock signal, wherein a phase of the delayed clock signal synchronizes with the phase of the reference clock signal when the enable signal is enabled. | 04-15-2010 |
Jong-Dae Lee, Ichon-Shi KR
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20090040805 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier, wherein the device has a multi-level output current according to a voltage level of an input voltage coupled to the lower and the upper electrodes during a data read operation. | 02-12-2009 |
Joong Ho Lee, Ichon-Shi KR
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20120110398 | DATA ERROR CHECK CIRCUIT, DATA ERROR CHECK METHOD, DATA TRANSMISSION METHOD USING DATA ERROR CHECK FUNCTION, SEMICONDUCTOR MEMORY APPARATUS AND MEMORY SYSTEM USING DATA ERROR CHECK FUNCTION - Various embodiments of a memory system are disclosed. In one exemplary embodiment, the memory system may include a semiconductor memory apparatus configured to generate error check signals in a column direction and a row direction of data groups to be transmitted through a plurality of data input/output terminals in a read operation and output the error check signals together with the data groups, and a memory controller configured to control data read/write operations of the semiconductor memory apparatus, generate error check signals by performing error check in a column direction and a row direction of data groups to be transmitted in a write operation, and provide the error check signals to the semiconductor memory apparatus together with the data groups. | 05-03-2012 |
Jung Hwan Lee, Ichon-Shi KR
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20120106273 | SEMICONDUCTOR MEMORY APPARATUS - Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus may include: a column control signal generator configured to generate a column control signal for a pair of bit lines corresponding to a data mask during a data mask operation; and a bit line sense amplifier configured to sense and amplify a voltage difference between the pair of bit lines and electrically couple the pair of bit lines to a pair of segment input/output lines in response to the column control signal. | 05-03-2012 |
Jung-Seock Lee, Ichon-Shi KR
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20080242042 | METHOD FOR FABRICATING A CAPACITOR IN A SEMICONDUCTOR DEVICE - A method for fabricating a capacitor in a semiconductor device includes forming a sacrificial layer and a support layer on a substrate. A plurality of openings are formed by etching the support layer and the sacrificial layer. An electrode is formed in inner walls of the openings including sidewalls of the support layer patterned through etching. A portion of the patterned support layer is removed, and the sacrificial layer is also removed. | 10-02-2008 |
Kang-Seol Lee, Ichon-Shi KR
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20100073078 | INTERNAL VOLTAGE GENERATING CIRCUIT - There is an internal voltage generating circuit for providing a stable high voltage by making a response time short. The internal voltage generating circuit includes a charge pump unit for generate a high voltage being higher than an external voltage in response to pumping control signals and a supply driving control signal; a pumping control signal generating unit for outputting the pumping control signals to the charge pump unit based on a driving signal; and a supply driving control unit for receiving the driving signal to generate the supply driving control signal to the charge pump unit. | 03-25-2010 |
20110291639 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes an internal reference voltage generation unit configured to generate an internal reference voltage; a high voltage generation unit configured to pump an external driving voltage based on the internal reference voltage applied from the internal reference voltage generation unit, and generate a high voltage having a specified level; and a reference voltage transfer unit configured to generate a test reference voltage from a reference voltage in a package test mode to correspond to a change in a driving operation of the external driving voltage applied from outside, and monitor and force the internal reference voltage. | 12-01-2011 |
20120195137 | SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD THEREOF - A semiconductor integrated circuit includes a first chip and a second chip stacked together with the first chip. A first memory area is formed on the second chip, and a second memory area for repairing a failure of the first memory area is formed on the first chip. | 08-02-2012 |
20120243355 | SEMICONDUCTOR APPARATUS - Various embodiments of a semiconductor apparatus are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a memory block chip and a signal input/output chip. The memory block chip is configured to control a data access size according to specifications. The signal input/output chip is configured to transmit input data from an external device to the memory block chip or transmit output data from the memory block chip to an external device and process the input data or the output data by selectively enabling a clock phase control unit and a signal processing unit according to the specifications. | 09-27-2012 |
Kang Youl Lee, Ichon-Shi KR
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20110271157 | TEST CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A test circuit of a semiconductor memory apparatus includes: a first fail detection unit configured to detect a fail of a memory cell group of a first memory block by combining a plurality of first test data signals outputted from the memory cell group of the first memory block; a second fail detection unit configured to detect a fail of a memory cell group of a second memory block by combining a plurality of second test data signals outputted from the memory cell group of the second memory block; a common fail detection unit configured to detect a fail of the memory cell groups of the first and second memory blocks by combining the plurality of first test data signals and the plurality of second test data signals; and a fail determination unit configured to output detection results of the first and second fail detection units or a detection result of the common is fail detection unit according to the detection results of the first and second fail detection units. | 11-03-2011 |
20120155199 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus may include a bonding pad; a control signal pad; and an operation mode signal generation unit configured to generate a plurality of operation mode signals in response to a bonding signal inputted through the bonding pad and a control signal inputted through the control signal pad. | 06-21-2012 |
Ki Hoon Lee, Ichon-Shi KR
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20110241764 | REDUNDANCY CIRCUITS - In one embodiment, a redundancy circuit may include a comparison unit configured to record a first repair address through fuse cutting, compare a comparison address with the first repair address, and output a comparison result signal; a first fuse enable unit configured to output a first fuse enable signal for repairing the first repair address; a second fuse enable unit configured to output a second fuse enable signal for repairing a second repair address; a first determination unit configured to output a first repair determination signal in response to receipt of the first fuse enable signal and the comparison result signal; and a second determination unit configured to output a second repair determination signal in response to receipt of an inverted signal of a value of the comparison result signal corresponding to the certain bit, remaining bits, and the second fuse enable signal. | 10-06-2011 |
Ki-Lyoung Lee, Ichon-Shi KR
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20090068838 | METHOD FOR FORMING MICROPATTERNS IN SEMICONDUCTOR DEVICE - A method for forming micropatterns in a semiconductor device includes forming a first etch stop layer over a etch target layer, forming a second etch stop layer over the first etch stop layer, forming a first sacrificial layer over the second etch stop layer, etching portions of the first sacrificial layer and second etch stop layer to form first sacrificial patterns, forming an insulation layer along an upper surface of the first etch stop layer, forming a second sacrificial layer over the insulation layer to cover the insulation layer, planarizing the second sacrificial layer and the insulation layer to expose the first sacrificial patterns, removing the first sacrificial patterns and the second sacrificial layer, etching the second etch stop layer and insulation layer to thereby form second sacrificial patterns, etching the first etch stop layer, and etching the etch target layer. | 03-12-2009 |
Min-Yong Lee, Ichon-Shi KR
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20110039403 | Method for Implanting Ions In Semiconductor Device - The present invention provides various methods for implanting ions in a semiconductor device that substantially compensate for a difference in threshold voltages between a central portion and edge portions of a substrate generated while performing uniform ion implantation to entire surfaces of a substrate. Other methods for fabricating a semiconductor device improve distribution of transistor parameters across a substrate by forming a nonuniform channel doping layer or by forming a nonuniform junction profile, across the substrate. | 02-17-2011 |
Moon-Keun Lee, Ichon-Shi KR
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20090146306 | Semiconductor device with epitaxial C49-titanium silicide (TiSi2) layer and method for fabricating the same - The present invention relates to a semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. This titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of agglomeration of the titanium layer and a grooving phenomenon can be prevented. The semiconductor device includes: a silicon layer; an insulation layer formed on the silicon layer, wherein a partial portion of the insulation layer is opened to form a contact hole exposing a partial portion of the silicon layer; an epitaxially grown titanium silicide layer having a phase of C49 and formed on the exposed silicon substrate disposed within the contact hole; and a metal layer formed on an upper surface of the titanium silicide layer. | 06-11-2009 |
Sang-Don Lee, Ichon-Shi KR
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20110198701 | Transistor of Volatile Memory Device with Gate Dielectric Structure Capable of Trapping Charges and Method for Fabricating the Same - The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate. | 08-18-2011 |
Sang-Oh Lee, Ichon-Shi KR
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20090061615 | METHOD FOR FORMING CONTACT IN SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes providing a substrate, forming an insulation layer over the substrate, forming a photoresist pattern for a contact hole over the insulation layer, wherein the photoresist pattern includes an opening having a critical dimension (CD) greater than a desired contact CD, forming a contact hole by selectively etching the insulation layer using the photoresist pattern, and forming a spacer on a sidewall of the contact hole until a CD of the contact hole whose sidewall is covered by the spacer is reduced to a desired contact CD. | 03-05-2009 |
Seung-Cheol Lee, Ichon-Shi KR
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20090008698 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAM - A nonvolatile memory device includes an active region which is defined by an isolation layer formed in a substrate and has a recess therein in a channel width direction, wherein an upper portion of the active region having the recess projects over an upper portion of the isolation layer, a lower insulation layer formed along a surface of the active region and a top surface of the isolation layer, a charge storage layer formed over the lower insulation layer, an upper insulation layer formed over the charge storage layer, and a gate electrode formed over the upper insulation layer. | 01-08-2009 |
Seung-Ryong Lee, Ichon-Shi KR
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20090111256 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a pattern including a first layer including tungsten, performing a gas flowing process on the pattern in a gas ambience including nitrogen, and forming a second layer over the pattern using a source gas including nitrogen, wherein the purge is performed at a given temperature for a given period of time in a manner that a reaction between the first layer and the nitrogen used when forming the second layer is controlled. | 04-30-2009 |
20100012998 | FLASH MEMORY DEVICE WITH STACKED DIELECTRIC STRUCTURE INCLUDING ZIRCONIUM OXIDE AND METHOD FOR FABRICATING THE SAME - A dielectric structure disposed between a floating gate and a control gate of a flash memory device includes: a first dielectric layer; a third dielectric layer having a k-dielectric constant substantially the same as that of the first dielectric layer; and a second dielectric layer disposed between the first dielectric layer and the third dielectric layer, having a greater k-dielectric constant than that of the first and third dielectric layers and formed by alternately and repeatedly stacking a plurality of aluminum oxide (Al | 01-21-2010 |
20110068380 | SEMICONDUCTOR DEVICE WITH BULB-TYPE RECESSED CHANNEL AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers. | 03-24-2011 |
Sung-Kwon Lee, Ichon-Shi KR
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20080293212 | METHOD FOR FORMING STORAGE NODE OF CAPACITOR IN SEMICONDUCTOR DEVICE - A method for forming a capacitor in a semiconductor device comprises forming an inter-layer layer on a semi-finished substrate; etching the inter-layer insulation layer to form a plurality of first contact holes; forming a first insulation layer on sidewalls of the first contact holes; forming a plurality of storage-node contact plugs filled into the first contact holes; forming a second insulation layer with a different etch rate from the first insulation layer over the storage-node contact plugs; forming a third insulation layer on the second insulation layer; sequentially etching the third insulation layer and the second insulation layer to form a plurality of second contact holes exposing the storage-node contact plugs; and forming the storage node on each of the second contact holes. | 11-27-2008 |
20090117492 | METHOD FOR FORMING FINE PATTERN IN SEMICONDUCTOR DEVICE - A method is used in forming a fine pattern in a semiconductor device. The method includes forming an etch target layer; forming a photoresist pattern over the etch target layer; forming a polymer pattern including silicon-oxygen (Si—O) bonds on sidewalls of the photoresist pattern; removing the photoresist pattern; and etching the etch target layer using the polymer pattern as an etch mask. | 05-07-2009 |
Tae-Kwon Lee, Ichon-Shi KR
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20090111256 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a pattern including a first layer including tungsten, performing a gas flowing process on the pattern in a gas ambience including nitrogen, and forming a second layer over the pattern using a source gas including nitrogen, wherein the purge is performed at a given temperature for a given period of time in a manner that a reaction between the first layer and the nitrogen used when forming the second layer is controlled. | 04-30-2009 |
20090146306 | Semiconductor device with epitaxial C49-titanium silicide (TiSi2) layer and method for fabricating the same - The present invention relates to a semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. This titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of agglomeration of the titanium layer and a grooving phenomenon can be prevented. The semiconductor device includes: a silicon layer; an insulation layer formed on the silicon layer, wherein a partial portion of the insulation layer is opened to form a contact hole exposing a partial portion of the silicon layer; an epitaxially grown titanium silicide layer having a phase of C49 and formed on the exposed silicon substrate disposed within the contact hole; and a metal layer formed on an upper surface of the titanium silicide layer. | 06-11-2009 |
Tae Yong Lee, Ichon-Shi KR
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20120012844 | SEMICONDUCTOR MEMORY APPARATUS FOR CONTROLLING PADS AND MULTI-CHIP PACKAGE HAVING THE SAME - A semiconductor memory apparatus includes a first pad group located along a first edge of a plurality of banks, a second pad group located along a second edge of the plurality of banks opposite the first pad group, and a pad control section configured to provide first and second bonding signals and to implement control operation in response to a test mode signal and a bonding option signal to selectively employ signals from the first and second pad groups. | 01-19-2012 |
Tae Young Lee, Ichon-Shi KR
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20100034005 | SEMICONDUCTOR MEMORY APPARATUS FOR CONTROLLING PADS AND MULTI-CHIP PACKAGE HAVING THE SAME - A semiconductor memory apparatus includes a first pad group located along a first edge of a plurality of banks, a second pad group located along a second edge of the plurality of banks opposite the first pad group, and a pad control section configured to provide first and second bonding signals and to implement control operation in response to a test mode signal and a bonding option signal to selectively employ signals from the first and second pad groups. | 02-11-2010 |
Yoon-Jik Lee, Ichon-Shi KR
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20090146306 | Semiconductor device with epitaxial C49-titanium silicide (TiSi2) layer and method for fabricating the same - The present invention relates to a semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. This titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of agglomeration of the titanium layer and a grooving phenomenon can be prevented. The semiconductor device includes: a silicon layer; an insulation layer formed on the silicon layer, wherein a partial portion of the insulation layer is opened to form a contact hole exposing a partial portion of the silicon layer; an epitaxially grown titanium silicide layer having a phase of C49 and formed on the exposed silicon substrate disposed within the contact hole; and a metal layer formed on an upper surface of the titanium silicide layer. | 06-11-2009 |