Lee, Icheon-Si Gyeonggi-Do
Byeong Cheol Lee, Icheon-Si Gyeonggi-Do KR
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20150155018 | CONTROL CIRCUIT FOR BIT-LINE SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME, AND OPERATING METHOD THEREOF - A control circuit for a bit-line sense amplifier may include: a bank active signal generator configured to generate an internal active signal and a bank active signal; and a sense amplifier enable signal generator configured to determine a skew in response to the internal active signal, and set an output time of a sense amplifier enable signal by delaying the bank active signal according to the determined skew. | 06-04-2015 |
Chang Hyun Lee, Icheon-Si Gyeonggi-Do KR
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20150332787 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a plurality of data storage regions; a first internal circuit configured to input a plurality of control signals to the plurality of data storage regions; and a second internal circuit configured to control input timing of a test control signal, and input the test control signal to the plurality of data storage regions according to the controlled input timing in response to a test mode signal. | 11-19-2015 |
20160069959 | SEMICONDUCTOR APPARATUS AND TEST DEVICE THEREFOR - A semiconductor apparatus includes a clock enable signal buffer unit configured to receive an input clock enable signal, and generate an output clock enable signal; a buffer control unit configured to generate a buffer enable signal in response to the output clock enable signal and a test enable signal; an input/output buffer unit configured to receive input patterns and generate output patterns; and a compression test unit configured to test the output patterns and the output clock enable signal according to the test enable signal. | 03-10-2016 |
Eun Ryeong Lee, Icheon-Si Gyeonggi-Do KR
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20130114350 | SEMICONDUCTOR MEMORY DEVICE INCLUDING INITIALIZATION SIGNAL GENERATION CIRCUIT - An initialization signal generation circuit includes: an initialization signal output unit configured to generate an initialization signal which is enabled during at least a portion of an auto refresh operation period of the initialization mode, in response to a flag signal; a refresh signal generation unit configured to generate a preliminary refresh signal and a refresh counting signal having the same period as the auto refresh signal in response to the flag signal and an auto refresh signal; and a counter unit configured to count a counting signal in response to the refresh counting signal and generate a counting initialization signal, which is delayed by at least a pulse width of the refresh counting signal, after a time point where a combination of the counting signal becomes a preset combination. | 05-09-2013 |
Hyun Bae Lee, Icheon-Si Gyeonggi-Do KR
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20150121018 | SEMICONDUCTOR MEMORY SYSTEM AND VOLTAGE SETTING METHOD - A semiconductor memory system includes a memory controller and memory apparatus. The memory controller provides a first data having a first level and a second data having a second level. The memory apparatus adjusts a level of a reference voltage by comparing the reference voltage with each of the first data and the second data. | 04-30-2015 |
Hyung Dong Lee, Icheon-Si Gyeonggi-Do KR
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20120213022 | SIP SEMICONDUCTOR SYSTEM - A system in package (SIP) semiconductor system includes a memory device, a controller, a first input/output terminal, a test control unit, and a second input/output terminal. The controller communicates with the memory device. The first input/output terminal performs communication between the controller and a device external to the SIP semiconductor system. The test control unit controls a predetermined test mode of the memory device. The second input/output terminal performs communication between the test control unit and at least the device external to the SIP semiconductor system. | 08-23-2012 |
20140143508 | MEMORY SYSTEM AND OPERATING METHOD THEREOF - A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory dies having different page sizes. The memory controller generates a plurality of chip selection signals for activating the plurality of memory dies based on the reordering number of requests received from a processor. | 05-22-2014 |
Hyun Gyu Lee, Icheon-Si Gyeonggi-Do KR
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20150124540 | SEMICONDUCTOR INTEGRATED CIRCUIT - A system including a circuit integrated with a semiconductor is provided. The system includes a first data line, a second data line, and a first sense amp configured to sense and amplify data of the first data line. The first sense amp is also configured to transfer the amplified data to the second data line in response to a third control signal. The system also includes a control signal generation circuit configured to generate a first control signal for controlling a precharge of the first data line and a second control signal for controlling a reset of the second data line in response to a preparatory signal and a third control signal. The third control signal is generated in response to the first control signal and the second control signal. | 05-07-2015 |
Hyun Ho Lee, Icheon-Si Gyeonggi-Do KR
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20160071869 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor memory device includes a stacked structure including conductive patterns and interlayer insulating patterns which are alternately stacked, a through-hole configured to pass through the stacked structure; a channel pattern formed inside the through-hole, a first capping conductive pattern formed on the channel pattern, a second capping conductive pattern formed on a sidewall of the first capping conductive pattern and surrounding the first capping conductive pattern, and a contact plug formed on the first capping conductive pattern and the second capping conductive pattern. | 03-10-2016 |
Hyun Sung Lee, Icheon-Si Gyeonggi-Do KR
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20150155020 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a logic memory chip including a transmission block which outputs input signals and a strobe signal; and a plurality of memory chips stacked with the logic memory chip. At least one of the plurality of memory chips includes a plurality of reception blocks. Each of the plurality of reception blocks receives an input signal among the input signals and the strobe signal, and controls a phase of any one of the input signal and the strobe signal. | 06-04-2015 |
Kang Seol Lee, Icheon-Si Gyeonggi-Do KR
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20140133256 | VOLTAGE GENERATION CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal. | 05-15-2014 |
20140353664 | SEMICONDUCTOR CHIP, SEMICONDUCTOR APPARATUS HAVING THE SAME AND METHOD OF ARRANGING THE SAME - Provided is a semiconductor apparatus in which a plurality of semiconductor chips stacked in a vertical direction. Each of the semiconductor chips comprises: a bank area comprising a plurality of banks configured to store data; and a peripheral area including a pad area in which a plurality of pads configured to receive signals for controlling the bank area and a plurality of TSV for electrically connecting the plurality of pads, respectively. | 12-04-2014 |
Nam Jae Lee, Icheon-Si Gyeonggi-Do KR
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20160027730 | INTERCONNECTION STRUCTURE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - An interconnection structure may include insulating layers stacked stepwise and dielectric layers interposed between the insulating layers. The interconnection structure may include conductive layers interposed between the insulating layers and surrounding sidewalls of the dielectric layers, respectively. The interconnection structure may include contact plugs each coupled to one of the conductive layers. The contact plugs may at least partially pass through the dielectric layers. | 01-28-2016 |
Sang Don Lee, Icheon-Si Gyeonggi-Do KR
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20150153794 | SYSTEM INCLUDING MEMORY CONTROLLER FOR MANAGING POWER OF MEMORY - A system includes a power supply, a memory controller and a memory device. The memory controller is configured to receive power from the power supply, generate a memory power supply voltage for use by the memory device based on the power received from the power supply and provide the memory power supply voltage to the memory device. | 06-04-2015 |
Seung Cheol Lee, Icheon-Si Gyeonggi-Do KR
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20150340373 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming isolation layers in a first direction at trenches at isolation regions defined at a semiconductor substrate and forming gate lines in a second direction crossing the first direction over the isolation layers and active regions defined between the isolation layers, performing a dry-etch process to remove the isolation layers, and forming an insulating layer over the semiconductor substrate to form a first air gap extending in the first direction in the trenches and a second air gap extending in the second direction between the gate lines. | 11-26-2015 |
Woo Young Lee, Icheon-Si Gyeonggi-Do KR
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20150124543 | SEMICONDUCTOR DEVICES - Semiconductor devices are provided. The semiconductor device includes a first pre-charge element and a second pre-charge element. The first pre-charge element receives a first pre-charge signal to pre-charge a first bit line to have a first pre-charge voltage signal. The second pre-charge element receives a second pre-charge signal to pre-charge a second bit line to have a second pre-charge voltage signal. The second pre-charge signal is enabled earlier than the first pre-charge signal in the event that a data stored in a memory cell of a first cell block is loaded on the first bit line. | 05-07-2015 |