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Lee, Austin
Byoung H. Lee, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080251814 | HETERO-BONDED SEMICONDUCTOR-ON-INSULATOR SUBSTRATE WITH AN UNPINNING DIELECTRIC LAYER - A hetero-bonded SOI substrate comprises a stack of a semiconductor handle substrate, an isolation insulator layer, a depinning dielectric layer, and a top non-silicon semiconductor layer. The depinning layer abuts both the top non-silicon semiconductor layer and the isolation insulator layer and relaxes Fermi level pinning in the top non-silicon semiconductor layer. The top non-silicon semiconductor layer may be a III-V compound semiconductor layer such as GaAs and the depinning dielectric layer may be a (Gd | 10-16-2008 |
| 20090294867 | DUAL METAL GATES USING ONE METAL TO ALTER WORK FUNCTION OF ANOTHER METAL - Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process. | 12-03-2009 |
Byoung Hun Lee, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090039441 | MOSFET WITH METAL GATE ELECTRODE - Devices comprising, and method for fabricating, a MOSFET with a metal gate electrode are disclosed. In one embodiment, the MOSFET includes a first doped region configured to receive current from a current source, a second doped region configured to drain current from the first doped region when an electric field is modified between the first doped region and the second doped region, and a gate electrode configured to modify the electric field. The gate electrode may include a high-k layer, a hafnium-based metal layer formed above the high-k layer, and a polysilicon layer formed above the hafnium-based metal layer. In a further embodiment, the gate electrode further comprises a titanium-based metal layer formed between the hafnium-based metal layer and the polysilicon layer. | 02-12-2009 |
Chung Lee, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090102489 | Systems and methods for detecting electric discharge - A distributed sensing system for detecting partial electric discharge along the length of an extended object or objects. An optical fiber having a cladding integrated with luminescent material and a silica core of less than 500 micro-meters in diameter with a first reflective end deployed in proximity to test objects. A photo detector is positioned at the second end of the optical sensing fiber and receives and measures both a direct emission light from an electric partial discharge event and the reflected emission light from the reflection end of the optical sensing fiber. The measured signals and their arrival times are used to determine the location and magnitude of a partial electrical discharge. | 04-23-2009 |
| 20100103978 | PURE SILICA CORE MULTIMODE FIBER SENSOES FOR DTS APPICATIONS - A new step-index multimode pure silica core fiber for DTS (Distributed Temperature Sensing) system particularly useful for downhole environments is disclosed and described. The new sensor system provides optimum tradeoffs between coupling power, spatial resolution, and temperature resolution. | 04-29-2010 |
| 20100128756 | DUAL SOURCE AUTO-CORRECTION IN DISTRIBUTED TEMPERATURE SYSTEMS - An automatic and continuous method is presented to improve the accuracy of fiber optic distributed temperature measurements derived from Raman back scatterings utilizing two light sources with different wavelengths, by choosing the wavelengths of the two sources so the primary source's return anti-Stokes component overlaps with the incident wavelength of the secondary light source thereby canceling out the non-identical attenuations generated by the wavelength differences between Stokes and anti-Stokes bands. | 05-27-2010 |
Di-Hong Lee, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080237717 | Fully Depleted SOI Multiple Threshold Voltage Application - An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric. | 10-02-2008 |
Eric Lee, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090075491 | Method for curing a dielectric film - A method of curing a low dielectric constant (low-k) dielectric film on a substrate is described, wherein the dielectric constant of the low-k dielectric film is less than a value of approximately 4. The method comprises exposing the low-k dielectric film to ultraviolet (UV) radiation. Following the UV exposure, the dielectric film is exposed to IR radiation. | 03-19-2009 |
Erik Lee, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100264740 | BATTERY SYSTEMS AND OPERATIONAL METHODS - This disclosure includes battery systems and operational methods. According to one aspect, a battery system includes conversion circuitry, a plurality of main terminals configured to be coupled with a load, a charger and a plurality of rechargeable battery modules which are coupled in series with one another intermediate the main terminals, switching circuitry configured to couple a first of the battery modules with an input of the conversion circuitry, and the conversion circuitry being configured to modify an electrical characteristic of electrical energy received from the first of the battery modules and to output the electrical energy having the modified characteristic to a second of the battery modules. | 10-21-2010 |
Hoojin Lee, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090327835 | Techniques for Reducing Joint Detection Complexity in a Channel-Coded Multiple-Input Multiple-Output Communication System - A technique for joint detection of channel-coded signals in a multiple-input multiple-output system includes detecting, when a decoded signal associated with a first symbol stream passes a cyclic redundancy check, channel-coded signals in the first symbol stream and a second symbol stream using minimum mean squared error with ordered successive interference cancellation (MMSE-OSIC) based detection. When the decoded signal associated with the first symbol stream fails the cyclic redundancy check, the channel-coded signals in the first and second symbol streams are detected using neighbor search algorithm (NSA) based detection. | 12-31-2009 |
| 20100208833 | Techniques for Transmitting Data in a Wireless Communication System Using Quasi-Orthogonal Space-Time Code - A technique for communicating in a wireless communication system includes creating, using two distinct Alamouti codes, a power-scaled quasi-orthogonal space-time block code. The technique further includes transmitting, using a transmitter, the power-scaled quasi-orthogonal space-time block code over multiple antennas (e.g., three or four transmit antennas). | 08-19-2010 |
Hyung Joo Lee, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090242513 | Multi-Layer/Multi-Input/Multi-Output (MLMIMO) Models and Method for Using - The invention provides a method of processing a substrate using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more masking layer creation procedures, one or more pre-processing measurement procedures, one or more Partial-Etch (P-E) procedures, one or more Final-Etch (F-E) procedures, and one or more post-processing measurement procedures. | 10-01-2009 |
| 20100036514 | Creating Multi-Layer/Multi-Input/Multi-Output (MLMIMO) Models for Metal-Gate Structures - The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes. | 02-11-2010 |
| 20100036518 | Using Multi-Layer/Multi-Input/Multi-Output (MLMIMO) Models for Metal-Gate Structures - The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes. | 02-11-2010 |
Jessie T. Lee, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100142700 | System for Translation and Communication of Messaging Protocols into a Common Protocol - An adapter for passing messages in a telecommunications infrastructure from a first device to a second device. The adapter comprises a messaging interface, a processor, and a bus interface. The messaging interface is in communication with the first device and is operable to receive a received message in a first messaging format from the first device. The processor is coupled to the messaging interface and is operable to receive the received message from the messaging interface and translate the received message into a common message in a common format. The bus interface is coupled to the processor and is operable to receive the common message from the processor and transmit the common message to the second device through a bus. | 06-10-2010 |
Michael J. H. Lee, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100302895 | ENHANCED PROGRAMMABLE PULSEWIDTH MODULATING CIRCUIT FOR ARRAY CLOCK GENERATION - A pulsewidth modulation circuit uses a plurality of programmable paths to connect its output line to ground connections. The paths have different numbers of serially-connected NFETs to provide different pulldown rates. A desired programmable paths is selected based on encoded control signals, with decode logic integrated into the programmable paths. The decode logic includes, for each path, at least two transistors controlled by one of the encoded signals or their complements. A default path to ground may also be provided for use when none of the programmable paths is selected. For example, two encoded signals may be used to select 1-in-4 among the default path and three programmable paths. Integration of the decode logic into the programmable paths results in smaller overall circuit area, leading to reduced power usage, while still retaining the orthogonal benefit of encoded control signals. | 12-02-2010 |
Michael Ju Hyeok Lee, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080270963 | SYSTEM AND COMPUTER PROGRAM FOR VERIFYING PERFORMANCE OF AN ARRAY BY SIMULATING OPERATION OF EDGE CELLS IN A FULL ARRAY MODEL - A system and computer program for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge “outlier” cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers. | 10-30-2008 |
| 20100002525 | Array Data Input Latch and Data Clocking Scheme - A data input latch and clocking method and apparatus for high performance SRAM in which an L1 data input latch is controlled by a logical combination of the normal local clock buffer clock signal and the local array clock buffer clock signal. This logical combination of clock signals minimizes the hold time of the L1 latch provides a fast cycle time in which the SRAM macro can process successive write instructions while avoiding early mode issues. | 01-07-2010 |
| 20100027361 | Information Handling System with SRAM Precharge Power Conservation - An information handling system (IHS) includes a processor with on-chip or off-chip SRAM array. After a read operation, a control circuit may instruct the SRAM array to conduct a precharge operation, or alternatively, instruct the SRAM array to conduct an equalize bitline voltage operation. A read operation may follow the precharge operation or the equalize bitline voltage operation. The control circuit may instruct the SRAM array to conduct an equalize bitline voltage operation if an equalized voltage of a bitline pair exhibits more that a predetermined amount of voltage. Otherwise, the control circuit instructs the SRAM array to conduct a precharge operation before the next read operation. | 02-04-2010 |
| 20100164586 | PROGAMABLE CONTROL CLOCK CIRCUIT FOR ARRAYS - A programmable clock control circuit includes a base block, a chop block, and a pulse width variation block coupled between the chop block and the base block that receives the chop block output and provides a pulse width variation output to the base block. The pulse width variation block is programmable to vary the chop block output to provide at least three different output pulse widths. The circuit also includes a clock delay block coupled an output of the base block to delay the output pulse and having a clock signal output. | 07-01-2010 |
Robert E. Lee, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110029681 | WEB CLIENT DATA CONVERSION FOR SYNTHETIC ENVIRONMENT INTERACTION - Web client data conversion for synthetic environment interaction is described, including receiving a message at a synthetic environment server indicating occurrence of an event on a web client by a web application server configured to generate a transformed message from a first protocol format to a second protocol format, sending the transformed message from the web application server to a message bus using the second protocol format, translating the transformed message into a translated message, the transformed message being translated from the second protocol to a third protocol using a property class, sending the translated message from the message bus to the synthetic environment server according to the property class, and updating the synthetic environment using data included in the translated message, wherein the synthetic environment is updated in substantially real-time. In some embodiments, a method can include an implementing an application programming interface associated with a transactional server. | 02-03-2011 |
Sang Hyun Lee, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100177839 | METHOD OF DIRTY PAPER CODING USING NESTED LATTICE CODES - A method of Dirty Paper Coding DPC using nested lattices is disclosed. The complexity of DPC can be reduced by scaling nested lattices and mapping interference to a lattice point of the scaled lattice. | 07-15-2010 |
Seung-Wuk Lee, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080206838 | Nanoscaling ordering of hybrid materials using genetically engineered mesoscale virus - The present invention includes methods for producing nanocrystals of semiconductor material that have specific crystallographic features such as phase and alignment by using a self-assembling biological molecule that has been modified to possess an amino acid oligomer that is capable of specific binding to semi-conductor material. One form of the present invention is a method to construct ordered nanoparticles within the liquid crystal of the self-assembling biological molecule. | 08-28-2008 |
Siew-Yee Lee, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090287592 | SYSTEM AND METHOD FOR CONFERRING A BENEFIT TO A THRID PARTY FROM THE SALE OF LEADS - A computer system and method for operating a computer system to confer a benefit to a third party recipient from the sale of leads. Receiving a lead entry from the lead contributor, the lead entry having a lead description describing a desired good or service. Transmitting an alert of the lead to potential providers inviting the potential providers to buy a share in the lead. Upon receiving a lead purchase request from the requesting potential provider including a payment for the lead, processing the lead purchase request including crediting an account of a third party recipient with a portion of the payment. | 11-19-2009 |
Susan Elise Lee, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100057644 | INTERACTIVE DIGITAL VIDEO LIBRARY - A system for increasing user interaction with a digital video library. In response to receiving a question by an interactive digital video library server from a user regarding course material being presented from a digital video library, it is determined whether the question is in an audio format. In response to determining that the question is in an audio format, the question is converted into a text format. The course material is searched in a time sliced video index database for an answer to the question using keywords found in the text format of the question. Also, other course materials similar to the course material are searched in a video knowledge base. A weight is assigned to each search result hit found in the course material and the other course materials. Search result hits are outputted in a priority order according to assigned weight and user preference. | 03-04-2010 |
Thomas H. Lee, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080205122 | MRAM MEMORY CONDITIONING - According to an example embodiment, a method (500) includes applying a magnetic field to an array of Magnetic Tunnel Junction (MTJ) bits, a magnitude of the magnetic field sufficient to eliminate a stuck-at-mid condition exhibited by one of the MTJ bits without causing other ones of the MTJ bits to develop the stuck-at-mid condition. | 08-28-2008 |
Wai L. Lee, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080272842 | Calibrated feedback - A differential feedback amplifier is provided with a feedback network wherein that feedback network is adjustable so as to improve the PSRR of the amplifier. In another aspect of the present invention, a differential feedback amplifier is provided with a feedback network wherein that feedback network is adjustable so as to improve the CMRR of the amplifier. In a further aspect of the present invention, a Class D amplifier is provided with a passive differential feedback, summing with an input current at a differential virtual ground produced by an amplifier which is a sub-section of the Class D amplifier. | 11-06-2008 |
Yofay Kari Lee, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080243819 | SEARCH MACRO SUGGESTIONS RELEVANT TO SEARCH QUERIES - Search macros suggestions are provided to refine a user's search. When a search query is received from an end user, one or more search macros are determined to be relevant to the search query. The search macros are then provided to the end user as suggestions for refining the user's search. In some instances, the end user may chose to select one of the suggested search macros. A search is then performed using the search query and the selected search macro to provide search results to the end user that may be more relevant to the user's search. | 10-02-2008 |
| 20100161583 | SEARCH MACRO SUGGESTIONS RELEVANT TO SEARCH QUERIES - Search macros suggestions are provided to refine a user's search. When a search query is received from an end user, one or more search macros are determined to be relevant to the search query. The search macros are then provided to the end user as suggestions for refining the user's search. In some instances, the end user may chose to select one of the suggested search macros. A search is then performed using the search query and the selected search macro to provide search results to the end user that may be more relevant to the user's search. | 06-24-2010 |