Patent application number | Description | Published |
20100268987 | Circuits And Methods For Processors With Multiple Redundancy Techniques For Mitigating Radiation Errors - Embodiments of circuits for processors with multiple redundancy techniques for mitigating radiation errors are described herein. Other embodiments and related methods and examples are also described herein. | 10-21-2010 |
20100269018 | Method for preventing IP address cheating in dynamica address allocation - Embodiments of circuits and methods for circuits for the detection of soft errors in cache memories are described herein. Other embodiments and related methods and examples are also described herein. | 10-21-2010 |
20100269022 | Circuits And Methods For Dual Redundant Register Files With Error Detection And Correction Mechanisms - Embodiments of circuits and method for dual redundant register files with error detection and correction mechanisms are described herein. Other embodiments and related examples are also described herein. | 10-21-2010 |
20110261634 | Differential Threshold Voltage Non-Volatile Memory and Related Methods - Embodiments and examples of differential threshold voltage non-volatile memories and related methods are described herein. Other embodiments, examples thereof, and related methods are also disclosed herein. | 10-27-2011 |
20110261635 | Differential Threshold Voltage Non-Volatile Memory and Related Methods - Embodiments and examples of differential threshold voltage non-volatile memories and related methods are described herein. Other embodiments, examples thereof, and related methods are also disclosed herein. | 10-27-2011 |
20120063189 | LONGEST PREFIX MATCH INTERNET PROTOCOL CONTENT ADDRESSABLE MEMORIES AND RELATED METHODS - Embodiments of content addressable memories for internet protocol devices and operations are described herein. Other examples and related methods are also disclosed herein. | 03-15-2012 |
20120070158 | FLEXIBLE IDENTIFICATION SYSTEMS AND RELATED METHODS - Embodiments of flexible identification systems are described herein. Other embodiments and related methods are also disclosed herein. | 03-22-2012 |
20120140929 | INTEGRATED CIRCUITS SECURE FROM INVASION AND METHODS OF MANUFACTURING THE SAME - An integrated circuit device that is secure from invasion and related methods are disclosed herein. Other embodiments are also disclosed herein. | 06-07-2012 |
20120230087 | SRAM CIRCUITS FOR CIRCUIT IDENTIFICATION USING A DIGITAL FINGERPRINT - Circuitry that includes static random access memory (SRAM) access circuitry and a group of SRAM memory cells is disclosed. A digital fingerprint of the group of SRAM memory cells is determined by using the SRAM access circuitry to force at least a portion of the group of SRAM memory cells into a metastable state and then releasing the portion of the SRAM memory cells. Each SRAM memory cell that was released then selects one of two stable states and the SRAM access circuitry provides a selection profile based on the selections. The digital fingerprint is based on the selection profile. | 09-13-2012 |
20120242409 | ANALOG CIRCUITS HAVING IMPROVED TRANSISTORS, AND METHODS THEREFOR - Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. | 09-27-2012 |
20120278593 | LOW COMPLEXITY OUT-OF-ORDER ISSUE LOGIC USING STATIC CIRCUITS - Instruction issue circuits are disclosed that are configured to issue multiple instructions within a superscalar pipeline of a microprocessor. The instruction issue circuit includes an instruction queue that stores instructions. A ready generation circuit is operably associated with the instruction queue and generates ready signals that indicate which instructions in the instruction queue are ready for execution. To simplify the instruction issue circuit, the instruction issue circuit has group blocks. Each group block receives a different group of the ready signals corresponding to a different group of the instructions. Each group block generates a group output indicating a group set within the corresponding group of the instructions that has a highest instruction execution priority and are ready for execution. By splitting the ready signals into groups, the groups of ready signals can be processed in parallel thereby reducing both the resulting delay and complexity of the instruction issue circuit. | 11-01-2012 |
20120306535 | STRUCTURES AND METHODS FOR DESIGN AUTOMATION OF RADIATION HARDENED TRIPLE MODE REDUNDANT DIGITAL CIRCUITS - The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The | 12-06-2012 |
20120327725 | CIRCUIT DEVICES AND METHODS HAVING ADJUSTABLE TRANSISTOR BODY BIAS - Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed. | 12-27-2012 |
20130111282 | FAST PARALLEL TEST OF SRAM ARRAYS | 05-02-2013 |
20130154739 | ANALOG CIRCUITS HAVING IMPROVED TRANSISTORS, AND METHODS THEREFOR - Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. | 06-20-2013 |
20140049286 | SEQUENTIAL STATE ELEMENTS FOR TRIPLE-MODE REDUNDANT STATE MACHINES, RELATED METHODS, AND SYSTEMS - The disclosure relates generally to sequential state elements (SSEs), triple-mode redundant state machines (TMRSMs), and methods and systems for testing triple-mode redundant pipeline stages (TMRPSs) within the TMRSMs using triple-mode redundant SSEs (TMRSSEs). The SSEs, TMRSMs, TMRPSs, and TMRSSEs may be formed as integrated circuits on a semiconductor substrate. Of particular focus in this disclosure are SSEs used to sample and hold bit states. Embodiments of the SSEs have a self-correcting mechanism to protect against radiation-induced soft errors. The SSE may be provided in a pipeline circuit of a TMRSM to receive and store a bit state of a bit signal generated by combinational circuits within the pipeline circuit. More specifically, the SSEs may be provided in a TMRSSE configured to perform self-correction. Also disclosed are methods for using the TMRSSE to test redundant pipeline stages of the TMRSM. | 02-20-2014 |
20140077854 | SEQUENTIAL STATE ELEMENTS RADIATION HARDENED BY DESIGN - This disclosure relates generally to sequential state elements (SSEs). More specifically, embodiments of flip-flops are disclosed, along with computerized methods and systems of designing the same. In one embodiment, the flip-flop includes a substrate and subcircuits that are formed on the substrate. The subcircuits provide subfunctions, wherein each of the subcircuits provides at least one of the subfunctions. More specifically, the subfunctions are provided in a sequential logical order by the subcircuits so that the flip-flop provides a flip-flop function. However, the subcircuits are interleaved out of the sequential logical order with respect to a corresponding subfunction provided by each of the subcircuits along a vector defined by the substrate. In this manner, interleaving the subcircuits along the vector of the substrate can provide separation between charge collection nodes without requiring increases in size. Thus, the flip-flop can be more compact and less expensive to manufacture. | 03-20-2014 |
20140119099 | DRAM-TYPE DEVICE WITH LOW VARIATION TRANSISTOR PERIPHERAL CIRCUITS, AND RELATED METHODS - A dynamic random access memory (DRAM) can include at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor; a body bias control circuit configured to generate body bias voltage from a bias supply voltage, the body bias voltage being different from power supply voltages of the DRAM; and peripheral circuits formed in the same substrate as the at least one DRAM array, the peripheral circuits comprising deeply depleted channel (DDC) transistors having bodies coupled to receive the body bias voltage, each DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region. | 05-01-2014 |
20140204644 | LONGEST PREFIX MATCH INTERNET PROTOCOL CONTENT ADDRESSABLE MEMORIES AND RELATED METHODS - Embodiments of content addressable memories for internet protocol devices and operations are described herein. Other examples and related methods are also disclosed herein. | 07-24-2014 |
20140331197 | SEQUENTIAL STATE ELEMENTS IN TRIPLE-MODE REDUNDANT (TMR) STATE MACHINES - The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit. | 11-06-2014 |
20150015334 | ANALOG CIRCUITS HAVING IMPROVED TRANSISTORS, AND METHODS THEREFOR - Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. | 01-15-2015 |