Lau, MY
Kam Chuan Lau, Perak MY
Patent application number | Description | Published |
---|---|---|
20090026594 | Thin Plastic Leadless Package with Exposed Metal Die Paddle - A method of making electronic packages includes providing a leadframe strip that includes a plurality of leadframes, wherein the leadframes comprise a plurality of leads, etching a surface of each of the leadframes to form an opening, wherein each of the leads has a lead tip that connects to a die paddle within the opening, isolating each of the leads from the die paddle, adhering a tape to a bottom side of the leadframe strips, leads, and die paddle, attaching a die to the die paddle, placing ball bumps on each of the lead tips, and connecting the die to the ball bumps. The electronic package includes a leadframe having a plurality of leads, wherein each of the leads has a lead tip, an opening formed within the leadframe, a die paddle that is disposed within the opening and is isolated from each of the lead tips, a tape that is adhered to a back side of the leadframe, leads, and die paddle, and a die, wherein the die is attached to the die paddle and is connected by wires to a bump disposed on each of the lead tips. | 01-29-2009 |
Ker Yon Lau, My MY
Patent application number | Description | Published |
---|---|---|
20150288355 | VOLTAGE LEVEL SHIFT WITH CHARGE PUMP ASSIST - A charge pump assist circuit to assist a voltage level shifter to toggle an output based on an input. The charge pump assist circuit may be implemented to toggle the output at a higher rate than the voltage level shifter. The voltage level shifter may be biased with an undivided voltage rail, such as an operating voltage of the charge pump assist circuit, rather than a divided voltage rail, while maintaining or increasing a toggle rate. The charge pump assist circuit may include a non-overlapping control generator to generate non-overlapping differential controls, and may further include first and second charge pump multipliers to increase voltages of the differential controls by a multiple of the operating voltage. | 10-08-2015 |
Kin Yip Lau, Kuala Lumpur MY
Patent application number | Description | Published |
---|---|---|
20100063937 | TARIFF MANAGEMENT TEST AUTOMATION - A method for an operator to test tariff and/or billing configurations using a computer based system, the method being effected by a user interface, said method including the steps of creating through said computer based system one or more accounts from a selection of a first set of options by the operator from the user interface, allocating a service or services to each account from a selection of a second set of options by the operator from the user interface said allocated services being assigned to said accounts by said computer based system, adding at least one package or component to each account from a selection of a third set of options by the operator from the user interface said packages or components services being assigned to said accounts by said computer based system, associating at least one usage file to each account from a selection of a fourth set of options by the operator from the user interface said usage files being assigned to said accounts by said computer based system thereby providing bulk test data; and simulating operation of the accounts with said bulk test data using said computer based system to provide the operator with information on the cost of the usage defined in the at least one usage file according to the services and component and/or package associated with said accounts which define the tariff and/or billing configuration. | 03-11-2010 |
20100064171 | TARIFF MANAGEMENT DEPLOYMENT AUTOMATION - A method for an operator to deploy tariff and/or billing configurations represented by computer program code, the deployment being effected by operation of a user interface, the method including the steps of the operator identifying at least one configuration to be deployed, selecting the at least one configuration by use of the user interface, and associating the at least one configuration with at least one environment in which the computer program code representing the configuration must be executed to effect the configuration. | 03-11-2010 |
20100088248 | TARIFF MANAGEMENT CONFIGURATION AUTOMATION - Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a new tariff and/or billing configuration for a tariff and/or billing plan on a computer based system using an entity framework for an hierarchical arrangement of entities, the hierarchical arrangement representing a tariff and/or billing configuration, with each entity representing one or more characteristics of the configuration. One method provides that the entity framework is populated by copying an existing entity and/or by generating a new entity. | 04-08-2010 |
20130275283 | Tariff Management Test Automation - A method for an operator to test tariff and/or billing configurations using a computer based system, the method being effected by a user interface, said method including the steps of creating through said computer based system one or more accounts from a selection of a first set of options by the operator from the user interface, allocating a service or services to each account from a selection of a second set of options by the operator from the user interface said allocated services being assigned to said accounts by said computer based system, and adding at least one package or component to each account from a selection of a third set of options by the operator from the user interface said packages or components services being assigned to said accounts by said computer based system. | 10-17-2013 |
Lee-Lee Lau, Melaka MY
Patent application number | Description | Published |
---|---|---|
20120094488 | CHEMICAL MECHANICAL POLISHING PROCESS - A chemical mechanical polishing process includes placing a substrate on a first polishing pad of a first platen, wherein the substrate has a bulk metal layer and a barrier layer; polishing the bulk metal layer by using the first polishing pad having a hardness of above 50 (Shore D) until the barrier layer is exposed; polishing the barrier layer on a second polishing pad of a second platen after removing the bulk metal layer, wherein the second polishing pad has a hardness ranging between 40 and 50 (Shore D) and includes an upper layer and a lower backing layer and the upper layer has a hardness less than 50 (Shore D). | 04-19-2012 |
Sei-Wei Henry Lau, Penang MY
Patent application number | Description | Published |
---|---|---|
20130219137 | REDUNDANCY LOADING EFFICIENCY - A system comprising a processor and a memory, wherein said memory comprises instructions that when executed by said processor implement a method. The method includes loading a first portion of a set of redundancy data into a register of the processor for each redundant sector of a plurality of redundant sectors. A second portion of a set of redundancy data is also loaded into the volatile memory for each redundant sector of the plurality of redundant sectors. Loading the second portions of the sets of redundancy data comprises loading a third portion of redundancy data comprising a plurality of second portions of redundancy data for the plurality of redundant sectors. | 08-22-2013 |
Sie Wei Henry Lau, Bayan Lepas MY
Patent application number | Description | Published |
---|---|---|
20140185393 | DESIGN FOR TEST (DFT) READ SPEED THROUGH TRANSITION DETECTOR IN BUILT-IN SELF-TEST (BIST) SORT - A memory is disclosed that can operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory. In the normal mode of operation, the memory can perform the asynchronous read operation, the page read operation, an asynchronous write operation in which a word of electronic data is stored into the memory that correspond to the address, or a page write operation in which a page electronic data is stored into the memory that correspond to the multiple addresses. | 07-03-2014 |
Sie-Wei Henry Lau, Penang MY
Patent application number | Description | Published |
---|---|---|
20150253988 | Memory Access Bases on Erase Cycle Time - Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for improving a read margin in non-volatile semiconductor memory device. An embodiment includes measuring an erase-time of a memory block in a memory device and associating an indicator from the plurality Of indicators for the memory block. The indicator is saved and later retrieved during a read operation. | 09-10-2015 |
Siong Cho Lau, Perak MY
Patent application number | Description | Published |
---|---|---|
20100213608 | Solder bump UBM structure - Disclosed is an under bump metallization structure including a plurality of metal or metal alloy layers formed on chip bond pads. The disclosed UBM structure has a stress improvement on the semiconductor device because the thickness of the copper-base layer is reduced to between about 0.3 and 10 microns, preferably between about 0.3 and 2 micron. The presence of the pure tin layer prevents oxidation and contamination of the nickel-base layer. It also forms a good solderable surface for the subsequent processes. Also disclosed are semiconductor devices having the disclosed UBM structure and the methods of making the semiconductor devices. | 08-26-2010 |
20110079908 | Stress buffer to protect device features - Disclosed is a stress buffer structure intended to be disposed adjacent a face of a semiconductor substrate. The stress buffer structure includes at least one polymer layer formed on the face of the semiconductor substrate and a plurality of metal plates disposed over the polymer layer, wherein the metal plates is physically and electrically isolated from the bond pads of the semiconductor substrate. The disclosed stress buffer structure provides protection to semiconductor components that are sensitive to stress. Also disclosed are semiconductor packages having the disclosed stress buffer structure and the methods of making the semiconductor packages. | 04-07-2011 |
Swee Aun Lau, Penang MY
Patent application number | Description | Published |
---|---|---|
20120032276 | N-WELL/P-WELL STRAP STRUCTURES - Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers. | 02-09-2012 |
20120261738 | N-Well/P-Well Strap Structures - Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers. | 10-18-2012 |
20130140640 | N-WELL/P-WELL STRAP STRUCTURES - Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers. | 06-06-2013 |
Teck Beng Lau, Petaling Jaya MY
Patent application number | Description | Published |
---|---|---|
20120032167 | SEMICONDUCTOR PACKAGE AND METHOD OF TESTING SAME - A packaged integrated circuit includes a substrate having a wire layout pattern and a solder mask layer. An integrated circuit attached to a surface of the substrate is electrically connected to the wire layout pattern. An encapsulation material covers at least the integrated circuit and the solder mask layer. One or more crack seal rings are disposed on the solder mask surface. The crack seal rings are copper traces with terminals that allow current to be applied to the traces. A broken trace (open circuit condition) is indicative of a crack in the package. Thus, electrical testing is performed to detect physical defects. | 02-09-2012 |
20150118802 | DUAL CORNER TOP GATE MOLDING - A mold die includes a side wall forming a hollow cavity and opposing first and second axial ends. The side wall has first and second openings respectively at the first and second axial ends. Each of the first and second openings accesses the hollow cavity. A main wall is coupled to the side wall at the first end thereof and spans the first opening. A center of the main wall is aligned with a longitudinal axis of the side wall. The main wall defines a plane oriented generally perpendicularly with respect to the longitudinal axis of the side wall. First and second gates are formed through the main wall to access the hollow cavity. The first and second gates define a first line lying in the plane of the main wall. The center of the main wall is located on the first line between the first and second gates. | 04-30-2015 |
20150137279 | MULTI-DIE SENSOR DEVICE - A semiconductor device includes a lead frame having a flag and leads that surround the flag. The leads include a dummy lead that has first and second wire bonding areas. A first die is attached on the flag and electrically connected to the first wire bonding area. The first die and the first wire bonding area are encapsulated with a molding material and a cavity with an opening is formed above the first die. The second wire bonding area is exposed in the cavity. A second die is placed in the cavity and electrically connected to the second wire bonding area such that the second die is electrically connected to the first die by way of the dummy lead. | 05-21-2015 |
Wai Shin Lau, Penang MY
Patent application number | Description | Published |
---|---|---|
20090158071 | INTEGRATED POWER MANAGEMENT LOGIC - A device and system are disclosed. In one embodiment the device includes a programmable power supply management logic. The programmable power supply management logic is capable of managing a plurality of voltage regulators present in a computer system. Additionally, the power supply management logic is integrated into an input/output complex in the computer system. | 06-18-2009 |
Wei-Chin Lau, Bayan Lepas MY
Patent application number | Description | Published |
---|---|---|
20140237815 | STIFFENER FRAME FIXTURE - Methods and apparatus for coupling a stiffener frame to a circuit board are disclosed. In one aspect, an apparatus for engaging a stiffener frame and a circuit board positioned in a fixture is provided. The stiffener frame includes an edge. The apparatus includes an alignment plate that has a shoulder to engage the edge of the stiffener frame. The alignment plate includes a first opening with a peripheral wall to restrain movement of a circuit board relative to the stiffener frame. | 08-28-2014 |
Wen Han Lau, Penang MY
Patent application number | Description | Published |
---|---|---|
20090042329 | Laser Process for Reliable and Low-Resistance Electrical Contacts - Disclosed is a method for manufacturing an organic optoelectronic device. The method comprises providing a substrate, disposing a first electrode on the substrate, disposing a metal pad on the substrate, electrically separated from the first electrode, disposing a first material over the first electrode and at least partially over the metal pad, applying a beam, wherein the beam ablates the first material in an ablation window so that the ablation window includes at least a portion of an edge of the metal pad, and disposing a second electrode over the first material and over the ablation window so that the second electrode is in electrical contact with the at least a portion of an edge of the metal pad. | 02-12-2009 |
William Siang Lim Lau, Kuching MY
Patent application number | Description | Published |
---|---|---|
20110198690 | TRANSISTOR - A Metal Oxide Semiconductor (MOS) transistor comprising: a source; a gate; and a drain, the source, gate and drain being located in or on a well structure of a first doping polarity located in or on a substrate; wherein at least one of the source and the drain comprises a first structure comprising: a first region forming a first drift region, the first region being of a second doping polarity opposite the first doping polarity; a second region of the second doping polarity in or on the first region, the second region being a well region and having a doping concentration which is higher than the doping concentration of the first region; and a third region of the second doping polarity in or on the second region. Due to the presence of the second region the transistor may have a lower ON resistance when compared with a similar transistor which does not have the second region. The breakdown voltage may be influenced only to a small extent. | 08-18-2011 |