Patent application number | Description | Published |
20080226992 | STRUCTURE AND METHOD FOR SUB-RESOLUTION DUMMY CLEAR SHAPES FOR IMPROVED GATE DIMENSIONAL CONTROL - A mask system for use by a lithographic system to project an image of a circuit design. The design includes at least one large feature and at least one nearby small feature. The mask comprises one or more shapes on a mask to project an image of the nearby small feature and, on the same mask or on a different mask, an opaque shape to project an image of the large feature. The opaque shape includes in a field thereof at least one dummy clear shape of size and configuration insufficient to be resolved. Light from the lithographic projection system may be projected through the opaque shape and the dummy clear shape to resolve an image of the large circuit feature on a resist layer of a wafer without resolving the clear shape on the resist layer, while simultaneously increasing optical flare on the resolved large circuit feature image. | 09-18-2008 |
20090032956 | DUMMY METAL FILL SHAPES FOR IMPROVED RELIABILITY OF HYBRID OXIDE/LOW-K DIELECTRICS - A semiconductor structure including a first rigid dielectric layer and a second rigid dielectric layer. A first non-rigid low-k dielectric layer is formed between the first and second rigid dielectric layer. A plurality of dummy fill shapes is formed in the first non-rigid layer which replace portions of the first non-rigid low-k dielectric layer with lower coefficient of thermal expansion (CTE) metal such that an overall CTE of the first non-rigid low-k dielectric layer and the plurality of dummy fill shapes matches a CTE of the first and second rigid dielectric layers more closely than that of the first non-rigid low-k dielectric layer alone. | 02-05-2009 |
20090100399 | DESIGN STRUCTURE FOR PARTITIONED DUMMY FILL SHAPES FOR REDUCED MASK BIAS WITH ALTERNATING PHASE SHIFT MASKS - A design structure, method, and system for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks, or with other two-mask lithographic processes employing a trim mask. A design structure is embodied in a machine readable medium used in a design process, the design structure comprising regions in a finished semiconductor design that do not contain as-designed shapes. The design structure additionally includes dummy fill shapes in the regions at a predetermined final density, wherein the generated dummy shapes are sized so that their local density is increased to a predetermined value. Moreover, corresponding trim shapes act to expose an oversized portion of the dummy shape, effectively trimming each dummy shape back to the predetermined final density. | 04-16-2009 |
20090193378 | MODIFYING LAYOUT OF IC BASED ON FUNCTION OF INTERCONNECT AND RELATED CIRCUIT AND DESIGN STRUCTURE - Modifying a layout of an integrated circuit (IC) based on a function of an interconnect therein and a related circuit and design structure are disclosed. In one embodiment, a method includes identifying a function of an interconnect in the layout from data of the layout embodied in a computer readable medium; and modifying the layout to form another layout that accommodates the function of the interconnect. A design structure embodied in a machine readable medium used in a design process, according to one embodiment, may include a circuit including a high voltage interconnect positioned in a dielectric layer, the high voltage interconnect positioned such that no fill is above or below the high voltage interconnect. | 07-30-2009 |
20100264545 | Metal Fill Structures for Reducing Parasitic Capacitance - Vertically-staggered-level metal fill structures include inner contiguous metal fill structures and outer contiguous metal fill structures. A dielectric material portion is provided between each contiguous metal fill structure. Vertical extent of each contiguous metal fill structure is limited up to three vertically adjoining metal interconnect levels, thereby limiting the capacitance of each contiguous metal fill structure. Capacitive coupling between the contiguous metal fill structures and the metal interconnect structures is minimized due to the fragmented structure of contiguous metal fill structures. | 10-21-2010 |
20110289470 | Methods and Systems to Meet Technology Pattern Density Requirements of Semiconductor Fabrication Processes - Techniques, systems, and methods are provided for optimizing pattern density fill patterns for integrated circuits. The method includes adjusting an area of a scribe line and a density of dummy fill shapes in the adjusted scribe line, while maintaining an area of the die, to achieve a pattern density associated with technology ground rules for a particular design of the die. | 11-24-2011 |
20120126294 | WAFER FILL PATTERNS AND USES - A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements. | 05-24-2012 |
20130181267 | WAFER FILL PATTERNS AND USES - A semiconductor device includes an active region including an element formed in a double etch, double exposure method and an inactive region including one or more fills, at least one of the one or more fills including a cut-away hole formed therein, where the cut-away holes expose a layer in the inactive region used for an endpoint detection. | 07-18-2013 |
20130183832 | NEAR-NEIGHBOR TRIMMING OF DUMMY FILL SHAPES WITH BUILT-IN OPTICAL PROXIMITY CORRECTIONS FOR SEMICONDUCTOR APPLICATIONS - Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections (OPCs) for semiconductor applications is provided. A method for the near-neighbor trimming includes adding one or more hole shapes onto a semiconductor design layout comprising a plurality of design shapes. The method further includes trimming adjacent ones of the plurality of which are covered by the one or more hole shapes. | 07-18-2013 |
20140021622 | OPTIMIZATION METALLIZATION FOR PREVENTION OF DIELECTRIC CRACKING UNDER CONTROLLED COLLAPSE CHIP CONNECTIONS - A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads. | 01-23-2014 |
20140215417 | NEAR-NEIGHBOR TRIMMING OF DUMMY FILL SHAPES WITH BUILT-IN OPTICAL PROXIMITY CORRECTIONS FOR SEMICONDUCTOR APPLICATIONS - Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections (OPCs) for semiconductor applications is provided. A method for the near-neighbor trimming includes adding one or more hole shapes onto a semiconductor design layout comprising a plurality of design shapes. The method further includes trimming adjacent ones of the plurality of which are covered by the one or more hole shapes. | 07-31-2014 |
Patent application number | Description | Published |
20080272457 | Formation Of Dummy Features And Inductors In Semiconductor Fabrication - A structure and a method for forming the same. The structure includes (a) a substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface, (b) N semiconductor regions on the substrate, and (c) P semiconductor regions on the substrate, N and P being positive integers. The N semiconductor regions comprise dopants. The P semiconductor regions do not comprise dopants. The structure further includes M interconnect layers on top of the substrate, the N semiconductor regions, and the P semiconductor regions, M being a positive integer. The M interconnect layers include an inductor. (i) The N semiconductor regions do not overlap and (ii) the P semiconductor regions overlap the inductor in the reference direction. A plane perpendicular to the reference direction and intersecting a semiconductor region of the N semiconductor regions intersects a semiconductor region of the P semiconductor regions. | 11-06-2008 |
20100230752 | SOI (SILICON ON INSULATOR) SUBSTRATE IMPROVEMENTS - A structure, and a method for forming the same. The structure includes a semiconductor substrate which includes a top substrate surface, a buried dielectric layer on the top substrate surface, N active semiconductor regions on the buried dielectric layer, N active devices on the N active semiconductor regions, a plurality of dummy regions on the buried dielectric layer, a protection layer on the N active devices and the N active semiconductor regions, but not on the plurality of dummy regions. The N active devices comprise first active regions which comprise a first material. The plurality of dummy regions comprise first dummy regions which comprise the first material. A first pattern density of the first active regions and the first dummy regions is uniform across the structure. A trench in the buried dielectric layer such that side walls of the trench are aligned with the plurality of dummy regions. | 09-16-2010 |
20100242012 | FORMATION OF MASKS/RETICLES HAVING DUMMY FEATURES - A method of forming a mask. The method includes providing design information of a design layer. The design layer includes M original design features and N original dummy features. The method further includes (i) creating a cluster of P representative dummy features, P being a positive integer less than N, (ii) performing OPC for the cluster of the P representative dummy features but not for the N original dummy features, resulting in P OPC-applied representative dummy features, and (iii) forming the mask including N mask dummy features. The N mask dummy features are identical. Each mask dummy feature of the N mask dummy features of the mask has an area which is a function of at least an area of an OPC-applied representative dummy feature of the P OPC-applied representative dummy features. The N mask dummy features have the same relative positions as the N original dummy features. | 09-23-2010 |