Patent application number | Description | Published |
20130128822 | CARRIER TRACKING WITHOUT PILOTS - A carrier tracking technique includes allocating a first number of bits per symbol to a carrier tracking subcarrier of a plurality of subcarriers of an orthogonal frequency division multiplexing (OFDM) signal based on a first target performance margin. The technique includes allocating numbers of bits per symbol to other subcarriers of the plurality of subcarriers based on a second target performance margin. | 05-23-2013 |
20130128995 | CHANNEL ESTIMATION IN A COMMUNICATIONS SYSTEM - A method includes generating representative noise variance estimates based on a plurality of received symbols received in an orthogonal frequency division multiplexing (OFDM) signal. The representative noise variance estimates correspond to respective frequency intervals of a plurality of frequency intervals of the OFDM channel. Individual frequency intervals of the plurality of frequency intervals include a plurality of contiguous frequency bins of the OFDM signal. | 05-23-2013 |
20130177088 | DETECTION OF A PACKET TYPE IN A COMMUNICATIONS SYSTEM - A technique detects the presence of a packet identification sequence in a received sequence of samples received over a communications network. The packet identification sequence, when present and properly detected in a received packet, is used to determine a particular type of the received packet from a plurality of packet types that may be received over the communications network. The technique for detecting the packet identification sequence includes detecting a null sequence in the received packet and a predetermined identification sequence in the packet. Detection of the predetermined sequence uses energy estimates for corresponding windows of received samples. | 07-11-2013 |
20130177112 | AUTOMATIC GAIN CONTROL IN A COMMUNICATIONS SYSTEM - An automatic gain control technique generates one or more gain control signals based on a known sequence of samples received in a preamble of a packet received over a particular communications link and generates one or more adjusted gain control signals based on a previously unknown sequence of samples received in a payload of a packet. In at least one embodiment of the gain control technique, time domain samples of the preamble of a symbol are used to generate the one or more gain control signals. In at least one embodiment of the gain control technique, frequency domain samples are used to generate the one or more adjusted gain control signals. The one or more gain control signals include digital and/or analog gain control signals that are provided to digital signal processing modules and/or analog circuits in an interface circuit, respectively, to adjust the gain applied to a received signal. | 07-11-2013 |
20140321403 | Carrier Tracking Without Pilots - A carrier tracking technique includes allocating a first number of bits per symbol to a carrier tracking subcarrier of a plurality of subcarriers of an orthogonal frequency division multiplexing (OFDM) signal based on a first target performance margin. The technique includes allocating numbers of bits per symbol to other subcarriers of the plurality of subcarriers based on a second target performance margin. | 10-30-2014 |
20150271699 | OFDMA SUBCHANNEL ASSIGNMENT - A device includes a signaling interface to receive OFDM signaling for an OFDM channel from multiple transmit nodes, an OFDM receiver to process the OFDM signaling, and a channel allocation module. The channel allocation module allocates subchannels of the channel among transmit nodes by: determining, for each transmit node, a corresponding SNR for each of the subchannels; assigning to each transmit node a corresponding subset of buckets of a set of buckets, the number of buckets in the subset based on a data rate requirement of the transmit node; distributing subchannels among the buckets based on the SNRs of the subchannels; and, for each transmit node, allocating to the transmit node the subchannels distributed to the subset of buckets assigned to the transmit node. The device further includes an OFDM transmitter to transmit configuration information to the transmit nodes, the configuration information representing the allocation of the subchannels. | 09-24-2015 |
20150271832 | PILOT SELECTION FOR OFDMA CARRIER TRACKING - A device includes a signaling interface to receive OFDM signaling for an OFDM channel from a plurality of transmit nodes and an OFDM receiver process the OFDM signaling. The device further includes a channel allocation module to determine, for each transmit node, a corresponding SNR for each of a plurality of subchannels of the channel and to allocate, to each transmit node of the plurality of transmit nodes, a corresponding subset of subchannels of the plurality of subchannels. The channel allocation module further is to select, for each subset of subchannels, one or more subchannels for use as pilots by the corresponding transmit node based on the SNRs of the subchannels in the subset. The device further includes an OFDM transmitter to transmit configuration information to the plurality of transmit nodes, the configuration information representing the allocation of the subchannels and the selection of subchannels for use as pilots. | 09-24-2015 |
Patent application number | Description | Published |
20090264854 | Systems and Methods for Delivery of Peritoneal Dialysis (PD) Solutions - The invention provides container systems, kits and methods for peritoneal dialysis (PD) solutions. Such a system, for example, includes a first compartment that contains a PD osmotic agent and a second compartment that contains a PD buffer agent. The compartments maintain their respective contents separately from one another for purposes of transport, storage and/or sterilization. However, the compartments are fluidly couplable, so that their respective contents can be combined with one another, e.g., following sterilization of the agents and prior to their introduction into the patient's abdomen. The invention provides, in other aspects, such systems, kits and methods that provide protective structure which inhibits breaking of a seal prior between the second compartment and an outlet of the system, prior to breaking of a seal between the first and second compartments. | 10-22-2009 |
20100168652 | METHODS AND APPARATUS FOR DELIVERING PERITONEAL DIALYSIS (PD) SOLUTION WITH A PERISTALTIC PUMP - In one aspect, the invention provides methods and apparatus for delivering peritoneal dialysis (PD) solution (or other fluids), from a supply to a patient. A first pump, in fluid coupling with the supply, delivers PD solution from the supply to a “mesne” (or intermediate) measuring element, and generates signals indicative of a volume of that delivered PD solution. The mesne measuring element, in fluid coupling with the first pump, generates signals indicative of a volume of PD solution received from that pump. A second pump, fluidly coupled to the mesne measuring element, routes PD solution from the mesne measuring element for delivery to the patient. | 07-01-2010 |
20120259275 | SYSTEMS AND METHODS FOR DELIVERY OF PERITONEAL DIALYSIS (PD) SOLUTIONS - The invention provides container systems, kits and methods for peritoneal dialysis (PD) solutions. Such a system, for example, includes a first compartment that contains a PD osmotic agent and a second compartment that contains a PD buffer agent. The compartments maintain their respective contents separately from one another for purposes of transport, storage and/or sterilization. However, the compartments are fluidly couplable, so that their respective contents can be combined with one another, e.g., following sterilization of the agents and prior to their introduction into the patient's abdomen. The invention provides, in other aspects, such systems, kits and methods that provide protective structure which inhibits breaking of a seal prior between the second compartment and an outlet of the system, prior to breaking of a seal between the first and second compartments. | 10-11-2012 |
Patent application number | Description | Published |
20080316566 | HIGH APERTURE-RATIO TOP-REFLECTIVE AM-IMOD DISPLAYS - High-aperture-ratio devices comprise active-matrix elements and interferometric modulators and methods of making thereof. The active-matrix element may be positioned behind the interferometric modulator with respect to incident light. In some embodiments, components of the active-matrix element may be formed on a first substrate, while components of the interferometric modulator may be formed on a second substrate, and the substrates may then be attached. | 12-25-2008 |
20090040136 | ESD PROTECTION FOR MEMS DISPLAY PANELS - A MEMS (Microelectromechanical system) device is described. The device includes an array of MEMS elements with addressing lines and MEMS switches configured to selectively connect the addressing lines to a ground or other potential in the event of an over-voltage, such as during an ESD event. The arrangement is particularly advantageous for protecting the array, because the MEMS switches can be formed using substantially the same processing steps which are used to form the array. | 02-12-2009 |
20090244683 | APPARATUS AND METHOD OF DUAL-MODE DISPLAY - One embodiment includes display comprising a light modulator configured to display a portion of an image such as a reflective light modulator, a light emitter configured to display the portion of the image and a circuit configured to selectively provide signals to at least one of the light modulator and the light emitter indicative of the portion of the image. In one such embodiment, an active matrix provides a simple, efficient drive for such devices. Other embodiments methods of making and driving such devices. | 10-01-2009 |
20100014146 | ENCAPSULATION METHODS FOR INTERFEROMETRIC MODULATOR AND MEMS DEVICES - Methods and devices used for the encapsulation of MEMS devices, such as an interferometric modulator, are disclosed. Encapsulation is provided to MEMS devices to protect the devices from such environmental hazards as moisture and mechanical shock. In addition to the encapsulation layer providing protection from environmental hazards, the encapsulation layer is additionally planarized so as to function as a substrate for additional circuit elements formed above the encapsulation layer. | 01-21-2010 |
20100123706 | APPARATUS AND METHOD OF DUAL-MODE DISPLAY - One embodiment includes display comprising a light modulator configured to display a portion of an image such as a reflective light modulator, a light emitter configured to display the portion of the image and a circuit configured to selectively provide signals to at least one of the light modulator and the light emitter indicative of the portion of the image. In one such embodiment, an active matrix provides a simple, efficient drive for such devices. Other embodiments methods of making and driving such devices. | 05-20-2010 |
20100290102 | ENCAPSULATED ELECTROMECHANICAL DEVICES - Encapsulation is provided to electromechanical devices to protect the devices from such environmental hazards as moisture and mechanical shock. In addition to the encapsulation layer providing protection from environmental hazards, the encapsulation layer is additionally planarized so as to function as a substrate for additional circuit elements formed above the encapsulation layer. | 11-18-2010 |
20110109383 | MEMS VARACTORS - MEMS varactors capable of handling large signals and/or achieving a high capacitance tuning range are described. In an exemplary design, a MEMS varactor includes (i) a first bottom plate electrically coupled to a first terminal receiving an input signal, (ii) a second bottom plate electrically coupled to a second terminal receiving a DC voltage, and (iii) a top plate formed over the first and second bottom plates and electrically coupled to a third terminal. The DC voltage causes the top plate to mechanically move and vary the capacitance observed by the input signal. In another exemplary design, a MEMS varactor includes first, second and third plates formed on over one another and electrically coupled to first, second and third terminals, respectively. First and second DC voltages may be applied to the first and third terminals, respectively. An input signal may be passed between the first and second terminals. | 05-12-2011 |
20110149374 | TWO-TERMINAL VARIABLE CAPACITANCE MEMS DEVICE - A two-terminal, variable capacitance device is described that is constructed by connecting multiple MEMS devices having different actuation or “pull in” voltages in parallel. | 06-23-2011 |
20110316899 | APPARATUS AND METHOD OF DUAL-MODE DISPLAY - One embodiment includes display comprising a light modulator configured to display a portion of an image such as a reflective light modulator, a light emitter configured to display the portion of the image and a circuit configured to selectively provide signals to at least one of the light modulator and the light emitter indicative of the portion of the image. In one such embodiment, an active matrix provides a simple, efficient drive for such devices. Other embodiments include methods of making and driving such devices. | 12-29-2011 |
20120162232 | METHOD OF FABRICATION AND RESULTANT ENCAPSULATED ELECTROMECHANICAL DEVICE - This disclosure provides systems, methods, and apparatus for encapsulated electromechanical systems. In one aspect, a release path includes a release hole through an encapsulation layer. The release path exposes a portion of a first sacrificial layer that extends beyond a second sacrificial layer in a horizontal direction. This allows the first sacrificial layer and the second sacrificial layer to later be etched through the release path. The corresponding electromechanical system device includes a shell layer encapsulating a mechanical layer. A conformal layer seals a release hole that extends through a shell layer. A portion of the conformal layer blocks the opening of the release passage within the release hole. The release passage has substantially the same vertical height as a gap that defines the spacing between the mechanical layer and a substrate. | 06-28-2012 |
20140009862 | MEMS VARACTORS - Tunable MEMS resonators having adjustable resonance frequency and capable of handling large signals are described. In one exemplary design, a tunable MEMS resonator includes (i) a first part having a cavity and a post and (ii) a second part mated to the first part and including a movable layer located under the post. Each part may be covered with a metal layer on the surface facing the other part. The movable plate may be mechanically moved by a DC voltage to vary the resonance frequency of the MEMS resonator. The cavity may have a rectangular or circular shape and may be empty or filled with a dielectric material. The post may be positioned in the middle of the cavity. The movable plate may be attached to the second part (i) via an anchor and operated as a cantilever or (ii) via two anchors and operated as a bridge. | 01-09-2014 |
Patent application number | Description | Published |
20110234357 | Three Dimensional Inductor and Transformer Design Methodology of Glass Technology - An inductor or transformer for use in integrated circuit devices that includes a high-resistivity substrate. The inductor includes a plurality of conductive traces around the substrate forming a continuous conductive path from a first to a second port. The conductive path can be solenoid-shaped. Some of the conductive traces can be formed during back-end-of-line processing or backside plating of an integrated circuit die. The transformer includes a first inductor with input and output ports, and a first continuous conductive path therebetween; and a second inductor with input and output ports, and a second continuous conductive path therebetween. The second inductor is independent of and electromagnetically coupled to the first inductor. The first and second conductive paths can be solenoid-shaped. The first conductive path can be interleaved with the second conductive path. | 09-29-2011 |
20120199949 | High Density Metal-Insulator-Metal Trench Capacitor - Higher capacitance density is achieved by increasing a surface area of a capacitor. A larger surface area may be obtained by forming isotropic ball shapes (a concave surface) in the trenches on the semiconductor die. The concave surfaces are fabricated by depositing bilayers of amorphous-silicon and silicon oxide. Openings are patterned in the silicon oxide hard mask for trenches. The openings are transferred to the amorphous-silicon layers through isotropic etching to form concave surfaces. Conducting, insulating, and conducting layers are deposited on the concave surfaces of the trenches by atomic layer deposition. | 08-09-2012 |
20120274647 | PIEZOELECTRIC RESONATORS AND FABRICATION PROCESSES - This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, a sacrificial layer is deposited on an insulating substrate. A lower electrode layer is formed proximate the sacrificial layer. A piezoelectric layer is deposited on the lower electrode layer. An upper electrode layer is formed on the piezoelectric layer. At least a portion of the sacrificial layer is removed to define a cavity such that at least a portion of the lower electrode layer is spaced apart from the insulating substrate. | 11-01-2012 |
20120286886 | Electromechanical Systems Oscillator with Piezoelectric Contour Mode Resonator for Multiple Frequency Generation - Electromechanical systems resonator structures, devices, circuits, and systems are disclosed. In one aspect, an oscillator includes an active component and a passive component connected in a feedback configuration. The passive component includes one or more contour mode resonators (CMR). A CMR includes a piezoelectric layer disposed between a first conductive layer and a second conductive layer. The conductive layers include an input electrode and an output electrode. The passive component is configured to output a first resonant frequency and a second resonant frequency, which is an odd integer harmonic of the first resonant frequency. The active component is configured to output a signal including the first resonant frequency and the second resonant frequency. This output signal can be a substantially square wave signal, which can serve as a clock in various applications. | 11-15-2012 |
20120293520 | PIEZOELECTRIC RESONATORS WITH CONFIGURATIONS HAVING NO GROUND CONNECTIONS TO ENHANCE ELECTROMECHANICAL COUPLING - This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, resonator apparatus includes a first conductive layer including a first electrode and a second electrode. The first electrode is coupled to receive a first input signal, and the second electrode is coupled to provide a first output signal. A piezoelectric layer includes a piezoelectric material. The piezoelectric layer has a first side and a second side opposite the first side. The first side is proximate the first conductive layer, and the second side is electrically isolated from ground. In some examples, the second side of the piezoelectric layer can be exposed and/or electrically de-coupled from one or more components. | 11-22-2012 |
20130176657 | ELECTROMECHANICAL SYSTEMS VARIABLE CAPACITANCE ASSEMBLY - This disclosure provides systems, methods and apparatus for a variable capacitance apparatus. In one aspect, an apparatus includes a plurality of electromechanical systems varactors connected in parallel. Each of the plurality of electromechanical systems varactors includes a first, a second, and a third metal layer. The first metal layer includes a first bias electrode. The second metal layer is spaced apart from the first metal layer to define a first air gap, and includes a first radio frequency electrode. A third metal layer is spaced apart from the second metal layer to define a second air gap, and includes a second radio frequency electrode and a second bias electrode. The second bias electrode of each of the plurality of electromechanical systems varactors has a different projected area perpendicular to a surface of the second metal layer and onto the surface of the second metal layer. | 07-11-2013 |
20140138792 | HYBRID TRANSFORMER STRUCTURE ON SEMICONDUCTOR DEVICES - Several novel features pertain to a hybrid transformer formed within a semiconductor die having multiple layers. The hybrid transformer includes a first set of windings positioned on a first layer of the die. The first layer is positioned above a substrate of the die. The first set of windings includes a first port and a second port. The first set of windings is arranged to operate as a first inductor. The hybrid transformer includes a second set of windings positioned on a second layer of the die. The second layer is positioned above the substrate. The second set of windings includes a third port, a fourth port and a fifth port. The second set of windings is arranged to operate as a second inductor and a third inductor. The first set of windings and the second set of windings are arranged to operate as a vertical coupling hybrid transformer. | 05-22-2014 |
20140197902 | DIPLEXER DESIGN USING THROUGH GLASS VIA TECHNOLOGY - A diplexer includes a substrate having a set of through substrate vias. The diplexer also includes a first set of traces on a first surface of the substrate. The first traces are coupled to the through substrate vias. The diplexer further includes a second set of traces on a second surface of the substrate that is opposite the first surface. The second traces are coupled to opposite ends of the set of through substrate vias. The through substrate vias and the traces also operate as a 3D inductor. The diplexer also includes a capacitor supported by the substrate. | 07-17-2014 |
20140240072 | VERTICAL-COUPLING TRANSFORMER WITH AN AIR-GAP STRUCTURE - In a particular embodiment, a device includes a low-loss substrate, a first inductor structure, and an air-gap. The first inductor structure is between the low-loss substrate and a second inductor structure. The first inductor structure is aligned with the second inductor structure to form a transformer. The air-gap is between the first inductor structure and the second inductor structure. | 08-28-2014 |
20140251947 | METHOD AND APPARATUS FOR LIGHT INDUCED ETCHING OF GLASS SUBSTRATES IN THE FABRICATION OF ELECTRONIC CIRCUITS - A method of etching a glass substrate using an etchant that is reversibly activated to etch only in precise locations in which such etching is desired and is deactivated when outside of these locations. The method involves exposing a first side of the glass substrate to a mixture of chemical substances that includes a neutralized etchant that is photosensitive. The neutralized etchant is formed by reacting a neutralizer with an etchant. The method also includes transmitting light from a direction of a second side of the glass into the mixture of chemical substances. In response to exposure to this light, the etchant is reversibly released from a bond to the neutralizer to form the etchant on predetermined areas of the first side of the glass, wherein the predetermined areas are defined by the dimension of the light. | 09-11-2014 |
20140266494 | INTEGRATION OF A REPLICA CIRCUIT AND A TRANSFORMER ABOVE A DIELECTRIC SUBSTRATE - A particular device includes a replica circuit disposed above a dielectric substrate. The replica circuit includes a thin film transistor (TFT) configured to function as a variable capacitor or a variable resistor. The device further includes a transformer disposed above the dielectric substrate and coupled to the replica circuit. The transformer is configured facilitate an impedance match between the replica circuit and an antenna. | 09-18-2014 |
20140268616 | CAPACITOR WITH A DIELECTRIC BETWEEN A VIA AND A PLATE OF THE CAPACITOR - In a particular embodiment, a device includes a substrate, a via that extends at least partially through the substrate, and a capacitor. A dielectric of the capacitor is located between the via and a plate of the capacitor, and the plate of the capacitor is external to the substrate and within the device. | 09-18-2014 |
20140327496 | TUNABLE DIPLEXERS IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS (IC) (3DIC) AND RELATED COMPONENTS AND METHODS - Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used. | 11-06-2014 |
20140327508 | INDUCTOR TUNABLE BY A VARIABLE MAGNETIC FLUX DENSITY COMPONENT - An inductor tunable by a variable magnetic flux density component is disclosed. A particular device includes an inductor. The device further includes a variable magnetic flux density component (VMFDC) positioned to influence a magnetic field of the inductor when a current is applied to the inductor. | 11-06-2014 |
20140327510 | ELECTRONIC DEVICE HAVING ASYMMETRICAL THROUGH GLASS VIAS - An electronic device includes a structure. The structure includes a first set of through glass vias (TGVs) and a second set of TGVs. The first set of TGVs includes a first via and the second set of TGVs includes a second via. The first via has a different cross-sectional shape than the second via. | 11-06-2014 |
20140354372 | SYSTEMS FOR REDUCING MAGNETIC COUPLING IN INTEGRATED CIRCUITS (ICS), AND RELATED COMPONENTS AND METHODS - Systems for reducing magnetic coupling in integrated circuits (ICs) are disclosed. Related components and methods are also disclosed. The ICs have a plurality of inductors. Each inductor generates a magnetic flux that has a discernible axis. To reduce magnetic coupling between the inductors, the flux axes are designed so as to be non-parallel. In particular, by making the flux axes of the inductors non-parallel to one another, magnetic coupling between the inductors is reduced relative to the situation where the flux axes are parallel. This arrangement may be particularly well suited for use in diplexers having a low pass and a high pass filter. | 12-04-2014 |
20140354378 | DESIGN FOR HIGH PASS FILTERS AND LOW PASS FILTERS USING THROUGH GLASS VIA TECHNOLOGY - A filter includes a glass substrate having through substrate vias. The filter also includes capacitors supported by the glass substrate. The capacitors may have a width and/or thickness less than a printing resolution. The filter also includes a 3D inductor within the substrate. The 3D inductor includes a first set of traces on a first surface of the glass substrate coupled to the through substrate vias. The 3D inductor also includes a second set of traces on a second surface of the glass substrate coupled to opposite ends of the through substrate vias. The second surface of the glass substrate is opposite the first surface of the glass substrate. The through substrate vias and traces operate as the 3D inductor. The first set of traces and the second set of traces may also have a width and/or thickness less than the printing resolution. | 12-04-2014 |
20140374914 | STRESS COMPENSATION PATTERNING - An apparatus includes a device that includes at least one layer. The at least one layer includes an inter-device stress compensation pattern configured to reduce an amount of inter-device warpage prior to the device being detached from another device. | 12-25-2014 |
20150014812 | THICK CONDUCTIVE STACK PLATING PROCESS WITH FINE CRITICAL DIMENSION FEATURE SIZE FOR COMPACT PASSIVE ON GLASS TECHNOLOGY - An integrated circuit device includes a substrate, and a first interlayer dielectric layer on the substrate that includes a first conductive layer and a second conductive layer. The integrated circuit device also includes a first conductive stack including a third conductive layer coupled to a portion of the second conductive layer with a first via. The integrated circuit device further includes a second conductive stack comprising a fourth conductive layer directly on a portion of the third conductive layer that is isolated from the substrate. The integrated circuit device also includes a second interlayer dielectric layer surrounding the third conductive layer and the fourth conductive layer. | 01-15-2015 |
20150035162 | INDUCTIVE DEVICE THAT INCLUDES CONDUCTIVE VIA AND METAL LAYER - An inductive device that includes a conductive via and a metal layer are disclosed. A particular method of forming an electronic device includes forming a metal layer that contacts a surface of a substrate. The substrate, including the surface, is formed from a substantially uniform dielectric material. The metal layer contacts a conductive via that extends at least partially within the substrate. The metal layer and the conductive via form at least a portion of an inductive device. | 02-05-2015 |
20150061813 | VARYING THICKNESS INDUCTOR - A particular device includes a substrate and a spiral inductor coupled to the substrate. The spiral inductor includes a first conductive spiral and a second conductive spiral overlaying the first conductive spiral. A first portion of an innermost turn of the spiral inductor has a first thickness in a direction perpendicular to the substrate. The first portion of the innermost turn includes a first portion of the first conductive spiral and does not include the second conductive spiral. A second portion of the innermost turn includes a first portion of the second conductive spiral. A portion of an outermost turn of the spiral inductor has a second thickness in the direction perpendicular to the substrate that is greater than the first thickness. A portion of the outermost turn includes a second portion of the first conductive spiral and a second portion of the second conductive spiral. | 03-05-2015 |
Patent application number | Description | Published |
20120075216 | INTEGRATED PASSIVES AND POWER AMPLIFIER - This disclosure provides systems, methods and apparatus for combining devices deposited on a first substrate, with integrated circuits formed on a second substrate such as a semiconducting substrate or a glass substrate. The first substrate may be a glass substrate. The first substrate may include conductive vias. A power combiner circuit may be deposited on a first side of the first substrate. The power combiner circuit may include passive devices deposited on at least the first side of the first substrate. The integrated circuit may include a power amplifier circuit disposed on and configured for electrical connection with the power combiner circuit, to form a power amplification system. The conductive vias may include thermal vias configured for conducting heat from the power amplification system and/or interconnect vias configured for electrical connection between the power amplification system and a conductor on a second side of the first substrate. | 03-29-2012 |
20130235001 | PIEZOELECTRIC RESONATOR WITH AIRGAP - This disclosure provides implementations of electromechanical systems (EMS) piezoelectric resonator structures, transformers, devices, apparatus, systems, and related processes. In one aspect, a piezoelectric resonator structure includes a first conductive electrode layer, a second conductive electrode layer, and a piezoelectric layer arranged between the first and second conductive layers. In some implementations, the surface of the piezoelectric layer adjacent to the first conductive layer is separated from the first conductive layer by a first gap, and the surface of the piezoelectric layer adjacent to the second conductive layer is separated from the second conductive layer by a second gap. In some implementations, the resonator structure further includes an encapsulation layer arranged over the second conductive layer and providing physical support to the second conductive layer. | 09-12-2013 |
20130293337 | HIGH QUALITY FACTOR PLANAR INDUCTORS - This disclosure provides systems, methods, and apparatus related to inductors. In one aspect, a planar inductor may include a substrate with a spacer in the shape of a planar spiral coil on a surface of the substrate. Disposed on the spacer may be a line of metal formed as a planar inductor in the shape of the planar spiral coil. The spacer may be between the line of metal and the surface of the substrate. The spacer may elevate the line of metal above the surface of the substrate. | 11-07-2013 |
20140028543 | COMPLEX PASSIVE DESIGN WITH SPECIAL VIA IMPLEMENTATION - This disclosure provides systems, methods and apparatus for vias in an integrated circuit structure such as a passive device. In one aspect, an integrated passive device includes a first conductive trace and a second conductive trace over the first conductive trace with an interlayer dielectric between a portion of the first conductive trace and the second conductive trace. One or more vias are provided within the interlayer dielectric to provide electrical connection between the first conductive trace and the second conductive trace. A width of the vias is greater than a width of at least one of the conductive traces. | 01-30-2014 |
20140035702 | HYBRID FILTER INCLUDING LC- AND MEMS-BASED RESONATORS - This disclosure provides implementations of filters and filter topologies, circuits, structures, devices, apparatus, systems, and related processes. In one aspect, a device includes one or more LC resonant circuit stages. In some implementations, each LC stage includes an inductor and a capacitor. Each LC stage also has a corresponding resonant frequency. The one or more LC stages are arranged to produce an unmodified passband over a range of frequencies having a corresponding bandwidth. One or more microelectromechanical systems (MEMS) resonators are arranged with the one or more LC stages. The one or more MEMS resonators are arranged with the one or more LC stages so as to modify characteristics of the unmodified passband such that the hybrid filter produces a modified passband having a modified bandwidth and one or more other modified band characteristics. | 02-06-2014 |
20140247269 | HIGH DENSITY, LOW LOSS 3-D THROUGH-GLASS INDUCTOR WITH MAGNETIC CORE - This disclosure provides systems, methods and apparatus for three-dimensional (3-D) through-glass via inductors. In one aspect, the through-glass via inductor includes a glass substrate with a first cavity, a second cavity, and at least two through-glass vias. The through-glass vias include metal bars that are connected by a metal trace. The metal bars and the metal trace define the inductor, and each cavity is at least partially filled with magnetic material. The magnetic material can include a plurality of particles having an average diameter of less than about 20 nm. The first cavity can be inside the inductor and the second cavity can be outside inductor. In some implementations, the first and the second cavity can be vias that extend only partially through the glass substrate. | 09-04-2014 |
20140361854 | COMPACT 3-D COPLANAR TRANSMISSION LINES - This disclosure provides systems, methods and apparatus for a compact 3-D coplanar transmission line (CTL). In one aspect, the CTL has a proximal end and a distal end separated, in a first plane, by a distance D, the first plane being parallel to a layout area of a substrate. The plane is defined by mutually orthogonal axes x and z The CTL provides a conductive path having pathlength L. D is substantially aligned along axis z, L is at least 1.5×D, and the CPW is configured such that at least one third of the pathlength L is disposed along one or more directions having a substantial component orthogonal to the first plane. Less than one third of the pathlength L is disposed in a direction having a substantial component parallel to axis x. | 12-11-2014 |
20150287677 | STRESS MITIGATION STRUCTURE FOR WAFER WARPAGE REDUCTION - An integrated circuit device includes a substrate. The integrated circuit device also includes a first conductive stack including a back-end-of-line (BEOL) conductive layer at a first elevation with reference to the substrate. The integrated circuit device also includes a second conductive stack including the BEOL conductive layer at a second elevation with reference to the substrate. The second elevation differs from the first elevation. | 10-08-2015 |
20150304059 | FREQUENCY MULTIPLEXER - An apparatus is disclosed that includes a frequency multiplexer circuit coupled to an input node and configured to receive an input signal via the input node. The frequency multiplexer circuit comprises a first filter circuit, a second filter circuit, and a third filter circuit. The apparatus also includes a switching circuit that is configurable to couple at least two of a first output of the first filter circuit, a second output of the second filter circuit, or a third output of the third filter circuit to a single output port. | 10-22-2015 |
Patent application number | Description | Published |
20120092169 | METHOD OF ASSESSING HUMAN FALL RISK USING MOBILE SYSTEMS - A method for determining the motive instability of an individual using foot pressure, foot speed and foot direction data collected from sensors on shoes. The sensed data is used to determine the minimum number and the placement of pressure sensors in the shoe. The data from the sensors is processed to extract spatial and temporal parameters as desired. The data is grouped into segments based on a segmentation rule. The trend in each segment is determined. The variability of the trend in each segment is determined. The risk of fall is computed on the basis of the trend and variance. The computation is adjustable by emphasizing certain parameters in order to tailor the instability assessment to a specific individual. | 04-19-2012 |
20140344208 | CONTEXT-AWARE PREDICTION IN MEDICAL SYSTEMS - A method includes receiving contextual data related to at least one of environmental, physiological, behavioral, and historical context, and receiving outcome data related to at least one outcome. The method further includes creating a feature set from the contextual data, selecting a subset of features from the feature set, assigning a score to each feature in the subset of features according to the probability that the feature is a predictor of the at least one outcome, and generating a characteristic curve for the at least one outcome from the subset of features, the characteristic curve being based on the scoring. The method further includes calculating the area under the characteristic curve, and using, the area under the characteristic curve, identifying whether the subset of features is a suitable predictor for the at least one outcome. | 11-20-2014 |
20140379620 | SYSTEMS AND METHODS FOR AUTOMATIC SEGMENT SELECTION FOR MULTI-DIMENSIONAL BIOMEDICAL SIGNALS - Systems and methods for automatically analyzing and selecting prominent channels from multi-dimensional biomedical signals in order to detect particular diseases or ailments are provided. Such systems and methods may be applied in different ways to obtain numerous benefits, such as lowering of power and processing requirements, reducing an amount of data acquired, simplifying hardware deployment, detecting non-trivial patterns, obtaining, clinical episode prognosis, improving patient care, and/or the like. | 12-25-2014 |
20150234997 | TASK OPTIMIZATION IN REMOTE HEALTH MONITORING SYSTEMS - Systems, methods, and devices are disclosed that monitor the health status of patients. Dynamic task management functions apply data analytics to discretize continuous data values from monitored patients, and apply association rule mining techniques to prioritized required user tasks. Embodiments of the present disclosure minimize the number of daily action items required by patients. The remaining action items maximize information gain, thereby improving the overall level of patient adherence and satisfaction without losing health monitoring effectiveness. | 08-20-2015 |
20150257712 | METHODS AND SYSTEMS FOR CALCULATING AND USING STATISTICAL MODELS TO PREDICT MEDICAL EVENTS - Systems and methods for generalized precursor pattern discovery that work with a wide range of biomedical signals and applications to detect a wide range of medical events are disclosed. In some embodiments, the methods and systems do not require domain-specific knowledge or significant reconfiguration based on the medical event being analyzed, hence it is also possible to discover patterns previously unknown to experts. In some embodiments, to build precursor pattern detection models, the system obtains annotated monitoring data. Positive and negative segments are extracted from the annotated monitoring data, and are preprocessed. Features are extracted from the preprocessed segments, and selected features are chosen from the extracted features. The selected features are classified to create the precursor pattern detection model The precursor pattern detection model may then be used in real time to detect occurrences of the medical event of interest. | 09-17-2015 |
Patent application number | Description | Published |
20080265240 | Memory device with improved performance - The present resistive memory device includes first and second electrodes. An active layer is situated between the first and second electrodes. The active layer with advantage has a thermal conductivity of 0.02 W/Kcm or less, and is surrounded by a body in contact with the layer, the body having a thermal conductivity of 0.01 W/Kcm or less. | 10-30-2008 |
20120081947 | METAL-INSULATOR-METAL-INSULATOR-METAL (MIMIM) MEMORY DEVICE - The present memory device includes first and second electrodes, first and second insulating layers between the electrodes, the first insulating layer being in contact with the first electrode, the second insulating layer being in contact with the second electrode, and a metal layer between the first and second insulating layers. Further included may be a first oxide layer between and in contact with the first insulating layer and the metal layer, and a second oxide layer between and in contact with the second insulating layer and the metal layer. | 04-05-2012 |
20120127779 | Re-writable Resistance-Switching Memory With Balanced Series Stack - A re-writable resistance-switching memory cell includes first and second capacitors in series. The first and second capacitors may have balanced electrical characteristics to allow nearly concurrent, same-direction switching. The first capacitor has a first bipolar resistance switching layer between first and second conductive layers, and the second capacitor has a second bipolar resistance switching layer between third and fourth conductive layers. The first and third conductive layers are made of a common material, and the second and fourth conductive layers are made of a common material. In one approach, the first and second bipolar resistance switching layers are made of a common material and have common thickness. In another approach, the first and second bipolar resistance switching layers are made of materials having different dielectric constants, but their thickness differs in proportion to the difference in the dielectric constants, to provide a common capacitance per unit area. | 05-24-2012 |
20120195097 | METHOD AND SYSTEM FOR UTILIZING PEROVSKITE MATERIAL FOR CHARGE STORAGE AND AS A DIELECTRIC - A memory device is disclosed. In a first aspect the memory comprises a first doped awell; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovsite material on top of the first doped well and located between two bitlines; and a wordline located above the Perovskite material. In a second aspect the memory comprises a first doped well; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovskite material located within one of the bitlines and a wordline located above the first doped well and located between the two bitlines. | 08-02-2012 |
20120195098 | METHOD AND SYSTEM FOR UTILIZING PEROVSKITE MATERIAL FOR CHARGE STORAGE AND AS A DIELECTRIC - A memory device is disclosed. In a first aspect the memory comprises a first doped awell; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovsite material on top of the first doped well and located between two bitlines; and a wordline located above the Perovskite material. In a second aspect the memory comprises a first doped well; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovskite material located within one of the bitlines and a wordline located above the first doped well and located between the two bitlines. | 08-02-2012 |
20130094278 | Non-Volatile Memory Cell Containing an In-Cell Resistor - A non-volatile memory cell includes a first electrode, a steering element, a metal oxide storage element located in series with the steering element, a dielectric resistor located in series with the steering element and the metal oxide storage element, and a second electrode. | 04-18-2013 |
20130170283 | LOW FORMING VOLTAGE NON-VOLATILE STORAGE DEVICE - A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are provided across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that the bit line acts as a cathode and the word line acts as an anode, with the cathode having a lower electron injection energy barrier to the switching material than the anode. | 07-04-2013 |
20130279236 | METHOD AND SYSTEM FOR UTILIZING PEROVSKITE MATERIAL FOR CHARGE STORAGE AND AS A DIELECTRIC - Memory devices and methods for providing the memory devices are provided. The memory devices utilize multiple metal oxide layers. The methods for providing the memory devices can include providing a transistor; producing a capacitor that includes metal layers and metal oxide layers; connecting the capacitor to a side of the transistor; and providing a wordline, bitline, and driveline through connection with the transistor or the capacitor. | 10-24-2013 |
20130292634 | RESISTANCE-SWITCHING MEMORY CELLS HAVING REDUCED METAL MIGRATION AND LOW CURRENT OPERATION AND METHODS OF FORMING THE SAME - In some aspects, a memory cell is provided that includes a steering element, a metal-insulator-metal (“MIM”) stack coupled in series with the steering element, and a conductor above the MIM stack. The MIM stack includes a resistance switching element and a top electrode disposed on the resistance switching element, and the top electrode includes a highly doped semiconductor material. The memory cell does not include a metal layer between the MIM stack and the conductor. Numerous other aspects are provided. | 11-07-2013 |
20140233299 | Set/Reset Algorithm Which Detects And Repairs Weak Cells In Resistive-Switching Memory Device - A resistance-switching memory cell is programmed in a set or reset operation which tests the stability of the cell. A first programming phase using program voltages which increase in magnitude or duration until a program verify test is passed. A stability test phase is then performed to evaluate a stability of the memory cell. The stability test phase determines whether the memory cell is weak and likely to transition out of the set or reset state by applying one or more disturb pulses and performing one or more stability verify tests. The disturb pulses can have a reduced magnitude or duration compared to the program voltages. If the stability test phase indicates the memory cell is not stable, a second programming phase is performed. If the stability test phase indicates the memory cell is stable, the operation is concluded. | 08-21-2014 |