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Laisne
Jean-Yves Laisne, Verrieuil-En-Halatte FR
| Patent application number | Description | Published |
|---|---|---|
| 20110293478 | DEVICE FOR REDUCING EVAPORATION IN A REAGENT BOTTLE - A device reducing evaporation in a reagent bottle, in particular in an automatic appliance for analyzing samples, the device being in the form of a tube inserted into the bottle and including, in its top portion, an annular rim for bearing on the top end of the neck of the bottle, and means for centering in the neck of the bottle. | 12-01-2011 |
Michael Laisne, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100060310 | Systems and Methods Utilizing Redundancy in Semiconductor Chip Interconnects - An integrated circuit, or combination of integrated circuits, has a primary interconnect, a redundant interconnect, and circuitry connecting the primary and redundant interconnects allowing selection of the redundant interconnect to bypass the primary interconnect. | 03-11-2010 |
| 20100141286 | INTEGRATED CIRCUIT WITH IMPROVED TEST CAPABILITY VIA REDUCED PIN COUNT - An integrated circuit that supports testing of multiple pads via a subset of these pads includes at least two sections. Each section has multiple pads and multiple test access circuits coupled to these pads. For each section, one pad is designated as a primary pad and the remaining pads are designated as secondary pads. For each section, the test access circuits couple the secondary pads to the primary pad such that all of the pads in the section can be tested by probing just the primary pad. Each test access circuit may be implemented with a simple switch. A controller generates a set of control signals for the test access circuits in all sections. These control signals enable and disable the test access circuits such that all of the sections can be tested in parallel, and the pads in each section can be tested in a sequential order. | 06-10-2010 |
| 20110164808 | TECHNIQUES PROVIDING FIDUCIAL MARKERS FOR FAILURE ANALYSIS - A semiconductor die includes a group of spacer cells within the semiconductor die. The spacer cells include fiducial markings therein. The fiducial markings can be located within a metal layer, a diffusion layer, a polysilicon layer, and/or a Shallow Trench Isolation (STI) structure. | 07-07-2011 |
Michael Laisne, Encinitas, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090206868 | METHODOLOGIES AND TOOL SET FOR IDDQ VERIFICATION, DEBUGGING AND FAILURE DIAGNOSIS - Quiescent supply current (I | 08-20-2009 |
| 20110231720 | DATA RECIRCULATION IN CONFIGURED SCAN PATHS - An Automated Test Equipment (ATE) system is configured to test a Device Under Test (DUT). The ATE system stores a Procedure Description Language program. The ATE system interprets the program, thereby causing a configured scan path to be set up in the DUT and causing bit values to be loaded into that scan path. During testing, it is sometimes desirable to change only bit values in certain scan path bit locations. In a data recirculation operation, the ATE system shifts bit values, on a bit-by-bit basis, out of the configured scan path via the TDO terminal of the DUT and shifts back in either the shifted out bit value or a replacement bit value. The shift back into the configured scan path occurs via the TDI terminal of the DUT so that each bit value in the scan path is replaced with its previous value or a replacement value. | 09-22-2011 |
| 20110270548 | AUTOMATED VERIFICATION AND ESTIMATION OF QUIESCENT POWER SUPPLY CURRENT - Procedures are disclosed to automate constraint and power mode (PM) setup determination for quiescent power supply current (I | 11-03-2011 |