| Patent application number | Description | Published |
|---|
| 20080246142 | Heat dissipation unit and a semiconductor package that has the heat dissipation unit - A heat dissipation unit and a semiconductor package having the same are disclosed. The semiconductor package includes a carrier; an electronic component mounted on and electrically connected to the carrier; a heat dissipation unit, which includes a flat section attached to the electronic component, extension sections connected to the flat section, and a heat dissipation section connected to the extension sections; and an encapsulant encapsulating the electronic component and the heat dissipation unit, wherein stress releasing sections are at least disposed at intersectional corners between the extension sections and the flat section so as to prevent projections from being formed by concentrated stresses in a punching process of the heat dissipation unit, thereby maintaining flatness of the flat section and further preventing circuits of the electronic component from being damaged due to a contact point produced between the electronic component and the flat section in a molding process. | 10-09-2008 |
| 20080277786 | Semiconductor package substrate - A semiconductor package substrate includes a body having an upper surface and a lower surface opposite to one another, a plurality of circuit layers formed in the body, a plurality of solder pads formed on the upper surface of the body, and a plurality of solder ball pads formed on the lower surface of the body. Each of the solder pads is electrically connected to one of the solder ball pads via the circuit layers and conductive structures disposed between the circuit layers, wherein the circuit layers and conductive structures are configured to expand outwardly in a fan-out manner so as to provide more space between the circuit layers closer to the lower surface of the body such that part of the solder pad-solder ball pad electrical connections can comprise a plurality of parallel connected conductive structures formed in the space, thereby enhancing the heat conducting passageway and the effect of heat-dissipation without having to dispose more solder pads on surface of the substrate. | 11-13-2008 |
| 20080303134 | Semiconductor package and method for fabricating the same - A semiconductor package and a method for fabricating the same are disclosed, which includes: providing a carrier board, forming a plurality of metal bumps on the carrier board, forming a metal layer on the carrier board to encapsulate the metal bumps, having at least one semiconductor chip electrically connected to the metal layer, then forming an encapsulant on the carrier board to encapsulate the semiconductor chip, and next removing the carrier board and the metal bumps to correspondingly form a plurality of grooves on surface of the encapsulant, wherein bottom and sides of the grooves are covered with the metal layer to allow electroconductive components to be effectively positioned in the grooves and completely bonded with the metal layer. | 12-11-2008 |
| 20090008801 | Semiconductor device and method for fabricating the same - This invention discloses a semiconductor device and a method for fabricating the same. The method includes providing a flexible carrier board having a first surface and a second surface opposite thereto; forming a metal lead layer and a first heat dissipating metal layer on the first surface of the flexible carrier board, and forming a second heat dissipating metal layer on the second surface of the flexible carrier board; providing a chip having an active surface and an opposed non-active surface, wherein a plurality of solder pads are formed on the active surface of the chip, each of the solder pads has a metal bump formed thereon and corresponding in position to the metal lead layer, and heat dissipating bumps are formed between the metal bumps corresponding in position to the first heat dissipating metal layer. | 01-08-2009 |
| 20090283303 | PACKAGE SUBSTRATE HAVING LANDLESS CONDUCTIVE TRACES - A package substrate having landless conductive traces is proposed, which includes a core layer with a plurality of plated through holes formed therein, and a plurality of conductive traces formed on at least a surface of the core layer. Each of the conductive traces has a connection end, a bond pad end, and a base body connecting the connection end and the bond pad end, the conductive trace is electrically connected to a corresponding one of the plated through holes through the connection end, and the connection end has a width greater than that of the base body but not greater than the diameter of the plated through hole, thereby increasing the contact area between the conductive trace and the plated through hole and preventing the contact surface of the conductive trace with the plated through hole from cracking. | 11-19-2009 |
