Lai, Singapore
Aaric Chee Meng Lai, Singapore SG
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20080319936 | Engineering expert system - An expert system aids engineering personnel working in a manufacturing or other industrial environment by answering questions relating to machines, processes, systems or other elements of the environment. Users can interact with the system using kiosks in the relevant areas of the plant to enter queries and receive answers. A user can enter a query in a natural language format, which the system parses for keywords or keyterms. The system can use a backward chaining method to reach a solution, based upon the user's answer to further questions that the system asks the user. | 12-25-2008 |
Chee Keen Lai, Singapore SG
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20150182114 | Imager for Medical Device - A system for transmitting a temperature of a patient to an electronic medical record associated with the patient includes a thermometer with a digital display that is configured to display a temperature value associated with the temperature signal and at least one error-checking value. The system also includes a handheld imaging device including a camera to capture an image of the digital display of the thermometer, a processor to extract the text in the image using optical character recognition, and perform an error-check on the temperature value using the at least one error-checking value in the image, and to transmit the patient's identification number and temperature to an electronic medical record system. | 07-02-2015 |
Choon Lee Lai, Singapore SG
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20140293120 | CONTACT HAVING AN ANGLED PORTION - Described herein are various embodiments of contacts that include different portions angled with respect to one another and methods of manufacturing devices that include such contacts. In some embodiments, a module may include a first portion of a contact that is disposed within a housing and a second portion that is disposed outside of the housing, with the second portion angled with respect to the first portion. Manufacturing such devices may include depositing a conductive material to electrically connect the contact to a contact pad of a substrate. In some embodiments, a deposition process for depositing the conductive material may have a minimum dimension, which defines a minimum dimension of a conductive material once deposited. In some such embodiments, a distance between a terminal end of the contact pin and the contact pad may be greater than the minimum dimension of the deposition process. | 10-02-2014 |
Da-Wei Lai, Singapore SG
Patent application number | Description | Published |
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20130187218 | ESD PROTECTION CIRCUIT - A device which includes a substrate defined with a device region having an ESD protection circuit is disclosed. The ESD protection circuit has a transistor. The transistor includes a gate having first and second sides. A first diffusion region is disposed adjacent to the first side of the gate and a second diffusion region is disposed in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. A drift isolation region is disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. A drain well having dopants of the first polarity type is disposed under the second diffusion region and within the first device well. | 07-25-2013 |
20130187231 | ESD PROTECTION CIRCUIT - A device having a substrate defined with a device region which includes an ESD protection circuit is disclosed. The ESD protection circuit has first and second transistors. A transistor includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, and a second diffusion region in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. The device includes a first device well which encompasses the device region and second device wells which are disposed within the first device well. A well contact is coupled to the second device wells. The well contact surrounds the gates of the transistors and abuts the first diffusion regions of the transistors. | 07-25-2013 |
20130207179 | ESD PROTECTION CIRCUIT - A device which includes a substrate defined with a device region with an ESD protection circuit having at least first and second transistors is disclosed. Each of the transistors includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, a second diffusion region in the device region displaced away from the second side of the gate, and a drift isolation region disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. The device also includes a drift well which encompasses the second diffusion region. Edges of the drift well do not extend below the gate and is away from a channel region. A drain well is disposed under the second diffusion region and within the drift well. | 08-15-2013 |
20130222950 | LATCH UP DETECTION - A device is presented. The device includes a first circuit coupled to first and second power rails of the device. The first circuit is subject to a latch up event in the presence of a latch up condition. The latch up event includes a low resistance path created between the first and second power rails. The device also includes a latch up sensing (LUS) circuit coupled to the first circuit. The LUS circuit is configured to receive a LUS input signal from the first circuit and generates a LUS output signal to the first circuit. When the input signal is an active latch up signal which indicates the presence of a latch up condition, the LUS circuit generates an active LUS output signal which creates a break in the low resistance path to terminate the latch up event. | 08-29-2013 |
20130222952 | ESD PROTECTION WITHOUT LATCH-UP - A device having an ESD module is disclosed. The ESD module includes an ESD circuit coupled between first and second rails and a control circuit coupled between the rails and to the ESD circuit. When the control circuit senses an ESD event, it causes the ESD circuit to create a current path between the rails to dissipate ESD current. When no ESD event is sensed, the control circuit ensures that no current path is created between the rails to prevent latch-up. | 08-29-2013 |
20130235496 | ESD-ROBUST I/O DRIVER CIRCUITS - An ESD-robust I/O driver circuit is disclosed. Embodiments include providing a first NMOS transistor having a first source, a first drain, and a first gate; coupling the first source to a ground rail and the first drain to an I/O pad; coupling a gate driver control circuit to the first drain and the first gate; and providing a ground potential to the first gate, via the gate driver control circuit, during an ESD event occurring from the I/O pad to the ground rail. | 09-12-2013 |
20130235498 | CROSS-DOMAIN ESD PROTECTION SCHEME - A cross-domain ESD protection scheme is disclosed. Embodiments include coupling a first power clamp to a first power rail and a first ground rail; providing a first NMOS transistor having a first source, a first drain, and a first gate; coupling the first source to a second ground rail; providing a first PMOS transistor having a second source, a second drain, and a second gate; coupling the second source to the first power rail; and providing, via the first power clamp, a signal to turn on the first NMOS transistor during an ESD event that occurs at the first power rail. | 09-12-2013 |
20130265676 | POWER CLAMP FOR HIGH VOLTAGE INTEGRATED CIRCUITS - A clamp circuit includes both nmos and pmos devices connected in series between a voltage source terminal, such as an integrated circuit pad, and ground. A trigger unit, connected between the voltage source and ground, includes a plurality of output terminals coupled to the clamp circuit. The trigger unit is responsive to a voltage threshold, such as caused by an ESD occurrence, between the voltage source and ground to apply clamping signals at its output terminals to couple the voltage source terminal to ground through both nmos and pmos devices. | 10-10-2013 |
20130279052 | ESD PROTECTION DEVICE WITH A TUNABLE HOLDING VOLTAGE FOR A HIGH VOLTAGE PROGRAMMING PAD - An ESD protection device with a tunable holding voltage is disclosed. Embodiments include: providing a silicon-controlled rectifier (SCR) having a first n-type layer with a cathode connection, a first p-type layer with a first control connection, a second n-type layer with a second control connection, and a second p-type layer with an anode connection; coupling the anode connection to a power rail; coupling the cathode connection to a ground rail; providing a tunable holding voltage control unit including a first NMOS having a first gate, a first drain, and a first source, wherein during an ESD event, the first NMOS is turned off and a holding voltage of the SCR is low; coupling the first drain to the first control connection; coupling the first source to the ground rail; and coupling the first gate to a program circuit. | 10-24-2013 |
20130286516 | GATE DIELECTRIC PROTECTION - Protecting a gate dielectric is achieved with a gate dielectric protection circuit coupled to a transistor at risk. The protection circuit is activated to reduce the voltage across the gate dielectric (V | 10-31-2013 |
20130308231 | ESD PROTECTION FOR HIGH VOLTAGE APPLICATIONS - An ESD module includes an ESD circuit coupled between a first source and a second source. A trigger circuit is also included in the ESD module for activating the ESD circuit to provide a low resistance current path between the first and second sources. The trigger circuit includes a reverse diode between the first source and the ESD circuit or between the second source and main ESD circuit. The trigger circuit provides a low trigger voltage to activate the ESD circuit. | 11-21-2013 |
20130320398 | LATCH-UP ROBUST SCR-BASED DEVICES - An approach for providing a latch-up robust silicon control rectifier (SCR) is disclosed. Embodiments include providing a first N+ region and a first P+ region in a substrate for a SCR; providing first and second n-well regions in the substrate proximate the first N+ and P+ regions; providing a second N+ region in the first n-well region, and a second P+ region in the second n-well region; and coupling the first N+ and P+ regions to a ground rail, the second N+ region to a power rail, and the second P+ region to an I/O pad. | 12-05-2013 |
20130321961 | ESD PROTECTION DEVICE FOR CIRCUITS WITH MULTIPLE POWER DOMAINS - A ESD protection scheme is disclosed for circuits with multiple power domains. Embodiments include: coupling a first power clamp to a first power rail and a first ground rail of a first domain; coupling a second power clamp to a second power rail and a second ground rail of a second domain; providing a blocking circuit for blocking current from an ESD event; providing an I/O interface connection in the first domain for transmitting signals from the first domain to the blocking circuit; providing a core interface connection in the second domain for transmitting signals from the blocking circuit to the second domain; coupling an input connection of the blocking circuit to the I/O interface connection; and coupling an output connection of the blocking circuit to a core interface connection. | 12-05-2013 |
20130321962 | ESD-ROBUST I/O DRIVER CIRCUITS - An ESD-robust I/O driver circuit is disclosed. Embodiments include providing a first NMOS transistor having a first source, a first drain, and a first gate; coupling the first source is coupled to a ground rail, and the first drain to an I/O pad; providing a gate driver control circuit including a second NMOS transistor having a second source, a second drain, and a second gate; and coupling the second drain to the first gate, the second source to the ground rail, wherein the gate driver control circuit provides a ground potential to the first gate during an ESD event occurring from the I/O pad to the ground rail. | 12-05-2013 |
20130321963 | ESD PROTECTION CIRCUIT - An ESD circuit is disclosed. The ESD circuit includes a pad and a ground and a sensing element coupled between the pad and ground for sensing an ESD current. The sensing element generates an active sense output signal when an ESD current is sensed and an inactive sense output signal when no ESD current is sensed. The ESD circuit also includes a bypass element comprising a bi-polar junction transistor. The bypass element is coupled in parallel to the sensing element between the pad and ground. The active sense output signal causes the bypass element to be activated to provide a current path between the pad and ground. | 12-05-2013 |
20130341675 | LATCH-UP FREE ESD PROTECTION - An ESD module having a first portion (FP) and a second portion (SP) in a substrate is presented. The FP includes a FP well of a second polarity type and first and second FP contact regions. The first FP contact region is of a first polarity type and the second FP contact region is of a second polarity type. The SP includes a SP well of a first polarity type and first and second SP contact regions. The first SP contact region is of a first polarity type and the second SP contact region is of a second polarity type. An intermediate portion (IP) is disposed in the substrate between the FP and SP in the substrate. The IP includes a well of the second polarity type. The IP increases trigger current and holding voltage of the module to prevent latch up during normal device operation. | 12-26-2013 |
20140002934 | LATCH-UP IMMUNE ESD PROTECTION | 01-02-2014 |
20140049313 | LATCH-UP ROBUST PNP-TRIGGERED SCR-BASED DEVICES - An approach for providing a latch-up robust PNP-triggered SCR-based device is disclosed. Embodiments include providing a silicon control rectifier (SCR) region; providing a PNP region having a first n-well region proximate the SCR region, a first N+ region and a first P+ region in the first n-well region, and a second P+ region between the SCR region and the first n-well region; coupling the first N+ region and the first P+ region to a power rail; and coupling the second P+ region to a ground rail. | 02-20-2014 |
20140054696 | NOVEL LATCH-UP IMMUNITY NLDMOS - An improved nLDMOS ESD protection device having an increased holding voltage is disclosed. Embodiments include: providing in a substrate a DVNW region; providing a HVPW region in the DVNW region; providing bulk and source regions in the HVPW region; providing a drain region in the DVNW region, separate from the HVPW region; and providing a polysilicon gate over a portion of the HVPW region and the DVNW region. | 02-27-2014 |
20140084366 | ESD PROTECTION CIRCUIT - A device having a substrate defined with a device region is presented. The device region includes an ESD protection circuit having a transistor. The transistor includes a gate having first and second sides, a first diffusion region adjacent to the first side of the gate and a second diffusion region displaced away from the second side of the gate. The device includes a first device well which encompasses the device region and a second device well disposed within the first device well. The device further includes a drift well which encompasses the second diffusion region of which edges of the drift well do not extend below the gate and is away from a channel region, and a drain well which is disposed under the second diffusion region and extends below the gate. | 03-27-2014 |
20140160604 | LATCH-UP FREE RC-BASED NMOS ESD POWER CLAMP IN HV USE - An RC-based electrostatic discharge protection device provides an extended snapback trigger voltage range, thereby avoiding latch-up. Two parallel current discharge paths are provided between supply terminals during an electrostatic discharge event by virtue of an added external resistor. The first current discharge path includes body resistance of the protection device and the second current discharge path includes the external resistor. | 06-12-2014 |
20140160605 | HIGH NOISE IMMUNITY WITH LATCH-UP FREE ESD CLAMP - A triple stack NMOS integrated circuit structure protection circuit for a plurality of terminals operative at respective voltage levels is coupled between the plurality of terminals. First and second NMOS elements of the triple stack NMOS share a common active region. A third NMOS element, vertically positioned with respect to the first and second NMOS elements, has an active region separate from the active region of the first and second NMOS elements. The first, second and third NMOS elements are connected in series between two terminals of the plurality of terminals. | 06-12-2014 |
20140247526 | FALSE-TRIGGERED IMMUNITY AND RELIABILITY-FREE ESD PROTECTION DEVICE - An acceptable voltage margin between a voltage level for triggering electrostatic current discharge and a voltage level for programming operation of an OTP device is determined. Activation of an ESD protection circuit is controlled in part in response to a false trigger prevention circuit. To avoid gate oxide breakdown that may occur with a MOSFET protection device used for higher voltage requirements of an OTP device, the ESD protection circuit employs a bipolar transistor. | 09-04-2014 |
20140264556 | ESD PROTECTION CIRCUIT - A device having a substrate defined with a device region is presented. The device region includes an ESD protection circuit having a transistor. The transistor includes a gate having first and second sides, a first diffusion region disposed adjacent to the first side of the gate and a second diffusion region displaced away from the second side of the gate. The device includes a first device well encompasses the device region and a second device well disposed within the first device well. The second device well encompasses the first diffusion region and at least a part of the gate. The device also includes a third well which is disposed within the second device well and a drain well which encompasses the second diffusion region and extends below the gate. | 09-18-2014 |
20150236006 | NOVEL LATCH-UP IMMUNITY NLDMOS - An improved nLDMOS ESD protection device having an increased holding voltage is disclosed. Embodiments include: providing in a substrate a DVNW region; providing a HVPW region in the DVNW region; providing bulk and source regions in the HVPW region; providing a drain region in the DVNW region, separate from the HVPW region; and providing a polysilicon gate over a portion of the HVPW region and the DVNW region. | 08-20-2015 |
20150340481 | LATCH-UP ROBUST SCR-BASED DEVICES - An approach for providing a latch-up robust silicon control rectifier (SCR) is disclosed. Embodiments include providing a first N+ region and a first P+ region in a substrate for a SCR; providing first and second n-well regions in the substrate proximate the first N+ and P+ regions; providing a second N+ region in the first n-well region, and a second P+ region in the second n-well region; and coupling the first N+ and P+ regions to a ground rail, the second N+ region to a power rail, and the second P+ region to an I/O pad. | 11-26-2015 |
Fon Lin Lai, Singapore SG
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20110295857 | SYSTEM AND METHOD FOR ALIGNING AND INDEXING MULTILINGUAL DOCUMENTS - A system and method for aligning multilingual content and indexing multilingual documents, to a computer readable data storage medium having stored thereon computer code means for indexing multilingual documents, to a system for presenting multilingual content. The method for aligning multilingual content and indexing multilingual documents comprises the steps of generating multiple bilingual terminology databases, wherein each bilingual terminology database associates respective terms in a pivot language with one or more terms in another language; and combining the multiple bilingual terminology databases to form a multilingual terminology database, wherein the multilingual terminology database associates terms in different languages via the pivot language terms. | 12-01-2011 |
Gai Leong Lai, Singapore SG
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20110108969 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a die paddle, having paddle projections along a paddle peripheral side; forming a lead terminal having a lead extension with the lead extension extending towards the paddle peripheral side and between the paddle projections; mounting an integrated circuit over the die paddle; connecting the integrated circuit and the lead extension; and forming an encapsulation over the die paddle and covering the integrated circuit and lead extension. | 05-12-2011 |
Hing Tim Lai, Singapore SG
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20080246958 | Multiple surface inspection system and method - A system for inspecting components is provided. The system includes a prism having a first end, a second end, a first reflecting surface, and a second reflecting surface. The first end of the prism is located in a plane that is parallel to and axially separated from a plane of one or more of a plurality of inspection pieces. An image data system is disposed beyond the second end of the prism and generates image data of one or more of the inspection piece that includes a top surface of at least one of the inspection pieces and at least one side of at least one of the inspection pieces. An inspection piece transportation system, such as a pick and place tool or conveyor, moves a plurality of inspection pieces past the first end of the prism through an inspection area. | 10-09-2008 |
20090073426 | Multiple Surface Inspection System and Method - A system for on-the-fly inspection of components is provided. The system includes a prism structure disposed below an inspection item transit path. An image data system is disposed below the prism structure. A lighting assembly provides a first lighting source to illuminate a plurality of sides of an inspection item and a second lighting source to illuminate a bottom of the inspection item. | 03-19-2009 |
Keng Heng Lai, Singapore SG
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20110032348 | DEFECT MONITORING IN SEMICONDUCTOR DEVICE FABRICATION - A method of forming a device is presented. The method includes providing a substrate containing at least a partially formed device thereon. The device comprises at least one defect site. A pixilated image of the defect site is acquired, and each pixel comprises a grey level value (GLV). Surrounding noises of the defect site is eliminated. A point of the image is identified as the center of the defect. A plurality of iterations to exclude outer edge pixels surrounding the center of the defect image is performed. The defect is categorized as a killer or non-killer defect. | 02-10-2011 |
Kuek Peow Lai, Singapore SG
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20130016403 | SYSTEM AND METHOD FOR SCANNINGAANM SOH; PHEY HONGAACI SingaporeAACO SGAAGP SOH; PHEY HONG Singapore SGAANM LAI; KUEK PEOWAACI SingaporeAACO SGAAGP LAI; KUEK PEOW Singapore SGAANM LEONG; SHYH CHIJEAACI SingaporeAACO SGAAGP LEONG; SHYH CHIJE Singapore SGAANM TAN; LIAN CHYE SIMONAACI SingaporeAACO SGAAGP TAN; LIAN CHYE SIMON Singapore SGAANM YAP; CHOON HWEEAACI SingaporeAACO SGAAGP YAP; CHOON HWEE Singapore SGAANM LIM; BOO SIONGAACI SingaporeAACO SGAAGP LIM; BOO SIONG Singapore SG - A scanner comprises a first gear assembly on a frame, a stationary scan surface having a first width, and a scan module having a length substantially less than the first width. The scan module includes a second gear assembly configured to move the scan module, in a first orientation generally perpendicular to the first width, in a first scanning path relative to a first width portion of the scan surface and in a second, non-duplicative scanning path relative to a second width portion of the scan surface. The second gear assembly is releasably engageable to the first gear assembly to selectively shift the scan module, in a second orientation generally perpendicular to the first orientation, between the respective first and second scanning paths. | 01-17-2013 |
20130016404 | SYSTEM AND METHOD FOR EDGE IDENTIFICATION TO POSITION COMPONENTS OF A SCANNERAANM YAP; CHOON HWEEAACI SingaporeAACO SGAAGP YAP; CHOON HWEE Singapore SGAANM TAN; LIAN CHYE SIMONAACI SingaporeAACO SGAAGP TAN; LIAN CHYE SIMON Singapore SGAANM LAI; KUEK PEOWAACI SingaporeAACO SGAAGP LAI; KUEK PEOW Singapore SG - A scanner includes a scan surface, a scan, a controller, and a positioning system. The scan surface is stationary and has a first width while the scan module has a second width substantially less than the first width. The controller is configured to automatically cause two scans of a media on the scan surface, without repositioning the media, and to automatically produce a composite image of the entire media from the two scans. The positioning system is in communication with the controller and includes an identification mechanism configured to identify an edge of a scanning area associated with the scan surface and to stop a position of the scan module at the identified edge. | 01-17-2013 |
Lee Wang Lai, Singapore SG
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20080280396 | STACKED DIE PACKAGE FOR PERIPHERAL AND CENTER DEVICE PAD LAYOUT DEVICE - An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device. An outer peripheral portion of the second semiconductor device overhangs both the first semiconductor device and the substrate. Discrete conductive elements are placed between the outer peripheral portion of the second semiconductor device and a second surface of the substrate. Intermediate portions of the discrete conductive elements pass outside of a side surface of the substrate. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed. | 11-13-2008 |
20110062583 | STACKED DIE PACKAGE FOR PERIPHERAL AND CENTER DEVICE PAD LAYOUT DEVICE - An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device. An outer peripheral portion of the second semiconductor device overhangs both the first semiconductor device and the substrate. Discrete conductive elements are placed between the outer peripheral portion of the second semiconductor device and a second surface of the substrate. Intermediate portions of the discrete conductive elements pass outside of a side surface of the substrate. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed. | 03-17-2011 |
Lim Kean Lai, Singapore SG
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20140077907 | TOOL AND METHOD FOR SWITCHING AN ELECTROMAGNETIC RELAY - A tool and method for switching an electromagnetic relay may be provided, whereby the tool comprises a switching member capable of moving between a first position and a second position along a path oriented to the relay; wherein movement of the switching member from the first position to the second position is capable of switching a switch state of the electromagnetic relay via a magnetic force exerted by the switching member. | 03-20-2014 |
Linfei Lai, Singapore SG
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20140087192 | CONDUCTING POLYMER/GRAPHENE-BASED MATERIAL COMPOSITES, AND METHODS FOR PREPARING THE COMPOSITES - A composite comprising a conducting polymer and a graphene-based material is provided. The composite includes a graphene-based material doped with nitrogen or having a nitrogen-containing species grafted thereon, and a conducting polymer arranged on the graphene-based material. Methods of preparing the composite, and electrodes formed from the composite are also provided. | 03-27-2014 |
Linke Lai, Singapore SG
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20140357878 | METHOD OF PRODUCING 5-HYDROXYMETHYLFURFURAL FROM CARBOHYDRATES - Disclosed herein is a process for preparing 5-hydroxymethylfurfural comprising the step of contacting a carbohydrate and a Brønsted acid in an alcoholic solvent comprising an alcohol selected from the group consisting of secondary alcohols, tertiary alcohols, aryl alcohols and combinations thereof under conditions to dehydrate the carbohydrate thereby forming a reaction product containing 5-hydroxymethylfurfural. | 12-04-2014 |
Man On Lai, Singapore SG
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20110229763 | CATHODE MATERIAL FOR A BATTERY WITH IMPROVED CYCLE PERFORMANCE AT A HIGH CURRENT DENSITY - A material for use in the cathode terminal of a battery that is made from a lithiated manganese oxide which is doped with ruthenium and optionally with a transition material and a method for the synthesis of the same. The material exhibits improved conductivity and cyclic performance at high current density (current density of 1470 mA/g and higher) and can be used in hybrid vehicles and other electronic devices due to its good cyclic performance at high current density and its relatively large capacity. | 09-22-2011 |
20120273717 | LiMPO4-based compositions of matter for cathodes for high-performance Li batteries | 11-01-2012 |
Poh San Lai, Singapore SG
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20120190036 | CLINICAL METHOD FOR GENOTYPING LARGE GENES FOR MUTATIONS THAT POTENTIALLY CAUSE DISEASE - A method of determining polymorphisms within a large gene comprising the steps of: (a) making a Whole-Genome Amplification (WGA) to obtain sufficient amounts of genetic templates for DNA analysis; (b) enriching the WGA sample with nested primers designed for the large gene; (c) using the enriched WGA sample for high resolution melt (HRM); and (d) detecting differential melt profiles during the transition from double strand to single strand with an increase in temperature wherein sequence point mutations within the gene affects the thermal stability and gives a different melt profile from the normal non-mutated gene sequence, and kits to carry out detection of the same. The method may further comprise the step of spiking the DNA being screened using DNA from a phenotypically normal individual in order to induce synthetic heterozygosity. The method in (d) may also work directly on genomic samples without WGA step if sufficient DNA material is present. | 07-26-2012 |
Poh Yoke Lai, Singapore SG
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20080279178 | PORT REDUCTION FOR VOICE OVER INTERNET PROTOCOL ROUTER - An apparatus and method for increasing available ports on a voice router is provided. A first gateway and a second gateway are assigned a single port number for a data stream, the direction of packet flow is identified to determine a destination gateway. The destination gateway is one of the first and second gateways, depending on the direction of the packet flow. The packets are then forwarded to the destination gateway. The voice router can further consolidate RTCP streams from a plurality of gateways into a single port on the voice router. | 11-13-2008 |
Ruenn Chai Lai, Singapore SG
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20130209528 | USE OF EXOSOMES TO PROMOTE OR ENHANCE HAIR GROWTH - We describe the use of an exosome for the preparation of a pharmaceutical composition to promote or enhance would healing or hair growth, or both, in an individual. The exosome may be derived from a stem cell such as a mesenchymal stem cell (MSC). | 08-15-2013 |
20150024011 | USE OF EXOSOMES TO PROMOTE OR ENHANCE HAIR GROWTH - We describe the use of an exosome for the preparation of a pharmaceutical composition to promote or enhance would healing or hair growth, or both, in an individual. The exosome may be derived from a stem cell such as a mesenchymal stem cell (MSC). | 01-22-2015 |
Sep Riang Lai, Singapore SG
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20160000640 | GARMENT FOR TREATING SENSORY DISORDER - A garment comprising: at least two compartments, at least two air bladders within the compartments configured to constrict the torso of a user, a sensor configured to detect the pressure in the air bladders, and a controller configured communicate with a mobile device app to allow a user independently control of the pressure in each air bladder according to predetermined criteria. | 01-07-2016 |
Siew Kong Lai, Singapore SG
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20100241031 | Analyte Test Device Integral With Lancet Firing Mechanism - The present invention provides an analyte test device ( | 09-23-2010 |
Soo Chen Lai, Singapore SG
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20110243361 | SPEAKER SYSTEM - A loudspeaker device includes an enclosure, a loudspeaker unit and a passive radiator both mounted to the enclosure. The passive radiator includes an edge sandwiched and bonded between a first diaphragm and a second diaphragm. This structure allows increasing the bonding strength between the edge and the first diaphragm as well as between the edge and the second diaphragm, so that the loudspeaker device can withstand greater maximum inputs and reproduce quality bass sound. | 10-06-2011 |
Szu Cheng Lai, Singapore SG
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20110105942 | SYSTEM AND METHOD FOR DETECTING SKIN PENETRATION - A system and method for detecting skin penetration. The system comprises an invasive component for penetrating the skin; a dummy electrode for making contact with the surface of the skin; at least one penetrating electrode disposed in the invasive component; and a Wheatstone bridge circuit; wherein a resistance across the dummy electrode and the penetrating electrode constitutes one of the resistive legs of the Wheatstone bridge circuit and skin penetration of the invasive component is detected based on a differential output voltage from the Wheatstone bridge circuit. | 05-05-2011 |
20120267240 | PHOTOELECTRODE WITH A POLYMER LAYER - A photoelectrode including at least one polymer layer is provided. The at least one polymer layer defines the surface of the photoelectrode, or it defines an interlayer within the photoelectrode. The polymer layer can be made of a non-conductive polymer and have a thickness of 100 nm or less. | 10-25-2012 |
20130026382 | PHOTOVOLTAIC UV DETECTOR - A photovoltaic UV detector configured to generate an electrical output under UV irradiation. The photovoltaic UV detector comprises a first layer comprising an electrically polarized dielectric thin layer configured to generate a first electrical output under the UV irradiation; and a second, layer configured to form an electrical energy barrier at an interface between the second layer and the first layer so as to generate a second electrical output under the UV irradiation, the second electrical output having a same polarity as the first electrical output, the electrical output of the photovoltaic UV detector being a sum of at least the first electrical output and the second electrical output. The electrically polarized dielectric thin layer may be a ferroelectric thin film, which may comprise PZT or PZLT. The second layer may be a metal and the electrical energy barrier may be a Schottky barrier. | 01-31-2013 |
20140034815 | SELF-POWERED PHOTODETECTOR AND METHOD OF FABRICATION THEREOF - A self-powered photodetector is provided including: a photovoltaic sensor element for generating an electrical charge under exposure to electromagnetic radiation; a charge storage section for accumulating the electrical charge generated by the photovoltaic sensor element; an electrical load configured to be powered by the accumulated electrical charge from the charge storage section and outputs a signal in response thereto, the signal being analyzable to determine a measurement of the electromagnetic radiation; and a switch for controlling a flow of the accumulated electrical charge from the charge storage section to the electrical load for powering the electrical load. There is also provided a wireless receiver for analyzing a signal from the self-powered photodetector to provide a measurement of the electromagnetic radiation, a photodetector system including the self-powered photodetector and the wireless receiver, and a method of fabricating the self-powered photodetector. | 02-06-2014 |
20140319317 | PHOTO-SENSOR - According to one aspect of the invention, there is provided a photo-sensor comprising: an optically transparent substrate; an electrode pair; and a photoactive film with electrical polarization located between the optically transparent substrate and the electrode pair, wherein the optically transparent substrate is configured to transmit incident radiation received by the optically transparent substrate to the photoactive film and wherein the electrode pair is configured to receive charge carriers generated by the photoactive film in response to the transmitted incident radiation. | 10-30-2014 |
Tim Hing Lai, Singapore SG
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20160125583 | SYSTEMS AND METHODS FOR AUTOMATICALLY VERIFYING CORRECT DIE REMOVAL FROM FILM FRAMES - A skeleton wafer inspection system includes an expansion table displaceable relative to a camera configured for capturing segmental images of a skeleton wafer on a film frame. During segmental image capture, illumination is directed to the top and/or bottom of the film frame. Segmental images are digitally stitched together to pro duce a composite image, which can be processed to identify die presence or absence therein at active area die positions having counterpart die positions in a process wafer map. A composite image of a diced wafer on a film frame can also be generated, and used as a navigation aid or guide during die sort operations, or to verify whether a die sort apparatus has correctly detected a reference die prior to die sort operations. A composite image of a skeleton wafer can similarly be generated for use as a navigation aid or guide for film frame repopulation operations. | 05-05-2016 |
Weng Hong Lai, Singapore SG
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20090080132 | ANTENNA DIODES WITH ELECTRICAL OVERSTRESS (EOS) PROTECTION - An antenna diode circuit for discharging static charge accumulated during wafer processing is described. The antenna diode circuit includes first and second junctions coupled to a circuit element and substrate. Between the first and second junctions is a diode circuit path with an antenna diode and at least one diode protection circuit coupled in series. The diode protection circuit reduces or prevents EOS current from flowing through the diode circuit path during an EOS event. | 03-26-2009 |
Yicheng Lai, Singapore SG
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20090147807 | Fiber grating laser - A fiber (Bragg) laser comprising a fiber with a cladding and a core having a (Bragg) grating inscribed in the core forming a laser cavity. | 06-11-2009 |
20140078505 | OPTICAL DEVICE, METHOD OF FORMING AN OPTICAL DEVICE, AND METHOD FOR DETERMINING A PARAMETER OF A FLUID - According to embodiments of the present invention, an optical device is provided. The optical device includes an optical fiber comprising a core for propagation of light and a cladding surrounding the core, and at least one microchannel defined in the optical fiber extending at least partially through the cladding, wherein the at least one microchannel has a concave-shaped surface arranged to interact with an optical field of the light. According to further embodiments of the present invention, a method of forming an optical device and a method for determining a parameter of a fluid are also provided. | 03-20-2014 |
20150160409 | METHOD OF FABRICATING A FIBRE DEVICE - Various embodiments provide a method of fabricating a fibre, the method comprising translating a fibre having a light transmissive core surrounding by a cladding material; and while translating, non-interferometrically applying energy to alter structure of the light transmissive core and/or the cladding material. | 06-11-2015 |
Yovita Sulaiman Lai, Singapore SG
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20100161689 | METHOD OF UPDATING/MODIFYING A STAND ALONE NON-NETWORK CONNECTIBLE DEVICE - A method and system is disclosed for updating/modifying/upgrading the system configuration of a stand alone non-network connectible device. The method is performed while a portable device is docked to the non-network connectible device. System configuration update information is embedded within the ordinary data content that is received from the portable device during the routine operation of the stand alone non-network connectible device. Upon receiving the embedded system configuration update information the non-network connectible device decrypts the embedded information and updates the system configuration accordingly. Generation of the embedded system configuration update information is performed in the portable docking device, and installation is performed on the non-network connectible device without requiring a network connection in the stand alone device. | 06-24-2010 |