Patent application number | Description | Published |
20090194109 | CPAP INTERFACE AND BACKUP DEVICES - Described herein are combined active PAP/passive EPAP interface devices to transmit positive air pressure from a PAP source to the user, but provide passive EPAP when the PAP source is disabled. These interface device may continue to provide benefit to the user even if the PAP source becomes disconnected or otherwise fails. The interface devices described herein include a passive EPAP airflow resistor configured to provide expiratory positive airway pressure (“EPAP”). These interface devices may also include quick connects and/or disconnects for releasably connecting to the source of pressurized breathable gas, a quick release for disconnecting from the source of pressurized breathable gas, and an adhesive user interface region that connects the device the user's face. Also described are adapter for converting a PAP interface devices into combined active PAP/passive EPAP interface devices, and methods of using these devices. | 08-06-2009 |
20090308398 | ADJUSTABLE RESISTANCE NASAL DEVICES - Described herein are adjustable-resistance respiratory devices, and particularly nasal devices that have an adjustable expiratory resistance while providing a greater resistance to exhalation than to inhalation. The resistance to exhalation may be manually adjustable by a user or remotely adjustable by a third party. For example, described herein are nasal devices having a greater resistance to exhalation than inhalation that includes one or more resistance-modifying members for modifying the resistance of a nasal device. A resistance modifying member may include a cover, a shutter or an adjustable valve for opening/closing a leak pathway through the nasal device. An adjustable-resistance nasal respiratory device may include a control or controls for adjusting the resistance to exhalation. Methods of adjusting the resistance of a nasal device, and systems including nasal devices allowing the resistance to be optimized and/or adjusted are also described. | 12-17-2009 |
20110108041 | NASAL DEVICES HAVING A SAFE FAILURE MODE AND REMOTELY ACTIVATABLE - Described herein are devices, methods and systems that regulate the failure of a nasal device by including a pre-determined failure mode, thereby minimizing the risk. Also described herein are nasal respiratory devices that may be remotely activated or inactivated to turn on and off an increased resistance to exhalation compared to inhalation. | 05-12-2011 |
20110203598 | NASAL DEVICES INCLUDING LAYERED NASAL DEVICES AND DELAYED RESISTANCE ADAPTERS FOR USE WITH NASAL DEVICES - Described herein are layered nasal devices including layered nasal devices having one or more stiffening members supporting the holdfast region of the nasal device. The stiffening member may be a stress-distributing member or a separate stress-distributing element or member may be included. In some variations the layered nasal device includes a stress distributing element to help prevent wrinkling, de-laminating, buckling, or otherwise disrupting the shape and/or activity of the nasal device. Also described herein are delayed resistance adapters that may be used with a nasal devices that inhibit exhalation more than inhalation (including, but not limited to the adhesive nasal devices described herein). A delayed resistance adapter may be activated to suspend or bypass the increased expiratory resistance of the nasal device. Suspending the increased expiratory resistance may allow the user to allow a user to acclimate to the use of the nasal device. | 08-25-2011 |
20110218451 | NASAL DEVICES, SYSTEMS AND METHODS - Described herein are passive nasal device having a resistance to exhalation that is greater than the resistance to inhalation. Also described are devices, methods and systems for sensing and measuring intranasal pressure when a subject is wearing a passive nasal respiratory device that is configured to inhibit exhalation more than inhalation. Also described are adapters for nasal devices and methods of using a nasal device adapter. Adapters may be used so that a passive nasal device may be applied indirectly in communication with a subject's nose; in some variations this may allow the passive nasal device to be re-used. Also described herein are nasal devices having a billowing airflow resistor that is configured to have a greater resistance to exhalation than to inhalation. The billowing airflow resistor typically includes a first layer that is adjacent to a second layer; the first layer is flexible and billows opens during inhalation so that the first layer remains separated from the second layer, but remains substantially parallel to the second layer. During exhalation, the first layer collapses back down against the second layer. Additional passive nasal devices, systems and methods of using them are also described. | 09-08-2011 |
20110290256 | LAYERED NASAL RESPIRATORY DEVICES - Described herein are nasal devices, including nasal devices formed in layers having four or fewer layers. In some variations, the nasal devices include a single integrated layer from which the flap of the airflow resistor is formed as well as the base of the holdfast region. The nasal devices may include a single aligner or rim body on the side of the device facing the subject. The aligner may protect the airflow resistor, and may help center or position the nasal device. In some variations, these nasal devices may include a noise-reduction feature. Also described herein are systems, devices and methods for determining if a passive nasal respiratory device having an airflow resistor configured to inhibit exhalation more than inhalation has been worn by a subject, and thereby confirming compliance. | 12-01-2011 |
20140109907 | CPAP INTERFACE AND BACKUP DEVICES - Described herein are combined active PAP/passive EPAP interface devices to transmit positive air pressure from a PAP source to the user, but provide passive EPAP when the PAP source is disabled. These interface device may continue to provide benefit to the user even if the PAP source becomes disconnected or otherwise fails. The interface devices described herein include a passive EPAP airflow resistor configured to provide expiratory positive airway pressure (“EPAP”). These interface devices may also include quick connects and/or disconnects for releasably connecting to the source of pressurized breathable gas, a quick release for disconnecting from the source of pressurized breathable gas, and an adhesive user interface region that connects the device the user's face. Also described are adapter for converting a PAP interface devices into combined active PAP/passive EPAP interface devices, and methods of using these devices. | 04-24-2014 |
Patent application number | Description | Published |
20140035892 | INCORPORATION OF PASSIVES AND FINE PITCH THROUGH VIA FOR PACKAGE ON PACKAGE - This disclosure provides systems, methods and apparatus for glass via bars that can be used in compact three-dimensional packages, including package-on-packages (PoPs). The glass via bars can provide high density electrical interconnections in the PoPs. In some implementations, the glass via bars can include integrated passive components. Packaging methods employing glass via bars are also provided. | 02-06-2014 |
20140035935 | PASSIVES VIA BAR - This disclosure provides systems, methods and apparatus for glass via bars that can be used in compact three-dimensional packages, including embedded wafer level packages. The glass via bars can provide high density electrical interconnections in a package. In some implementations, the glass via bars can include integrated passive components. Methods of fabricating glass via bars are provided. In some implementations, the methods can include patterning and etching photo-patternable glass substrates. Packaging methods employing glass via bars are also provided. | 02-06-2014 |
20140104284 | THROUGH SUBSTRATE VIA INDUCTORS - This disclosure provides systems, methods, and apparatus for through substrate via inductors. In one aspect, a cavity is defined in a glass substrate. At least two metal bars are in the cavity. A first end of each metal bar is proximate a first surface of the substrate, and a second end of each metal bar is proximate a second surface of the substrate. A metal trace connects a first metal bar and a second metal bar. In some instances, one or more dielectric layers can be disposed on surfaces of the substrate. In some instances, the metal bars and the metal trace define an inductor. The inductor can have a degree of flexibility corresponding to a variable inductance. Metal turns can be arranged in a solenoidal or toroidal configuration. The toroidal inductor can have tapered traces and/or thermal ground planes. Transformers and resonator circuitry can be realized. | 04-17-2014 |
20140104288 | THROUGH SUBSTRATE VIA INDUCTORS - This disclosure provides systems, methods, and apparatus for through substrate via inductors. In one aspect, a cavity is defined in a glass substrate. At least two metal bars are in the cavity. A first end of each metal bar is proximate a first surface of the substrate, and a second end of each metal bar is proximate a second surface of the substrate. A metal trace connects a first metal bar and a second metal bar. In some instances, one or more dielectric layers can be disposed on surfaces of the substrate. In some instances, the metal bars and the metal trace define an inductor. The inductor can have a degree of flexibility corresponding to a variable inductance. Metal turns can be arranged in a solenoidal or toroidal configuration. The toroidal inductor can have tapered traces and/or thermal ground planes. Transformers and resonator circuitry can be realized. | 04-17-2014 |
20140144681 | ADHESIVE METAL NITRIDE ON GLASS AND RELATED METHODS - This disclosure provides systems, methods and apparatus for an adhesive metal nitride layer on glass. In one aspect, a glass substrate having a surface is provided. A via with a depth to width aspect ratio of 5 to 1 or greater extends at least partially through the glass substrate. An adhesive metal nitride layer is disposed on the surface of the glass substrate and on one or more interior surfaces of the via. The adhesive metal nitride layer includes at least one of titanium nitride and tantalum nitride. | 05-29-2014 |
20140177188 | LASER ENCAPSULATION OF MULTIPLE DISSIMILAR DEVICES ON A SUBSTRATE - This disclosure provides systems, methods and apparatus for packaging of dissimilar devices using electromagnetic radiation from a laser. In one aspect, an apparatus can include a first substrate, a second substrate, and a first device and a second device disposed on the second substrate. A first metal ring on the first substrate contacts a second metal ring on a second substrate, and is heated by a first electromagnetic radiation from a laser to enclose a first cavity containing the first device. A third metal ring on the first substrate contacts a fourth metal ring on the second substrate, and is heated by a second electromagnetic radiation to enclose a second cavity containing the second device. Enclosing the first cavity may be performed under a first atmosphere, and the enclosing the second cavity may be performed under a second, different atmosphere. | 06-26-2014 |
20150041189 | METAL-INSULATOR-METAL CAPACITORS ON GLASS SUBSTRATES - This disclosure provides systems, methods, and apparatus for metal-insulator-metal capacitors on glass substrates. In one aspect, an apparatus may include a glass substrate, with the glass substrate defining at least one via in the glass substrate. A first electrode layer may be disposed over surfaces of the glass substrate, including surfaces of the at least one via. A dielectric layer may be disposed on the first electrode layer. A second electrode layer may be disposed on the dielectric layer, with the dielectric layer electrically isolating the first electrode layer from the second electrode layer. | 02-12-2015 |
Patent application number | Description | Published |
20080279032 | Integrated Circuit Memory Device, System And Method Having Interleaved Row And Column Control - An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal. | 11-13-2008 |
20090193202 | MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE - A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface. | 07-30-2009 |
20100030955 | MASK KEY SELECTION BASED ON DEFINED SELECTION CRITERIA - An improved data system permits power efficient mask key write operations. A mask key selector implements criteria-based selection of mask keys for mask key write operations on blocks data. In one embodiment, a first set of mask keys is compared to data bytes of a data block that will be written to memory. The comparison culls keys from the list of candidates that match unmasked data bytes, that is, values that will be written to memory as “changed” data. A mask key is selected from the resulting set of candidates so a memory write operation consumes less power (relative to selection of other keys), or so that the operation minimizes switching noise. The selected mask key is then substituted by a controller into masked data values, and a modified data block is transmitted to memory, with the memory detecting masked data by identifying mask keys in the modified data block. | 02-04-2010 |
20110153932 | MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE - A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface. | 06-23-2011 |
20110211415 | Integrated Circuit Memory Device, System And Method Having Interleaved Row And Column Control - An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal. | 09-01-2011 |
20120020178 | MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE - A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface. | 01-26-2012 |
20120117317 | ATOMIC MEMORY DEVICE - In an integrated-circuit memory device having a memory core, a first data value is retrieved from an address-specified location within the memory core in response to a memory access command. The first data value is output from the memory device in response to the memory access command, and a second data value is stored in the address-specified location within the memory core in response to the memory access command. | 05-10-2012 |
20120170399 | MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE - A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface. | 07-05-2012 |
20130194854 | MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DATA INTERFACES - A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins. | 08-01-2013 |
20130265842 | Micro-Threaded Memory - A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval. | 10-10-2013 |
20130305074 | PROTOCOL FOR MEMORY POWER-MODE CONTROL - In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command. | 11-14-2013 |
20140003131 | MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE | 01-02-2014 |
20140082234 | COMMUNICATION VIA A MEMORY INTERFACE - A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer. | 03-20-2014 |
20140344546 | Memory Controller For Micro-Threaded Memory Operations - A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval. | 11-20-2014 |
20150103610 | PROTOCOL FOR MEMORY POWER-MODE CONTROL - In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command. | 04-16-2015 |
20150106560 | METHODS AND SYSTEMS FOR MAPPING A PERIPHERAL FUNCTION ONTO A LEGACY MEMORY INTERFACE - A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power. | 04-16-2015 |
20150178187 | SINGLE COMMAND, MULTIPLE COLUMN-OPERATION MEMORY DEVICE - A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values. | 06-25-2015 |
20150270000 | METHODS AND SYSTEMS FOR MAPPING A PERIPHERAL FUNCTION ONTO A LEGACY MEMORY INTERFACE - A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power. | 09-24-2015 |
20150324309 | COMMUNICATION VIA A MEMORY INTERFACE - A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer. | 11-12-2015 |
20150332746 | MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DATA INTERFACES - A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins. | 11-19-2015 |
Patent application number | Description | Published |
20080229121 | Selectively Powered Data Interfaces - A plurality of separately powered data interface circuits, a controller circuit, and power switch circuits that collectively enable a supply of power to only one of the data interface circuits and disable the supply of power to the other data interface circuits. Alternatively, the separately powered circuits need not be data interface circuits. | 09-18-2008 |
20090160256 | Multi-regulator power delivery system for ASIC cores - A method for operating an electronic product having an application specific semiconductor chip (ASIC) device which includes in its circuitry both a linear regulator module configured to be coupled to an optional external capacitance and a capless regulator module configured to be coupled to internal capacitance of the electronic product utilizes control logic of the ASIC device responsive to a regulator selection signal for selecting one of the linear regulator module and the capless regulator module for use in powering the ASIC device. The control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation. | 06-25-2009 |
20090160421 | Multi-regulator power delivery system for ASIC cores - An electronic product includes an application specific semiconductor chip (ASIC) device which includes in its circuitry both a linear regulator module configured to be coupled to an optional external capacitance and a capless regulator module configured to be coupled to internal capacitance of the electronic product. Control logic of the ASIC device is responsive to a regulator selection signal for selecting one of the linear regulator module and the capless regulator module for use in powering the ASIC device. The control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation. | 06-25-2009 |
20090160423 | Self-configurable multi-regulator ASIC core power delivery - An electronic product includes an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product. The capless regulator module includes both a low-power sub-module and a high-power sub-module. Control logic of the ASIC is configured to determine if an external capacitance is present. If so, the control logic causes the high-power capless regulator sub-module to be used during a power-up phase of the ASIC; if not, only the low-power capless regulator sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation. | 06-25-2009 |
20090164807 | Self-configurable multi-regulator ASIC core power delivery - A method for operating an electronic product having an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product selects a low-power sub-module or high-power sub-module of the capless regulator module for use in a power-up phase of the ASIC. Control logic of the ASIC determines if an external capacitance is present. If so, then the high-power capless sub-module is used during a power-up phase of the ASIC; if not only the low-power capless sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation. | 06-25-2009 |
20090166679 | INTEGRATED CIRCUIT AND MANUFACTURING PROCESS FACILITATING SELECTIVE CONFIGURATION FOR ELECTROMAGNETIC COMPATIBILITY - An integrated circuit (IC) having a selectively-designated electromagnetic compatibility (EMC) performance characteristic. The IC includes an IC die having an input or output (I/O) node. A first I/O cell of a first type associated with the I/O node provides a first EMC performance characteristic, and a second I/O cell of a second type associated with the I/O node provides a second EMC performance characteristic different from the first EMC performance characteristic. A first bonding pad is electrically coupled with the first I/O cell, and a second bonding pad is electrically coupled with the second I/O cell. The IC die can be packaged into a packaged IC having an I/O pin corresponding to the I/O node. The I/O pin is wired to one of either the first bonding pad or the second bonding pad, but not to the other, such that a pinout for the I/O node is preferentially provided having one of either the first EMC performance characteristic or the second EMC performance characteristic. | 07-02-2009 |
20090167357 | EXTENDING DRIVE CAPABILITY IN INTEGRATED CIRCUITS UTILIZING PROGRAMMABLE-VOLTAGE OUTPUT CIRCUITS - An integrated circuit (IC) includes an output driver circuit portion that is electrically configurable, via a configuration input, to operate in either a first mode or a second mode corresponding to an indication of a condition of the IC, such as a supply voltage indication, the first mode and the second mode having different drive characteristics. A configuration interface circuit portion as part of the improved IC is adapted to selectively override the configuration input to configure operation of the output driver circuit portion in either the first mode or the second mode based on a drive strength control input, regardless of the condition of the IC. | 07-02-2009 |
Patent application number | Description | Published |
20090284292 | SIGNAL ADJUSTMENT RECEIVER CIRCUITRY - Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block. | 11-19-2009 |
20090285275 | SIGNAL ADJUSTMENT RECEIVER CIRCUITRY - Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block. | 11-19-2009 |
20110188564 | DIGITAL ADAPTATION CIRCUITRY AND METHODS FOR PROGRAMMABLE LOGIC DEVICES - Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal. | 08-04-2011 |
20110188621 | CLOCK AND DATA RECOVERY CIRCUITRY WITH AUTO-SPEED NEGOTIATION AND OTHER POSSIBLE FEATURES - An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation. | 08-04-2011 |
20130093482 | CLOCK AND DATA RECOVERY CIRCUITRY WITH AUTO-SPEED NEGOTIATION AND OTHER POSSIBLE FEATURES - An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation. | 04-18-2013 |