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| 20090194109 | CPAP INTERFACE AND BACKUP DEVICES - Described herein are combined active PAP/passive EPAP interface devices to transmit positive air pressure from a PAP source to the user, but provide passive EPAP when the PAP source is disabled. These interface device may continue to provide benefit to the user even if the PAP source becomes disconnected or otherwise fails. The interface devices described herein include a passive EPAP airflow resistor configured to provide expiratory positive airway pressure (“EPAP”). These interface devices may also include quick connects and/or disconnects for releasably connecting to the source of pressurized breathable gas, a quick release for disconnecting from the source of pressurized breathable gas, and an adhesive user interface region that connects the device the user's face. Also described are adapter for converting a PAP interface devices into combined active PAP/passive EPAP interface devices, and methods of using these devices. | 08-06-2009 |
| 20090308398 | ADJUSTABLE RESISTANCE NASAL DEVICES - Described herein are adjustable-resistance respiratory devices, and particularly nasal devices that have an adjustable expiratory resistance while providing a greater resistance to exhalation than to inhalation. The resistance to exhalation may be manually adjustable by a user or remotely adjustable by a third party. For example, described herein are nasal devices having a greater resistance to exhalation than inhalation that includes one or more resistance-modifying members for modifying the resistance of a nasal device. A resistance modifying member may include a cover, a shutter or an adjustable valve for opening/closing a leak pathway through the nasal device. An adjustable-resistance nasal respiratory device may include a control or controls for adjusting the resistance to exhalation. Methods of adjusting the resistance of a nasal device, and systems including nasal devices allowing the resistance to be optimized and/or adjusted are also described. | 12-17-2009 |
| 20110108041 | NASAL DEVICES HAVING A SAFE FAILURE MODE AND REMOTELY ACTIVATABLE - Described herein are devices, methods and systems that regulate the failure of a nasal device by including a pre-determined failure mode, thereby minimizing the risk. Also described herein are nasal respiratory devices that may be remotely activated or inactivated to turn on and off an increased resistance to exhalation compared to inhalation. | 05-12-2011 |
| 20110203598 | NASAL DEVICES INCLUDING LAYERED NASAL DEVICES AND DELAYED RESISTANCE ADAPTERS FOR USE WITH NASAL DEVICES - Described herein are layered nasal devices including layered nasal devices having one or more stiffening members supporting the holdfast region of the nasal device. The stiffening member may be a stress-distributing member or a separate stress-distributing element or member may be included. In some variations the layered nasal device includes a stress distributing element to help prevent wrinkling, de-laminating, buckling, or otherwise disrupting the shape and/or activity of the nasal device. Also described herein are delayed resistance adapters that may be used with a nasal devices that inhibit exhalation more than inhalation (including, but not limited to the adhesive nasal devices described herein). A delayed resistance adapter may be activated to suspend or bypass the increased expiratory resistance of the nasal device. Suspending the increased expiratory resistance may allow the user to allow a user to acclimate to the use of the nasal device. | 08-25-2011 |
| 20110218451 | NASAL DEVICES, SYSTEMS AND METHODS - Described herein are passive nasal device having a resistance to exhalation that is greater than the resistance to inhalation. Also described are devices, methods and systems for sensing and measuring intranasal pressure when a subject is wearing a passive nasal respiratory device that is configured to inhibit exhalation more than inhalation. Also described are adapters for nasal devices and methods of using a nasal device adapter. Adapters may be used so that a passive nasal device may be applied indirectly in communication with a subject's nose; in some variations this may allow the passive nasal device to be re-used. Also described herein are nasal devices having a billowing airflow resistor that is configured to have a greater resistance to exhalation than to inhalation. The billowing airflow resistor typically includes a first layer that is adjacent to a second layer; the first layer is flexible and billows opens during inhalation so that the first layer remains separated from the second layer, but remains substantially parallel to the second layer. During exhalation, the first layer collapses back down against the second layer. Additional passive nasal devices, systems and methods of using them are also described. | 09-08-2011 |
| 20110290256 | LAYERED NASAL RESPIRATORY DEVICES - Described herein are nasal devices, including nasal devices formed in layers having four or fewer layers. In some variations, the nasal devices include a single integrated layer from which the flap of the airflow resistor is formed as well as the base of the holdfast region. The nasal devices may include a single aligner or rim body on the side of the device facing the subject. The aligner may protect the airflow resistor, and may help center or position the nasal device. In some variations, these nasal devices may include a noise-reduction feature. Also described herein are systems, devices and methods for determining if a passive nasal respiratory device having an airflow resistor configured to inhibit exhalation more than inhalation has been worn by a subject, and thereby confirming compliance. | 12-01-2011 |
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| 20080316830 | COMPENSATION METHOD TO ACHIEVE UNIFORM PROGRAMMING SPEED OF FLASH MEMORY DEVICES - Systems and methodologies are provided herein for increasing operation speed uniformity in a flash memory device. Due to the characteristics of a typical flash memory array, memory cells in a memory array may experience distributed substrate resistance that increases as the distance of the memory cell from an edge of the memory array increases. This difference in distributed substrate resistance can vary voltages supplied to different memory cells in the memory array depending on their location, which can in turn cause non-uniformity in the speed of high voltage operations on the memory array such as programming. The systems and methodologies provided herein reduce this non-uniformity in operation speed by providing compensated voltage levels to memory cells in a memory array based at least in part on the location of each respective memory cell. For example, a compensated operation voltage can be provided that is higher near the center of the memory array and lower near an edge of the memory array, thereby lessening the effect of distributed substrate resistance and providing increased operation speed uniformity throughout the memory array. | 12-25-2008 |
| 20090106481 | HYBRID FLASH MEMORY DEVICE - A hybrid memory system is provided that combines the advantages of NAND flash memory devices with the advantages of NOR flashes memory devices. The system includes a NAND flash memory portion to provide mass storage and fast programming/erasure capabilities of conventional NAND flash memory devices. The system further comprises a NOR flash memory portion to provide code storage and fast random reading capabilities of conventional NOR flash memory devices. Accordingly, the hybrid memory system provides both mass storage and code storage. along with fast programming/erasure speeds and fast random access speeds. | 04-23-2009 |
| 20090273998 | BITCELL CURRENT SENSE DEVICE AND METHOD THEREOF - A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell and a reference current. During a first phase, the switch between the input terminals of the sense amplifier is closed, so that a common voltage is applied to both input terminals. During a second phase, the switch is opened, and the sense amplifier senses a state of information stored at the bitcell based on the current through the node. By using the switch to connect and disconnect the inputs of the sense amplifier in the two phases, the accuracy and speed with which the state of the information stored at the bitcell can be determined is improved. | 11-05-2009 |
| 20100090337 | SYSTEM AND METHOD FOR MULTI-LAYER GLOBAL BITLINES - A system and method for manufacturing a semiconductor device including multi-layer bitlines. The location of the bitlines in multiple layers provides for increased spacing and increased width thereby overcoming the limitations of the pitch dictated by the semiconductor fabrication process used. The bitlines locations in multiple layers thus allows the customization of the spacing and width according to the use of a semiconductor device. | 04-15-2010 |
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| 20080279032 | Integrated Circuit Memory Device, System And Method Having Interleaved Row And Column Control - An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal. | 11-13-2008 |
| 20090193202 | MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE - A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface. | 07-30-2009 |
| 20100030955 | MASK KEY SELECTION BASED ON DEFINED SELECTION CRITERIA - An improved data system permits power efficient mask key write operations. A mask key selector implements criteria-based selection of mask keys for mask key write operations on blocks data. In one embodiment, a first set of mask keys is compared to data bytes of a data block that will be written to memory. The comparison culls keys from the list of candidates that match unmasked data bytes, that is, values that will be written to memory as “changed” data. A mask key is selected from the resulting set of candidates so a memory write operation consumes less power (relative to selection of other keys), or so that the operation minimizes switching noise. The selected mask key is then substituted by a controller into masked data values, and a modified data block is transmitted to memory, with the memory detecting masked data by identifying mask keys in the modified data block. | 02-04-2010 |
| 20110153932 | MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE - A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface. | 06-23-2011 |
| 20110211415 | Integrated Circuit Memory Device, System And Method Having Interleaved Row And Column Control - An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal. | 09-01-2011 |
| 20120020178 | MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE - A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface. | 01-26-2012 |
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| 20080229121 | Selectively Powered Data Interfaces - A plurality of separately powered data interface circuits, a controller circuit, and power switch circuits that collectively enable a supply of power to only one of the data interface circuits and disable the supply of power to the other data interface circuits. Alternatively, the separately powered circuits need not be data interface circuits. | 09-18-2008 |
| 20090160256 | Multi-regulator power delivery system for ASIC cores - A method for operating an electronic product having an application specific semiconductor chip (ASIC) device which includes in its circuitry both a linear regulator module configured to be coupled to an optional external capacitance and a capless regulator module configured to be coupled to internal capacitance of the electronic product utilizes control logic of the ASIC device responsive to a regulator selection signal for selecting one of the linear regulator module and the capless regulator module for use in powering the ASIC device. The control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation. | 06-25-2009 |
| 20090160421 | Multi-regulator power delivery system for ASIC cores - An electronic product includes an application specific semiconductor chip (ASIC) device which includes in its circuitry both a linear regulator module configured to be coupled to an optional external capacitance and a capless regulator module configured to be coupled to internal capacitance of the electronic product. Control logic of the ASIC device is responsive to a regulator selection signal for selecting one of the linear regulator module and the capless regulator module for use in powering the ASIC device. The control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation. | 06-25-2009 |
| 20090160423 | Self-configurable multi-regulator ASIC core power delivery - An electronic product includes an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product. The capless regulator module includes both a low-power sub-module and a high-power sub-module. Control logic of the ASIC is configured to determine if an external capacitance is present. If so, the control logic causes the high-power capless regulator sub-module to be used during a power-up phase of the ASIC; if not, only the low-power capless regulator sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation. | 06-25-2009 |
| 20090164807 | Self-configurable multi-regulator ASIC core power delivery - A method for operating an electronic product having an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product selects a low-power sub-module or high-power sub-module of the capless regulator module for use in a power-up phase of the ASIC. Control logic of the ASIC determines if an external capacitance is present. If so, then the high-power capless sub-module is used during a power-up phase of the ASIC; if not only the low-power capless sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation. | 06-25-2009 |
| 20090166679 | INTEGRATED CIRCUIT AND MANUFACTURING PROCESS FACILITATING SELECTIVE CONFIGURATION FOR ELECTROMAGNETIC COMPATIBILITY - An integrated circuit (IC) having a selectively-designated electromagnetic compatibility (EMC) performance characteristic. The IC includes an IC die having an input or output (I/O) node. A first I/O cell of a first type associated with the I/O node provides a first EMC performance characteristic, and a second I/O cell of a second type associated with the I/O node provides a second EMC performance characteristic different from the first EMC performance characteristic. A first bonding pad is electrically coupled with the first I/O cell, and a second bonding pad is electrically coupled with the second I/O cell. The IC die can be packaged into a packaged IC having an I/O pin corresponding to the I/O node. The I/O pin is wired to one of either the first bonding pad or the second bonding pad, but not to the other, such that a pinout for the I/O node is preferentially provided having one of either the first EMC performance characteristic or the second EMC performance characteristic. | 07-02-2009 |
| 20090167357 | EXTENDING DRIVE CAPABILITY IN INTEGRATED CIRCUITS UTILIZING PROGRAMMABLE-VOLTAGE OUTPUT CIRCUITS - An integrated circuit (IC) includes an output driver circuit portion that is electrically configurable, via a configuration input, to operate in either a first mode or a second mode corresponding to an indication of a condition of the IC, such as a supply voltage indication, the first mode and the second mode having different drive characteristics. A configuration interface circuit portion as part of the improved IC is adapted to selectively override the configuration input to configure operation of the output driver circuit portion in either the first mode or the second mode based on a drive strength control input, regardless of the condition of the IC. | 07-02-2009 |
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| 20090284292 | SIGNAL ADJUSTMENT RECEIVER CIRCUITRY - Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block. | 11-19-2009 |
| 20090285275 | SIGNAL ADJUSTMENT RECEIVER CIRCUITRY - Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block. | 11-19-2009 |
| 20110188564 | DIGITAL ADAPTATION CIRCUITRY AND METHODS FOR PROGRAMMABLE LOGIC DEVICES - Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal. | 08-04-2011 |
| 20110188621 | CLOCK AND DATA RECOVERY CIRCUITRY WITH AUTO-SPEED NEGOTIATION AND OTHER POSSIBLE FEATURES - An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation. | 08-04-2011 |
