Patent application number | Description | Published |
20100061153 | Refresh Method for a Non-volatile Memory - A refresh method for a non-volatile memory for preventing disturb phenomenon includes dividing a plurality of sectors of a block of the non-volatile memory into a plurality of groups, determining a first group of the plurality of groups according to a first value when a first sector of the plurality of sectors is performed an erase operation, and reading and rewriting data of sectors of the first group. | 03-11-2010 |
20100067295 | Refresh Method for a Non-volatile Memory - A refresh method for a non-volatile memory for preventing disturb phenomenon includes reading data of a memory unit of the non-volatile memory at a first time point within a predefined period and storing the data in a buffer, determining whether data of the memory unit and data of the buffer are identical at a second time point within the predefined period, so as to generate a determination result, and refreshing the memory unit according to the determination result. | 03-18-2010 |
20120324147 | Read While Write Method for Serial Peripheral Interface Flash Memory - The present invention discloses a RWW method for SPI flash memory. The RWW method comprises executing a write command, halting the write command during receiving a read command, executing the reading, and internally restoring the write command when completing the read command. | 12-20-2012 |
Patent application number | Description | Published |
20120270382 | METHOD OF FABRICATING AN EPITAXIAL LAYER - A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si—OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800° C. | 10-25-2012 |
20130026464 | TEST PATTERN FOR MEASURING SEMICONDUCTOR ALLOYS USING X-RAY DIFFRACTION - A test pattern for measuring semiconductor alloys using X-ray diffraction (XRD) includes a first region to an Nth region defined on a wafer, and a plurality of test structures positioned in the first region and so forth up to in the Nth region. The test structures in the same region have sizes identical to each other and the test structures in different regions have sizes different from each other. | 01-31-2013 |
20130026538 | SEMICONDUCTOR DEVICE HAVING EPITAXIAL STRUCTURES - A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant, and the second lattice constant is larger than the first lattice constant. The undoped cap layer also includes the first semiconductor material and the second semiconductor material. The second semiconductor material in the epitaxial structures includes a first concentration, the second semiconductor material in the undoped cap layer includes at least a first concentration, and the second concentration is lower than the first concentration. | 01-31-2013 |
20130126949 | MOS DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a metal oxide semiconductor (MOS) device is described, including following steps. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed with an epitaxial temperature lower than 700° C., so as to form a cap layer on each of the first semiconductor compound layers. Each of the cap layers includes a second semiconductor compound layer protruding from a surface of the substrate. The first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element. The content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers. | 05-23-2013 |
20130137243 | SEMICONDUCTOR PROCESS - First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below −30° C. | 05-30-2013 |
20140191285 | SEMICONDUCTOR DEVICE HAVING EPITAXIAL STRUCTURES - A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant. The epitaxial structures and the undoped cap layer include a first semiconductor material having a first lattice constant and a second semiconductor material having a second lattice constant. The second lattice constant is larger than the first lattice constant. The second semiconductor material in the epitaxial structure includes a first concentration and the second semiconductor material in the undoped cap layer includes a second concentration. The second concentration is lower than the first concentration, and is upwardly decreased. | 07-10-2014 |
Patent application number | Description | Published |
20120235174 | LIQUID CRYSTAL PANEL AND PIXEL STRUCTURE THEREOF - There is provided a pixel structure of a liquid crystal panel including a transparent substrate, and a gate line, a data line, a switching transistor, a first electrode, a second electrode and a shield layer formed on the transparent substrate. The gate line is substantially perpendicular to the data line. The switching transistor is located adjacent to a crossing point of the gate line and the data line, and is configured to input a display voltage of the data line to the second electrode according to the control of the gate line. The first electrode and the second electrode are arranged in such a way that the display voltage forms a transverse electric field between the first electrode and the second electrode. The shield layer overlaps at least a part of the gate and is electrically isolated from the first electrode and the second electrode. | 09-20-2012 |
20140103307 | VERTICAL THIN-FILM TRANSISTOR STRUCTURE OF DISPLAY PANEL AND METHOD OF FABRICATING THE SAME - A vertical thin-film transistor structure includes a substrate, a source electrode, an insulation layer, a drain electrode, two first channel layers, a gate insulation layer and a gate electrode, which are stacked upward in that order on the substrate. The first channel layers are respectively disposed at two opposite ends of the drain electrode, and extend from the upper surface of the drain electrode to the upper surface of the source electrode respectively. Each of the first channel layers contacts the source electrode and the drain electrode. The gate insulation layer is disposed on the source electrode, the first channel layers and the drain electrode. The gate electrode is disposed on the gate insulation layer and covers the first channel layers. Therefore, the volume of the conventional thin-film transistor structure shrinks, and the ratio of the volume of the conventional thin-film transistor structure to that of a pixel structure decreases. | 04-17-2014 |
20140168583 | PIXEL STRUCTURE OF A LIQUID CRYSTAL DISPLAY PANEL AND PIXEL FORMING METHOD THEREOF - A pixel structure of a liquid crystal display panel includes a first substrate; a color filter layer formed on the first substrate, the color filter layer comprising a plurality of filtering areas for filtering light, and a plurality of blocking areas for blocking light; a main spacer formed on one of the blocking areas; a sub spacer formed on another one of the blocking areas; a second substrate; a thin film transistor formed on the second substrate; an insulating layer formed above the thin film transistor and the second substrate; a liquid crystal layer formed between the first substrate and the second substrate; wherein a distance from an upper surface of the insulating layer near the main spacer to the second substrate is greater than a distance from an upper surface of the insulating layer near the sub spacer to the second substrate. | 06-19-2014 |
20140340603 | PIXEL ARRAY SUBSTRATE - A pixel array substrate includes a substrate, a plurality of thin-film transistors disposed on the substrate, a first insulating layer covering the thin-film transistors and the substrate, a common electrode disposed on the first insulating layer, a second insulating layer covering the first insulating layer and the common electrode, and a plurality of pixel electrodes disposed on the second insulating layer. Each thin-film transistor includes a drain electrode. The first insulating layer includes a plurality of first openings exposing the drain electrodes respectively. The second insulating layer includes a plurality of second openings exposing the first openings respectively. Each pixel electrode is electrically connected to each drain electrode respectively through each first opening and each second opening. The first insulating layer includes a thickness between 1 micron and 5 microns. | 11-20-2014 |
20150034943 | Thin film transistor array substrate - The present invention discloses a thin film transistor array substrate comprising a plurality of thin film transistors, with each one thereof including a gate electrode, a gate insulation layer, an amorphous-oxide semiconductor layer and a pair of a source electrode and a drain electrode. The amorphous-oxide semiconductor layer comprises an amorphous-oxide semiconductor material having a-IGZO. The thin film transistor array substrate further comprises a first insulation layer and a second insulation layer disposed on the thin film transistors. Since the a-IGZO semiconductor layer and the thick insulation layer covered thereon are used in the present invention, a common electrode can overlap the scan lines or data lines to increase the aperture ratio of the pixel structure. Furthermore, the thick insulation layer can be fabricated through a coating process, so as to keep the a-IGZO semiconductor layer from damages during the fabrication processes. | 02-05-2015 |
20150076486 | PIXEL STRUCTURE AND FABRICATING METHOD THEREOF - The pixel structure includes a scan line, a data line, a thin-film transistor, a first electrode layer, a protective layer and a second electrode layer. The thin-film transistor is electrically connected to the scan line and the data line, and includes a gate, an oxide semiconductor layer, an insulating layer, a source and a drain. The first electrode layer is in the same layer as the oxide semiconductor layer, and is surrounded by the scan line and the data line. The second electrode layer is located on the first electrode layer, and the protective layer is located between the first electrode layer and the second electrode layer, wherein one of the first and second electrode layers is electrically connected to the thin-film transistor, and the other is connected to a common voltage. The second electrode layer includes a plurality of slits exposing an area of the first electrode layer. | 03-19-2015 |
20150194449 | PIXEL SUBSTRATE AND FABRICATION METHOD THEREOF - A pixel substrate and a fabrication method thereof are provided. The method includes: forming a gate and a lower pad on a substrate; forming a gate insulating layer overlaying the gate and the lower pad; forming a channel layer and a first electrode layer on the gate insulating layer, in which the projection areas of the channel layer and the gate on the substrate are overlapped; forming an etching-barrier material layer on the substrate and simultaneously forming a contact opening at the gate insulating layer to expose the lower pad; forming a source, a drain and an upper pad on the substrate; forming a protective layer; forming a second electrode layer with multiple slits on the protective layer, in which one of the first and second electrode layers is electrically connected to the drain. The invention can simplify the process steps and reduce fabrication time. | 07-09-2015 |
Patent application number | Description | Published |
20120071004 | STRESS-ADJUSTING METHOD OF MOS DEVICE - A stress-adjusting method for use in a manufacturing system of a MOS device is provided. At first, a first stress layer is formed onto a substrate wherein at least two MOSFETs are previously formed on the substrate. The first stress layer overlies an inter-gate region between two adjacent gate regions of the MOSFETs and overlies the two adjacent gate regions. Then, the first stress layer in the inter-gate region is thinned. A second stress layer is further formed onto the substrate to overlie the thinned first stress layer in the inter-gate region to provide the resulting MOS device with satisfactory stress. | 03-22-2012 |
20120306028 | SEMICONDUCTOR PROCESS AND STRUCTURE THEREOF - A semiconductor process is provided, including: a substrate is provided, a buffer layer is formed, and a dielectric layer having a high dielectric constant is formed, wherein the methods of forming the buffer layer include: (1) an oxidation process is performed; and a baking process is performed; Alternatively, (2) an oxidation process is performed; a thermal nitridation process is performed; and a plasma nitridation process is performed; Or, (3) a decoupled plasma oxidation process is performed. Furthermore, a semiconductor structure fabricated by the last process is also provided. | 12-06-2012 |
20130012012 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate having an oxide layer thereon is provided. A high temperature process higher than 1000° C. is performed to form a melting layer between the substrate and the oxide layer. A removing process is performed to remove the oxide layer and the melting layer. | 01-10-2013 |
20130045594 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING METAL GATE - A manufacturing method for a semiconductor device having a metal gate includes providing a substrate having at least a first semiconductor device formed thereon, forming a first gate trench in the first semiconductor device, forming a first work function metal layer in the first gate trench, and performing a decoupled plasma oxidation to the first work function metal layer. | 02-21-2013 |
20130075874 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure includes a substrate, an oxide layer, a metallic oxynitride layer and a metallic oxide layer. The oxide layer is located on the substrate. The metallic oxynitride layer is located on the oxide layer. The metallic oxide layer is located on the metallic oxynitride layer. In addition, the present invention also provides a semiconductor process for forming the semiconductor structure. | 03-28-2013 |
20140057434 | THROUGH SILICON VIA PROCESS - A through silicon via process includes the following steps. A substrate having a front side and a back side is provided. A passivation layer is formed on the back side of the substrate. An oxide layer is formed on the passivation layer. | 02-27-2014 |
20140295629 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses. | 10-02-2014 |
20140349467 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface. | 11-27-2014 |
20150263170 | SEMICONDUCTOR PROCESS FOR MODIFYING SHAPE OF RECESS - A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface. | 09-17-2015 |
Patent application number | Description | Published |
20110134318 | HEAD-MOUNTED VISUAL DISPLAY DEVICE FOR LOW-VISION AID AND ITS SYSTEM - A head-mounted visual display device for low-vision aid, which features 2 models, they are analog signal model and digital signal model. Said analog device contains at least an analog video extractor, a video decoder, an ITU-R.656 decoder, a de-interlacing unit, an image processor, two YCbCr to RGB converter, two color enhancement units, two video D/A converter, a head mounted display, a signal voltage controller and a wireless communication module. Said digital device consists of a digital video signal extractor/capturer, a RGB to YCbCr converter, an image processor, two YCbCr to RGB converter, two color enforcement units, a head-mounted display, a signal voltage controller and a wireless communication module. | 06-09-2011 |
20110134319 | HEAD-MOUNTED VISUAL DISPLAY DEVICE WITH STEREO VISION AND ITS SYSTEM - A head-mounted visual display device for low-vision aid, which features 2 models, they are analog signal model and digital signal model. Said analog device contains at least an analog video extractor, a video decoder, an ITU-R.656 decoder, a de-interlacing unit, an image processor, two YCbCr to RGB converter, two color enhancement units, two video D/A converter, a head mounted display, a signal voltage controller and a wireless communication module. Said digital device consists of a digital video signal extractor/capturer, a RGB to YCbCr converter, an image processor, two YCbCr to RGB converter, two color enforcement units, a head-mounted display, a signal voltage controller and a wireless communication module. | 06-09-2011 |