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Lai, Hsinchu City
Chao-Hsu Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100308348 | LIGHT-EMITTING DEVICE AND THE MANUFACTURING METHOD THEREOF - The disclosure provides a light-emitting device comprising a light-emitting epitaxy structure. The light-emitting epitaxy structure has a modulus of a critical reverse voltage not less than 50 volts while the light-emitting epitaxy structure is reverse-biased at a current density of −10 μA/mm | 12-09-2010 |
Chieh-Lung Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110111539 | METHOD OF MANUFACTURING LIGHT EMITTING DIODE PACKAGE - A method of manufacturing a light emitting diode (LED) package includes disposing at least one LED chip on a first surface of a lead frame, and the LED chip is connected to the lead frame. At least one heat dissipation area corresponding to the LED chip is defined on a second surface of the lead frame. A thermal conductive material is disposed in the heat dissipation area. The thermal conductive material directly comes into contact with the lead frame. A solidification process is performed to solidify the thermal conductive material and form a plurality of heat dissipation blocks. The heat dissipation blocks directly come into contact with the lead frame, and the solidification process is performed at a temperature substantially lower than 300° C. | 05-12-2011 |
| 20110127563 | DIE-BONDING METHOD OF LED CHIP AND LED MANUFACTURED BY THE SAME - A die-bonding method is suitable for die-bonding a LED chip having a first metal thin-film layer to a substrate. The method includes forming a second metal thin film layer on a surface of the substrate; forming a die-bonding material layer on the second metal thin film layer; placing the LED chip on the die-bonding material layer with the first metal thin film layer contacting the die-bonding material layer; heating the die-bonding material layer at a liquid-solid reaction temperature for a pre-curing time, so as to form a first intermetallic layer and a second intermetallic layer; and heating the die-bonding material layer at a solid-solid reaction temperature for a curing time, so as to perform a solid-solid reaction. The liquid-solid reaction temperature and the solid-solid reaction temperature are both lower than 110° C., and a melting point of the first and second intermetallic layers after the solid-solid reaction is higher than 200° C. | 06-02-2011 |
Chih-Huang Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110241253 | METHOD FOR MANUFACTURING COBALT ALLOY-BASED CERAMIC COMPOSITE SPUTTERING TARGET - A method for manufacturing a cobalt (Co) alloy-based ceramic composite sputtering target is provided. A cobalt ingot and a chromium (Cr) ingot are melted in vacuum and then nebulized to form a cobalt-chromium (CoCr) alloy powder. Additionally, a ceramic powder and a platinum powder are wetly mixed to form a platinum-ceramic (Pt-ceramic) slurry, in which the ceramic powder is applied onto the platinum powder's surface uniformly. Next, the CoCr alloy powder and the Pt-ceramic slurry are wetly mixed to form a CoCrPt-ceramic slurry. Thereafter, the CoCrPt-ceramic slurry is dried, molded and compressed to form the cobalt alloy-based ceramic composite sputtering target. The resulted cobalt alloy-based ceramic composite sputtering target, which has a fine and dense structure, uniform composition and lower magnetic permeability, is beneficial to a magnetron sputter deposition process, as well as a film sputtering process used in the magnetic recording industry. | 10-06-2011 |
| 20120068279 | DOMAIN WALL ASSISTED SPIN TORQUE TRANSFER MAGNETRESISTIVE RANDOM ACCESS MEMORY STRUCTURE - A semiconductor memory device includes a first ferromagnetic layer magnetically pinned and positioned within a first region of a substrate; a second ferromagnetic layer approximate the first ferromagnetic layer; and a barrier layer interposed between the first ferromagnetic layer and the first portion of the second ferromagnetic layer. The second ferromagnetic layer includes a first portion being magnetically free and positioned within the first region; a second portion magnetically pinned to a first direction and positioned within a second region of the substrate, the second region contacting the first region from a first side; and a third portion magnetically pinned to a second direction and positioned within a third region of the substrate, the third region contacting the first region from a second side. | 03-22-2012 |
Chin-Chun Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100212686 | CYLINDER-TYPE COSMETIC CONTAINER STRUCTURE - The present invention relates to an improved structure for a cylinder-type cosmetic container, which is structured from an upper case, a lower case and a cover which covers one side of the upper and lower cases. The upper and lower cases respectively retain an inner housing, lower two sides extending therefrom are respectively provided with stop strips, and at least one slide groove is provided distant from end areas of the stop strips. Moreover, the cases are provided with drawers which mutually insert into the slide grooves, and two sides at a tail end of each of the drawers are provided with protruding portions which insert into the slide grooves enabling the drawers to be held firm within the housings using the protruding portions. Accordingly, the advantages of enabling the drawers to move more steadily and firmly, and preventing swaying thereof are achieved. | 08-26-2010 |
Ching-Ming Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110205762 | INTEGRATED-TYPE HIGH STEP-UP RATIO DC-AC CONVERSION CIRCUIT WITH AUXILIARY STEP-UP CIRCUIT - An integrated-type high step-up ratio DC-AC conversion circuit with an auxiliary step-up circuit applies to converting a low DC voltage of alternative energy into a high AC voltage. The conversion circuit uses an isolated Cuk integration unit and an auxiliary step-up unit to form a multi-phase input and uses parallel charging and cascade discharging to boost the DC voltage in the DC side with a low voltage power switches and low duty cycle and then converts the boosted DC voltage into AC voltage. The auxiliary step-up unit not only shares the entirety of power but also exempts the DC-side circuit from using high voltage power switches, whereby the cost of elements is reduced. Further, the conversion circuit can decrease the switching loss and conduction loss of the DC-side switches and promote the efficiency of the circuit. | 08-25-2011 |
Ching-Wen Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080320199 | MEMORY AND CONTROL APPARATUS FOR DISPLAY DEVICE, AND MEMORY THEREFOR - A memory and control apparatus and a memory for a display device are provided. The memory and control apparatus includes a memory, a sense-latch circuit, and a timing and memory controlling apparatus. The memory is used for storing data. The memory has a display data bus and a general data bus. The sense-latch circuit is used for sensing and latching the data on the display data bus. The timing and memory controlling apparatus is used for controlling the memory, so as to make the display data represented on the display data bus, and to make the sense-latch circuit outputting the data on the display data bus. When the display device intends to store the data in the memory, the data on the general data bus is stored to the memory. | 12-25-2008 |
Chi Shao Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090274049 | NON-BLOCKED NETWORK SYSTEM AND PACKET ARBITRATION METHOD THEREOF - A non-blocked network system and a packet arbitration method thereof are provided to dynamically adjust packet arbitration policy, thereby avoiding the congestion of packet traffic. The non-blocked network system includes a switch network, a source device and a target device. The switch network includes at least a first switch unit and a second switch unit. A first path and a second path connect between the first and second switch units. The target device is coupled to the second switch unit, and the source device is coupled to the first switch unit. Before issuing a first packet to the target device via the first path, the source device issues a corresponding token of the first packet to the second switch unit via the second path, so as to inform the second switch unit that the first packet will pass the first path soon. The second switch unit dynamically adjusts its packet arbitration policy according to the token, so as to determine the forwarding sequence of a second packet to be forwarded on the first path. | 11-05-2009 |
| 20090323532 | NETWORK SYSTEM WITH QUALITY OF SERVICE MANAGEMENT AND ASSOCIATED MANAGEMENT METHOD - A network system with QoS management and an associated management method are provided. The network system comprises a switch network, a target device, and at least a source device for issuing a packet to the target device via the switch network. The switch network comprises a flow control unit, a switch unit and a scheduling unit. The flow control unit determines whether to output a high priority packet according to a target priority level and a high priority bandwidth quota of the source device, and directly outputs a low priority packet. The switch unit determines a packet forwarding sequence according to a packet arbitration policy. The scheduling unit determines the sequence for packets to enter the target device. The scheduling unit updates the target priority level as the priority level of a packet entering the target device, and informs the flow control unit of the updated target priority level. | 12-31-2009 |
Da-Wei Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100314709 | LATCH-UP PREVENTION STRUCTURE AND METHOD FOR ULTRA-SMALL HIGH VOLTAGE TOLERANT CELL - A latch-up prevention structure and method for ultra-small high voltage tolerant cell is provided. In one embodiment, the integrated circuit includes an input and/or output pad, a floating high-voltage n-well (HVNW) connected to the input and/or output pad through a P+ in the floating HVNW and also connected to a first voltage supply, a low-voltage n-well (LVNW) connected to a second voltage supply through a N+ in the LVNW, a HVNW control circuit, and a guard-ring HVNW, where the first voltage supply has higher voltage level than the second voltage supply, guard-ring HVNW is inserted in between the floating HVNW and LVNW to prevent a latch-up path between a P+ in HVNW and N+ in LVNW by using the HVNW control circuit that controls the guard-ring HVNW's voltage level. The guard-ring HVNW's voltage level is matched by the floating HVNW's voltage level. | 12-16-2010 |
| 20100328827 | ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUITS, INTEGRATED CIRCUITS, SYSTEMS, AND OPERATING METHODS THEREOF - An electrostatic discharge (ESD) protection circuit coupled with an input/output (I/O) pad. The ESD protection circuit includes a clamp field effect transistor (FET) coupled between a first supply voltage and a second supply voltage. An inverter includes an input end and an output end. The output end of the inverter is coupled with a gate of the clamp FET. A RC time constant circuit is disposed between the first supply voltage and the second supply voltage. A current mirror includes a first transistor. The current minor is coupled between the input end of the inverter and the second supply voltage. A circuit is coupled with the input end of the inverter. The circuit is capable of outputting a voltage state on the input end of the inverter that is capable of substantially turning off the clamp FET while the I/O pad is subjected to a latch-up test using a negative current. | 12-30-2010 |
| 20110051298 | ESD IMPROVEMENT WITH DYNAMIC SUBSTRATE RESISTANCE - In some embodiments, an electrostatic discharge (ESD) protection circuit includes a substrate resistance control circuit coupled to a body of a first NMOS transistor. The substrate resistance control circuit increases a resistance of the body of the first NMOS transistor during an ESD event. The first NMOS transistor has a drain coupled to an input/output (I/O) pad and a gate coupled to a first voltage source. The first voltage source is set at ground potential. | 03-03-2011 |
De-Wei Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110119430 | METHODS FOR MEASURING USABLE LIFESPAN AND REPLACING AN IN-SYSTEM PROGRAMMING CODE OF A MEMORY DEVICE, AND DATA STORAGE SYSEM USING THE SAME - A data storage system comprises a host and a flash memory device having a non-non-volatile memory. A controller of the flash memory device calculates an average erase count of the flash memory to obtaining a remaining period of time indicating usable lifespan of the flash memory device. The host obtains an index by comparing the average erase count with a first threshold and determines a performance capability status for the flash memory device. The performance capability status is set to a first status when the average erase count exceeds the first threshold. The host generates an indication based on the performance capability status and performs a limp function responsive to the first status. The limp function loads a predetermined in-system programming code for replacing an original one to configure a minimum number of at least some spare blocks of the flash memory reserved and used for data update operations. | 05-19-2011 |
Horng Goung Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120068940 | ELECTRONIC DEVICE - An electronic device includes a housing, an optical touch module, and a detecting unit. The housing includes a first body and a second body, and an angle is formed between the first body and the second body. The optical touch module executes a positioning function by sensing signals. The detecting unit is configured to the optical touch module, and is used for detecting the angle. When the angle is smaller than a predetermined angle, the detecting unit instructs the optical touch module to pause executing the positioning function, so as to avoid false position determinations by the optical touch module. | 03-22-2012 |
Hsiang-Ling Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090239809 | Process For Preparing Peptide Products For Promoting Cholecystokinin Secretion And Use Of The Peptide Products - A process for producing a peptide product having cholecystokinin secretion promoting effect, said process comprising hydrolyzing soybean residues with one or more proteases so that the peptide product having cholecystokinin secretion promoting effect is obtained. Also disclosed is the composition containing the peptide product and the use thereof. | 09-24-2009 |
Hung-Ching Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110200066 | CHIP MODULE PACKAGE STRUCTURE - A chip module package structure applied to an optical input device includes a cover body, a first chip module, and a second chip module. The first chip module and the second chip module are respectively combined with the cover body, the first chip module has an optical source, and the second chip module has an optical sensor. Further, the optical source and the optical sensor form a preset relative spatial position relation, such that a part of light emitted by the optical source is received by the optical sensor after at least one reflection. | 08-18-2011 |
Kao-Ting Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110079820 | DEVICE WITH SELF ALIGNED STRESSOR AND METHOD OF MAKING SAME - A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material. | 04-07-2011 |
Kou-Rueh Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090026470 | SUPER THIN SIDE-VIEW LIGHT-EMITTING DIODE (LED) PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a side-view LED package is provided. A chip carrier is provided. An opaque housing is bonded with the chip carrier. An LED chip electrically connects the chip carrier by performing a chip-bonding process and the opaque housing has a cavity for accommodating the LED chip. A transparent encapsulant is disposed in the cavity wherein the transparent encapsulant has a side-view light output surface uncovered by the opaque housing and light emitted from the LED chip is output via the side-view light output surface. A portion of the opaque housing and a portion of the transparent encapsulant are removed for reducing an overall thickness of the opaque housing such that a top surface of the transparent encapsulant is uncovered by the opaque housing beside the side-view light output surface. An opaque protective layer is formed on the top surface of the transparent encapsulant and the opaque housing. | 01-29-2009 |
| 20100084683 | LIGHT EMITTING DIODE PACKAGE AND FABRICATING METHOD THEREOF - A light emitting diode (LED) package is provided. The LED package includes a carrier, a package housing, a strength enhancement structure, an ESD protector and an LED chip. The carrier has a first surface and a second surface. The carrier includes a first electrode and a second electrode, wherein a gap is between the first electrode and the second electrode. The package housing is disposed on the carrier and has a first aperture and a second aperture. The first surface is exposed by the first aperture while the second surface is exposed by the second aperture. The strength enhancement structure is disposed at the gap. The ESD protector is disposed on the carrier and located within the second aperture. The LED chip is disposed on the carrier and located within the first aperture, wherein the ESD protector and the LED chip is electrically connected to the carrier. | 04-08-2010 |
Rui-Yang Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100271360 | Bi-Stable Display, Frame Updating Method and Timing Control Method thereof - A bi-stable display, frame updating method and timing sequence controlling method thereof are disclosed. The frame updating method of the bi-stable display includes the steps of comparing a difference of source driver output voltages of adjacent frames of image updating period with a preset threshold, and determining parameter value of each transitional state of the adjacent frames when the difference equal or greater than the preset threshold for controlling level of source driver output voltage. Accordingly, the effects such as signal interference, reduction of image quality resulted from switching between high voltage levels directly and rapidly and excessive power consumption may be eliminated. | 10-28-2010 |
Shang-Hong Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100183241 | RESTORATION METHOD FOR BLURRED IMAGES USING BI-LEVEL REGIONS - A blind image restoration method restores a motion blurred image and a blur kernel is estimated based on an intrinsic bi-level image region of the motion blurred image. In addition, the blur kernel is iteratively estimated. When the blur kernel is iteratively estimated, bi-level image priors are introduced to achieve better image restoration. | 07-22-2010 |
| 20110128354 | SYSTEM AND METHOD FOR OBTAINING CAMERA PARAMETERS FROM MULTIPLE IMAGES AND COMPUTER PROGRAM PRODUCTS THEREOF - Systems and methods for obtaining camera parameters from images are provided. First, a sequence of original images associated with a target object under circular motion is obtained. Then, a background image and a foreground image corresponding to the target object within each original image are segmented. Next, shadow detection is performed for the target object within each original image. A first threshold and a second threshold are respectively determined according to the corresponding background and foreground images. Each original image, the corresponding background image, the first and second threshold are used for obtaining silhouette data and feature information associated with the target object within each original image. At least one camera parameter is obtained based on the entire feature information and the geometry of circular motion. | 06-02-2011 |
| 20110150337 | METHOD AND SYSTEM FOR AUTOMATIC FIGURE SEGMENTATION - A method for achieving segmentation of a picture according to one aspect of the present invention comprises: determining a first foreground of a picture based on a predetermined mask; applying Gaussian Mixture Models with weighted data (GMM-WD) to the first foreground to generate a second foreground; determining a first background of the picture based on the second foreground; applying the GMM-WD to the first background to generate a second background; and determining an unknown region based on the second background and the second foreground. | 06-23-2011 |
| 20110229044 | HIERARCHICAL MOTION DEBLURRING METHOD FOR SINGLE IMAGE - A hierarchical motion deblurring method for a single image is provided. In the method, a blur kernel of a target image is calculated and a multi-scale representation for representing the target image and the blur kernel is constructed. Then, a gradient attenuation function and a strong edge suppression function are applied to a residual Richardson-Lucy algorithm, so as to iteratively calculate a residual image between the blur kernel and the target image represented by the representation in each scale and restore the residual image to obtain a first restored image and a second restored image. Finally, the two restored images are compared so as to obtain a motion deblurring image. | 09-22-2011 |
| 20110310237 | Facial Expression Recognition Systems and Methods and Computer Program Products Thereof - A facial expression recognition system includes a facial database, an image capture unit, an expression recognition data generation unit and an expression recognition unit. The facial database includes a plurality of expression information and expression features of optical flow field, wherein each of the expression features of optical flow field corresponds to one of the expression information. The image capture unit captures a plurality of facial images. The expression recognition data generation unit is coupled to the image capture unit and the facial database for receiving a first facial image and a second facial image from the image capture unit and calculating an expression feature of optical flow field between the first facial image and the second facial image corresponding to each of the expression information. The expression recognition unit is coupled to the expression recognition data generation unit for determining a facial expression corresponding to the first and second facial images according to the calculated expression feature of optical flow field for each of the expression information and the variation features in optical flow in the facial database. | 12-22-2011 |
Sheng-Tang Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100097710 | FIXED FOCUS LENS - A fixed focus lens includes, numbered in order of location from an object side to an image side, a first lens, a second lens, a third lens, and a fourth lens. The first lens is a biconvex lens with a positive refractive power, and the second lens is a convex-concave lens with a negative refractive power. The third lens is a concave-convex lens with a positive refractive power, and the fourth lens is an aspherical lens having a negative refractive power in the centre portion thereof and a positive refractive power at the periphery portion thereof. The fixed focus lens satisfies the condition: 1.0>|(1/r | 04-22-2010 |
Sung-Ming Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100253259 | Driving Method and Related Driving Device for a Motor - A driving method for a motor includes sensing variation of magnetic pole of a rotator of the motor, to generate a magnetic pole sensing signal, determining dead zone of the motor according to the magnetic pole sensing signal, to generate a determination result, and adjusting voltage outputted to a coil of the rotator according to the determination result. | 10-07-2010 |
| 20110121770 | Method and Device for Driving a Two-Phase Brushless Motor - A method for driving a two-phase brushless motor is disclosed. The motor includes a rotator with permanent magnetism and a stator including a first coil and a second coil. The method includes activating the two-phase brushless motor, detecting an output voltage of a disabled coil of the first coil and the second coil to generate a detection result, comparing the detection result and a reference voltage to determine a commutation time point between the first coil and the second coil, generating a commutation signal according to the commutation time point, and driving the two-phase brushless motor according to the commutation time point. | 05-26-2011 |
| 20120007526 | Rotation Speed Control Circuit, Rotation Speed Control Method and Fan System - A rotation speed control circuit for controlling a rotation speed of a fan includes: a rotation speed detector, for generating a rotation speed voltage according to a rotation speed signal corresponding to the rotation speed; a sample and hold element, coupled to the rotation speed detector, for sampling and storing the rotation speed voltage; an error amplifier, coupled to the sample and hold element, for controlling a voltage of a filter capacitor according to the rotation speed voltage and a reference voltage, to adjust an error voltage; and a pulse width modulation signal generator, coupled to the filter capacitor, for generating a pulse width modulation signal according to the error voltage and a triangle wave. | 01-12-2012 |
Tung-Ming Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110169106 | MICRO ELECTRONIC MECHANICAL SYSTEM STRUCTURE AND MANUFACTURING METHOD THEREOF - A micro electronic mechanical system structure and a manufacturing method thereof are provided. A substrate has a plurality of conductive regions is provided. A dielectric layer is formed on the substrate. A plurality of openings and recesses are formed in the dielectric layer, wherein the openings expose the conductive regions. The recesses are located between the openings. A conductive layer is formed on the dielectric layer and the openings and the recesses are filled with the conductive layer. The conductive layer is patterned to form a plurality of strips of the first conductive patterns on the dielectric layer and a second conductive pattern on the sidewall and the bottom of each recess, wherein the first conductive patterns are connected with each other through the second conductive patterns. The dielectric layer is removed. The second conductive patterns between the first conductive patterns are removed. | 07-14-2011 |
Wan-Chen Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090052483 | OPTOELECTRONIC SEMICONDUCTOR PACKAGE AND METHOD FOR ATTACHING HEAT DISSIPATION ELEMENT THERETO - An optoelectronic semiconductor package for packaging a heat source capable of emitting light includes a base, a seal member, and a plurality of heat-dissipation elements. The base carries and touches the heat source and has a plurality of openings formed thereon, and the seal member is used to seal the heat source on the base. Each of the heat-dissipation elements is inserted in one of the corresponding openings, and the heat-dissipation element placed in the corresponding opening is deformed to result in a tight coupling between the heat-dissipation element and the base. | 02-26-2009 |
Wei-Chi Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120102081 | LOW-LATENCY ARC-TANGENT CALCULATION STRUCTURE AND CALCULATION METHOD THEREOF - The present invention provides a low-latency arc-tangent calculation structure and a calculation method thereof. The arc-tangent calculation structure comprises two lookup tables, a subtractor, a sign comparator, a numerical comparator and a shift encoder. The present invention divides the coordinate system into a plurality of sectors for simplifying the lookup tables. The first lookup table is used to perform logarithmic transformation so as to replace a divider with a subtractor. The second lookup table integrates an exponentiation table and an angle table to translate the output of the subtractor into arc-tangent value θ. Then, θ is shifted to a correct angle according to the output of the shift encoder. | 04-26-2012 |
Yi-Ying Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100142048 | LIGHT SOURCE MODULE FOR GENERATING POLARIZED LIGHT - A light source module for generating polarized light includes a light emitting element, a reflector, and an optical element. The light emitting element generates a light ray, and the reflector reflects the light ray towards the optical element. The optical element includes a light splitting face and a reflection face. The light splitting face receives the light ray, and an angle between the light splitting face and the incident light ray is at about a Brewster's Angle. After the light ray is irradiated to the light splitting face, the light ray is divided into a refraction light and a reflection light. The reflection face reflects the refraction light, and the reflection face is substantially perpendicular to a path of the refraction light. Therefore, a light source with a high degree of polarization is realized by a design of the light splitting face and the reflection face. | 06-10-2010 |
Yuan-Tai Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110109415 | INDUCTOR STRUCTURE - The present invention discloses an improved inductor structure, which applies to the semiconductor field, particularly to a system-on-chip, and which comprises a substrate, a first conductive patterned film, and a first insulating layer formed between the substrate and the first conductive patterned film. The substrate has a base and an accommodation portion formed in the base. A magnetic material is filled into the accommodation portion to form a magnetic region. The accommodation portion is fabricated via etching the base or drilling a through-hole in the base. A plurality of conductive wires is arranged in a spiral way to form the first conductive patterned film. A protective layer covers the surface of the first conductive patterned film and isolates the contact of the first conductive patterned film and moisture. | 05-12-2011 |
| 20110175698 | INDUCTOR WITH FERROMAGNETIC METAL FILM - The present invention discloses an inductor with a ferromagnetic metal film, which comprises an upper magnetic material layer, a lower magnetic material layer, and a metallic conducting wire. The metallic conducting wire is sandwiched between the upper magnetic material layer and the lower magnetic material layer. Either the upper magnetic material layer or the lower magnetic material layer is a ferromagnetic metal film. The ferromagnetic metal film can effectively converge the magnetic fluxes and enhance the inductance of the inductor. Thus is reduced the thickness of the upper magnetic material layer or lower magnetic material layer and achieved a thin drum inductor. | 07-21-2011 |
Yu-Sheng Lai, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100073062 | Voltage Control Oscillator Without Being Affected by Variations of Process and Bias Source - A VCO includes a reference current module and a clock signal generating module. The reference current module generates a reference current according to a reference voltage. The clock signal generating module generates a clock signal according to the reference current. The reference current module utilizes the negative feed-back mechanism to keep the generated reference current at the predetermined size without being changed with the variation of the process and the bias source. | 03-25-2010 |
| 20120056652 | DLL circuit with dynamic phase-chasing function and method thereof - A method of dynamically adjusting phase-chasing speed for increasing efficiency of a DLL circuit includes detecting an overall loop delay for an input clock signal in the DLL circuit, obtaining an optimal divisor according to the overall loop delay, and in the phase-locking period of the DLL circuit, dividing the frequencies of the input clock signal and a feedback clock signal corresponding to the input clock signal according to the optimal divisor. | 03-08-2012 |