Patent application number | Description | Published |
20100240189 | Methods of Fabricating Semiconductor Devices - Methods of fabricating semiconductor devices are provided including forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein. A metal pattern is formed in the opening. An oxidization process is performed on the metal pattern to form a conductive metal oxide pattern, and the conductive metal oxide pattern is planarized. Related semiconductor devices are also provided. | 09-23-2010 |
20110092038 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a three dimensional semiconductor memory device and a method of fabricating the same. The method includes forming a stepwise structure by using mask patterns and a sacrificial mask pattern formed on the mask patterns as a consumable etch mask. | 04-21-2011 |
20110204421 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a three dimensional semiconductor memory device and a method of fabricating the same. The method includes forming a stepwise structure by using mask patterns and a sacrificial mask pattern formed on the mask patterns as a consumable etch mask. | 08-25-2011 |
20120026740 | LIGHTING APPARATUS - A lighting apparatus is broadly disclosed and embodied herein. The lighting apparatus may include a heat sink, a first reflector provided over the heat sink, a light emitting module provided at the first reflector, an enclosure provided over the heat sink to surround the light emitting module, and a second reflector provided over the light emitting module. At least a portion of the light emitted from the light emitting module may be reflected at least in a direction a prescribed angle below a horizontal plane of the light emitting module. | 02-02-2012 |
20120033423 | LIGHTING APPARATUS - A lighting apparatus is broadly disclosed and embodied herein. The lighting apparatus may include a heat sink, a first reflector provided over the heat sink, a light emitting module provided at the first reflector, an enclosure provided over the heat sink to surround the light emitting module, and a second reflector provided over the light emitting module. At least a portion of the light emitted from the light emitting module may be reflected at least in a direction a prescribed angle below a horizontal plane of the light emitting module. | 02-09-2012 |
20120070944 | Methods of Manufacturing Three Dimensional Semiconductor Devices - Provided are methods of manufacturing a three dimensional semiconductor device. The method includes providing a substrate including a cell array region and a peripheral circuit region, forming a peripheral structure on the peripheral circuit region, forming a cell structure being thicker than the peripheral structure in the cell array region, forming an interlayer dielectric to cover the peripheral structure and the cell structure, forming a polishing stop layer on the interlayer dielectric, and planarizing the interlayer dielectric using the polishing stop layer as a planarization stop. | 03-22-2012 |
20120106147 | LIGHTING APPARATUS - A lighting apparatus may include a case, a circuit board, a light source including a light emitting diode (LED), and a light controlling layer to reflect light from the light source toward an inside of the case to prevent the light from being directly radiated to an outside of the case. | 05-03-2012 |
20120248525 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided. | 10-04-2012 |
20120300480 | LIGHTING APPARATUS - A lighting apparatus may include a body having a light emitting module with a light emitting diode (LED), a support member to support the body at a plurality of different tilt positions relative to the support member, and a connection member provided to the body to connect the body to the support member. The connection member may include a first projection that extends to a first height and a second projection that extends to a second height. The body may be provided in a first tilt position relative to the support member when the first projection contacts the end portion of the support member without the second projection contacting the support member, and the body is provided in a second tilt position relative to the support member when the second projection contacts the end portion of the support member. | 11-29-2012 |
20120300481 | LIGHTING APPARATUS - A lighting apparatus may include a body having a substrate, and a light emitting module with a light emitting diode (LED) mounted to the substrate. A connection member may be provided to the body, and a support member may be mounted to the connection member at a predetermined tilt angle thereto to adjust a light directing angle of the body. | 11-29-2012 |
20130017629 | METHODS OF MANUFACTURING THREE-DIMENSIONAL SEMICONDUCTOR DEVICESAANM Pyo; MyungjungAACI Hwaseong-siAACO KRAAGP Pyo; Myungjung Hwaseong-si KRAANM Kim; Hyo-JungAACI SeoulAACO KRAAGP Kim; Hyo-Jung Seoul KRAANM Lim; JongHeunAACI Hwaseong-siAACO KRAAGP Lim; JongHeun Hwaseong-si KRAANM Kim; KyunghyunAACI SeoulAACO KRAAGP Kim; Kyunghyun Seoul KRAANM Yoon; ByoungmoonAACI Suwon-siAACO KRAAGP Yoon; Byoungmoon Suwon-si KRAANM Han; JaHyungAACI Suwon-siAACO KRAAGP Han; JaHyung Suwon-si KR - According to example embodiments, a methods includes forming a peripheral structure including peripheral circuits on a peripheral circuits region of a substrate, recessing a cell array region of the substrate to form a concave region having a bottom surface lower than a top surface of the peripheral structure, forming a stacked layer structure conformally covering the concave region, the stacked layer structure including a plurality of layers sequentially stacked and having a lowest top surface in the cell array region and a highest top surface in the peripheral circuits region, forming a planarization stop layer that conformally covers the stacked layer structure, and planarizing the stacked layer structure using the planarization stop layer in the cell array region as a planarization end point to expose top surfaces of the thin layers between the cell array region and the peripheral circuits region simultaneously with a top surface of the peripheral structure. | 01-17-2013 |
20130039047 | LIGHTING APPARATUS - This invention relates to lighting apparatuses, and more particularly to a lighting apparatus in which an LED module is detachably mounted to make replacement and repair easy, and which enables to mount the same to fit to different sizes of spaces by a combination of assembly of a plurality of LED modules. | 02-14-2013 |
20130092872 | COMPOSITIONS FOR ETCHING AND METHODS OF FORMING A SEMICONDUCTOR DEVICE USING THE SAME - Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound. The silicon compound includes a silicon atom, an atomic group having an amino group combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided. | 04-18-2013 |
20130107519 | LIGHTING APPARATUS | 05-02-2013 |
20130134493 | VERTICAL CHANNEL MEMORY DEVICES WITH NONUNIFORM GATE ELECTRODES - A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers. | 05-30-2013 |
20130241037 | Semiconductor Devices Having Metal Oxide Patterns - Methods of fabricating semiconductor devices are provided including forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein. A metal pattern is formed in the opening. An oxidization process is performed on the metal pattern to form a conductive metal oxide pattern, and the conductive metal oxide pattern is planarized. Related semiconductor devices are also provided. | 09-19-2013 |
20140004676 | VERTICAL CHANNEL MEMORY DEVICES WITH NONUNIFORM GATE ELECTRODES AND METHODS OF FABRICATING THE SAME | 01-02-2014 |