| Patent application number | Description | Published |
|---|
| 20080209159 | MEMORY ACCESS METHOD USING THREE DIMENSIONAL ADDRESS MAPPING - A memory access method includes: obtaining a, b, and c from a program code for accessing a memory with a triple loop in a program, a being a number of values which an inner-most loop variable of the triple loop may have, b being a number of values which a middle loop variable of the triple loop may have, and c being a number of values which an outer-most loop variable of the triple loop may have; obtaining a starting address of the memory accessed by the triple loop; and obtaining an a×b×c number of addresses of the memory accessed by the triple loop using the starting address and a function. | 08-28-2008 |
| 20090073163 | Apparatus for and method of processing vertex - An apparatus for and method of processing a vertex in relation to 3 dimensional (3D) graphics pipeline are provided. According to the method, while a processor processes vertex data in units of batches, vertex data corresponding to a batch to be processed next is extracted and temporarily stored in a buffer independently of the processor. If the processor finishes processing of the current batch, the batch stored in the buffer is output so that the processor can immediately process the batch. | 03-19-2009 |
| 20090089551 | Apparatus and method of avoiding bank conflict in single-port multi-bank memory system - Provided are a method and apparatus for avoiding bank conflict. A first instruction that is one of access instructions that are predicted to cause the bank conflict is replaced with a second instruction by changing an execute timing of the first instruction to a timing prior to the execute timing of the first instruction so as for the access instructions not to cause the bank conflict. Next, a load/store unit that is scheduled to access the bank according to the first instruction accesses the bank and reads out a data from the bank at an execute timing of the second instruction, and after that, the load/store unit is allowed to be inputted the read data at the execute timing of the first instruction. Accordingly, although the access instructions that are predicted to cause the bank conflict are allocated to the load/store units, the bank conflict can be prevented, so that it is possible to avoid deterioration in performance due the occurrence of the bank conflict. | 04-02-2009 |
| 20100115141 | Processor and method for controlling memory - A processor and a memory controlling method. The processor enables a Scratch-Pad Memory (SPM) to prepare data that a processor core intends to process, using a data management unit including a data cache, thereby increasing a data processing rate. | 05-06-2010 |
| 20100164949 | System and method of rendering 3D graphics - A system and method of rendering three-dimensional (3D) graphics. The system for rendering 3D graphics may include a plurality of cores including a scratch pad memory, a first memory to perform a control flow, a second memory for loop acceleration, and a shared memory to interpolate with the plurality of cores. | 07-01-2010 |
| 20110099555 | Reconfigurable processor and method - Disclosed are a reconfigurable processor and processing method, a reconfiguration control apparatus and method, and a thread modeler and modeling method. A memory area of a reconfigurable processor may be divided into a plurality of areas, and a context enabling a thread process may be stored in respective divided areas, in advance. Accordingly, when a context switching is performed from one thread to another thread, the other thread may be executed by using information stored in an area corresponding to the other thread. | 04-28-2011 |
| 20110164038 | APPARATUS AND METHOD FOR TILE-BASED RENDERING - A tile-based rendering apparatus and method is provided. Vertex data sorted based on a tile unit may be stored in a scene buffer and be rendered. Among the stored vertex data, vertex data used several times for rendering may be temporarily stored in a memory or a cache. Vertex data having a probability of being read several times from the scene buffer may be temporarily stored in another memory. | 07-07-2011 |
| 20110193862 | METHOD AND SYSTEM FOR EARLY Z TEST IN TITLE-BASED THREE-DIMENSIONAL RENDERING - A method and system for an early Z test in a tile-based three-dimensional rendering is provided. In the method and system for an early Z test, a portion which is not displayed to a user is removed prior to performing a rasterization process, and thereby performing the 3D rendering efficiently. The method includes segmenting a scene into tiles for performing a rendering with respect to a triangle; selecting a first tile of the tiles, which has a tile Z value less than a minimum Z value of the triangle; and performing the rendering with respect to the triangle in remaining tiles excluding the selected first tile of the tiles. | 08-11-2011 |
