Patent application number | Description | Published |
20080225595 | CHARGE TRAP TYPE NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF - A method of programming a charge trap type non-volatile memory device includes applying a program pulse to a selected memory cell, applying a detrap pulse to the selected memory cell, and applying a program verify pulse to the memory cell. The charge trap type non-volatile memory device includes a memory cell array including a charge trap memory cell, and a high voltage generator for supplying a detrap pulse to the charge trap memory cell. | 09-18-2008 |
20080230830 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer. | 09-25-2008 |
20090296476 | Flash Memory Device and Method for Manufacturing the Same - A flash memory device includes a substrate, a cell stack having a semiconductor layer, in which junction areas for setting areas therebetween to channel areas are formed in a shape of a stripe, and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked. The flash memory device further includes an array of gate columns penetrating through the cell stack, perpendicular to the substrate and cutting through the junction areas to dispose the junction areas at both sides thereof, and a trap layered stack introduced into an interface between the gate column and the cell stack to store charge. | 12-03-2009 |
20100190315 | METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - There is provided a method of manufacturing a semiconductor memory device. According to the method, a tunnel insulating layer and a charge trap layer are formed in a cell region of a semiconductor substrate defining the cell region and a peripheral region. A gate insulation layer and a first conductive layer are formed over the semiconductor substrate of the peripheral region. A blocking insulating layer is formed on the charge trap layer of the cell region and the first conductive layer of the peripheral region. A second conductive layer is formed over the entire surface including the blocking insulating layer, thereby forming a capacitor having a stack structure of the first conductive layer, the blocking insulating layer, and the second conductive layer. | 07-29-2010 |
20100308398 | Flash Memory Device With an Array of Gate Columns Penetrating Through a Cell Stack - A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge. | 12-09-2010 |
20110204430 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer. | 08-25-2011 |
20120217572 | Flash Memory Device With an Array of Gate Columns Penetrating Through a Cell Stack - A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge. | 08-30-2012 |
20130064029 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - An operating method of a semiconductor memory device includes precharging a channel region of a program-inhibited cell of first memory cells coupled to a first word line, selected from a first one of word line groups between a drain select line and a source select line, to a first level based on first data; performing a first program operation for storing the first data in the first memory cells; precharging the channel region of a program-inhibited cell of second memory cells coupled to a second word line, selected from a second one of the word line groups, to a second level based on second data to be stored in the second memory cells; and performing a second program operation for storing the second data in the second memory cells. | 03-14-2013 |