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Kyoung Hwan
Kyoung Hwan Cho, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090097219 | MAGNETIC AND DIELECTRIC COMPOSITE ELECTRONIC DEVICE - There is a provided a magnetic and dielectric composite electronic device, comprising: a first region with a plurality of magnetic material sheets being layered; a second region with a plurality of dielectric material sheets being layered; and a third region as a middle layer interposed between the first region and the second region, including a Zn—Ti based material to prevent diffusion of the materials during co-firing of the first region and the second region, and the first region, the second region and the third region are integrally formed in a single body. In accordance with the present invention, the low pass filter including the function of the varistor is realized to obtain the EMI function and the ESD control effect. Furthermore, the one chip electronic device having the composite functions is manufactured by a simple process, and the interdiffusion between the different materials forming the magnetic and the dielectric parts is prevented to secure the durability and electrical characteristics of the product. | 04-16-2009 |
Kyoung Hwan Kim, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080264566 | Apparatus and method for removing a photoresist structure from a substrate - In an apparatus and method for removing a photoresist structure from a substrate, a chamber for receiving the substrate includes a showerhead for uniformly distributing a mixture of water vapor and ozone gas onto the substrate. The showerhead includes a first space having walls and configured to receive the water vapor, and a second space connected to the first space so that the water vapor is supplied to and partially condensed into liquid water on one or more walls of the first space. Ozone gas and water vapor without liquid water may be supplied to the second space to form the mixture therein. The showerhead may be heated to vaporize the liquid water on a given surface of the first space. | 10-30-2008 |
| 20110052278 | FUSING UNIT AND IMAGE FORMING APPARATUS HAVING THE SAME - A fusing unit which includes a pressure member to be elastically supported on an outer peripheral surface of a heating roller while coming into surface contact with the outer peripheral surface. The pressure member serves to grind the outer peripheral surface of the heating roller, to maintain a surface roughness of the heating roller at a predetermined level or less. | 03-03-2011 |
Kyoung Hwan Kim, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20110132347 | PORTABLE CHARCOAL GRILL - A portable charcoal grill is disclosed which places charcoal on an internal support mesh located at the bottom of the housing thereof. The portable charcoal grill includes: a fixing string ( | 06-09-2011 |
Kyoung Hwan Kwon, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20090175114 | MULTI-PORT SEMICONDUCTOR MEMORY DEVICE HAVING VARIABLE ACCESS PATHS AND METHOD THEREFOR - A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports. | 07-09-2009 |
| 20100232249 | MULTI-PORT SEMICONDUCTOR MEMORY DEVICE HAVING VARIABLE ACCESS PATHS AND METHOD THEREFOR - A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports. | 09-16-2010 |
| 20110026335 | POWER-UP SIGNAL GENERATION CIRCUIT - A power-up signal generation circuit includes a fixed level transition voltage generation unit, a variable level transition voltage generation unit, a comparison unit, and a selective output unit. The fixed level transition voltage generation unit is configured to generate a fixed level transition voltage changing at a constant level of an external voltage. The variable level transition voltage generation unit is configured to generate a variable level transition voltage changing at a level of an external voltage which varies depending on temperature. The comparison unit is configured to compare the level of the fixed level transition voltage with the level of the variable level transition voltage, and generate a selection signal. The selective output unit is configured to output the fixed level transition voltage or the variable level transition voltage as a power-up signal in response to the selection signal. | 02-03-2011 |
Kyoung Hwan Lim, Gyeongsangnam-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20110247858 | Printed Circuit Board and Method Of Manufacturing The Same - Disclosed herein is a printed circuit board, including: a substrate; a first circuit layer formed on the substrate; a first insulation layer formed on the first circuit layer and having a pattern corresponding to that of the first circuit layer; and a second insulation layer formed on the substrate such that the second insulation layer surrounds the first circuit layer and the first insulation layer formed on the first circuit layer. The printed circuit board is advantageous in that process time and process cost can be reduced because a first insulation layer is used as an etching resist and is included as a part of a printed circuit board even after etching. | 10-13-2011 |
Kyoung Hwan Park, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20080225595 | CHARGE TRAP TYPE NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF - A method of programming a charge trap type non-volatile memory device includes applying a program pulse to a selected memory cell, applying a detrap pulse to the selected memory cell, and applying a program verify pulse to the memory cell. The charge trap type non-volatile memory device includes a memory cell array including a charge trap memory cell, and a high voltage generator for supplying a detrap pulse to the charge trap memory cell. | 09-18-2008 |
| 20080230830 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer. | 09-25-2008 |
| 20090296476 | Flash Memory Device and Method for Manufacturing the Same - A flash memory device includes a substrate, a cell stack having a semiconductor layer, in which junction areas for setting areas therebetween to channel areas are formed in a shape of a stripe, and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked. The flash memory device further includes an array of gate columns penetrating through the cell stack, perpendicular to the substrate and cutting through the junction areas to dispose the junction areas at both sides thereof, and a trap layered stack introduced into an interface between the gate column and the cell stack to store charge. | 12-03-2009 |
| 20100190315 | METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - There is provided a method of manufacturing a semiconductor memory device. According to the method, a tunnel insulating layer and a charge trap layer are formed in a cell region of a semiconductor substrate defining the cell region and a peripheral region. A gate insulation layer and a first conductive layer are formed over the semiconductor substrate of the peripheral region. A blocking insulating layer is formed on the charge trap layer of the cell region and the first conductive layer of the peripheral region. A second conductive layer is formed over the entire surface including the blocking insulating layer, thereby forming a capacitor having a stack structure of the first conductive layer, the blocking insulating layer, and the second conductive layer. | 07-29-2010 |
| 20100308398 | Flash Memory Device With an Array of Gate Columns Penetrating Through a Cell Stack - A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge. | 12-09-2010 |
| 20110204430 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer. | 08-25-2011 |
Kyoung-Hwan Choi, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090110975 | HYDROGEN GENERATOR AND FUEL CELL USING THE SAME - A hydrogen generator and a fuel cell using the same includes: a first container containing an aqueous solution of alkaline metal carbonate or bicarbonate; a second container containing a metal hydride; and a supply unit disposed between the first container and the second container. The hydrogen generator has a high hydrogen generating rate, can provide a fuel cell with a high energy density, and the amount of hydrogen generated thereby is easy to control. | 04-30-2009 |
| 20090169966 | FUEL DIFFUSION UNIT, FUEL SUPPLY UNIT, AND FUEL CELL SYSTEM INCLUDING THE SAME - A fuel diffusion unit including: a fuel diffusion plate; a diffusion sheet disposed on fuel diffusion plate, to evenly distribute a fuel to the fuel diffusion plate; a primary transportation unit disposed on the diffusion sheet; secondary transportation units connected to the primary transportation unit, to distribute the fuel to the fuel from the primary transportation unit to the diffusion sheet. The diffusion sheet has a wetting direction that allows the fuel to flow in a predetermined direction. The fuel diffusion unit can be included in a fuel supply unit and a fuel cell system. | 07-02-2009 |
| 20090176140 | FUEL CELL PROVIDING IMPROVED DISPOSING STRUCTURE FOR UNIT CELLS - A fuel cell including a plurality of unit cells that each includes an anode, an electrolyte membrane, and a cathode. The unit cells are stacked together, such that the unit cells form rows and furrows. The fuel cell can further include an anode frame to support an anode side of the fuel cell stack, and a cathode frame to support a cathode side of the fuel cell stack. The fuel cell can include reinforcing members to support either of the frames. | 07-09-2009 |
Kyoung-Hwan Kim, Daejeon KR
| Patent application number | Description | Published |
|---|---|---|
| 20110318535 | THREE-DIMENSIONAL NANOSTRUCTURES AND METHOD FOR FABRICATING THE SAME - A three-dimensional nanostructures and a method for fabricating the same, and more particularly to three-dimensional structures of various shapes having high aspect ratio and uniformity in large area and a method of fabricating the same by attaching a target material to the outer surface of patterned polymer structures using an ion bombardment phenomenon occurring during a physical ion etching process to form target material-polymer composite structures, and then removing the polymer from the target material-polymer structures. A three-dimensional nanostructures with high aspect ratio and uniformity can be fabricated by a simple process at low cost by using the ion bombardment phenomenon occurring during physical ion etching. Also, nanostructures of various shapes can be easily fabricated by controlling the pattern and shape of polymer structures. In addition, uniform fine nanostructures having a thickness of 10 nm or less can be formed in a large area. | 12-29-2011 |
Kyoung-Hwan Kim, Hwaseong-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080293200 | Method of fabricating nonvolatile semiconductor memory device - In a nonvolatile semiconductor memory device, and a method of fabricating the same, the nonvolatile semiconductor memory device includes a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conductive type, a channel region disposed between the source/drain regions in the semiconductor substrate, a tunnel doping region of the first conductive type formed in a predetermined region of an upper portion of the cell doping region, the tunnel doping region being doped in a higher concentration than that of the cell doping region, a tunnel insulating layer formed on a surface of the semiconductor substrate on the tunnel doping region, a gate insulating layer surrounding the tunnel insulating layer and covering the channel region and the cell doping region exposed beyond the tunnel doping region, and a gate electrode covering the tunnel insulating layer and on the gate insulating layer. | 11-27-2008 |
| 20100155958 | BONDING PAD STRUCTURE AND MANUFACTURING METHOD THEREOF - A bonding pad structure of a semiconductor device and a method of manufacturing the same reduce the likelihood of peel-off defects from occurring. The bonding pad structure includes a substrate, an interlayer insulation layer on the substrate, an upper wiring layer on the interlayer insulation layer, and a plurality of lower wiring layers disposed in the interlayer insulation layer between the upper wiring layer and the substrate and configured to prevent the interlayer insulation layer from cracking especially during a wire bonding process in which a wire is bonded to the upper wiring layer. For example, the respective areas occupied by the lower wiring layers sequentially increase in the interlayer insulation layer in a downward direction from the upper wiring layer towards the substrate. Also, each of the lower wiring layers may project further inwardly toward a central part of the bonding pad than the lower layer of wiring disposed above it in the interlayer insulation layer. | 06-24-2010 |
Kyoung-Hwan Kim, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080225178 | AUTOMATIC SIGNAL GAIN CONTROL METHOD AND APPARATUS - Provided are an automatic signal gain control method and apparatus that adaptively controls signal gain according to sync tip depths in a video receiving system. The method includes: detecting a sync signal from a video signal; detecting a blank level and a sync tip level from a sync section of the sync signal; extracting a difference between the blank level and the sync tip level, as a sync tip depth; and controlling the gain of the video signal differently according to a variation of the sync tip depth. | 09-18-2008 |
| 20090033799 | VIDEO PROCESSING METHOD AND VIDEO PROCESSING APPARATUS USING THE SAME - A video processing method and a video processing apparatus employing the same are provided. The video processing apparatus measures an amount of noise included in an incoming composite video signal, and outputs 2D comb filtered signal and 3D comb filtered signal in different proportions according to the measured amount of noise. By varying the proportions of the 2D comb filtered signal and 3D comb filtered signal according to the measured amount of noise, video artifacts associated with 2D and 3D comb filtering are compensated and improved. | 02-05-2009 |
Kyoung-Hwan Ohoi, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090142646 | DIRECT METHANOL FUEL CELL STACK INCLUDING FLOW RESTRICTOR AND DIRECT METHANOL FUEL CELL INCLUDING THE SAME - A direct methanol fuel cell (DMFC) that includes: an anode, a cathode, and a membrane disposed therebetween; a bipolar plate having a flow channel to supply a fluid to the anode; and a flow restrictor installed in the flow channel, to restrict the flow of the fluid. | 06-04-2009 |