Patent application number | Description | Published |
20080299784 | APPARATUS AND METHOD FOR THERMALLY TREATING SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING WAFER FROM WARPING - A thermal treatment apparatus and method for processing a wafer are provided. The thermal treatment apparatus includes a process chamber for thermally treating the wafer, a heating unit for heating the wafer in the process chamber, and a gas supply unit for supplying a gas and controlling a gas pressure differently by sections of the wafer. The heating unit is provided in at least one of the upper side and the lower side of the process chamber. The heating unit includes a plurality of heater blocks capable of controlling a temperature for sections of the wafer. | 12-04-2008 |
20090004837 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided is a method of fabricating a semiconductor device having an impurity region with an impurity concentration of a first dose in a substrate. In the method, first impurity ions of a first conductivity type are implanted into the substrate, and a rapid thermal processing (RTP) is performed on the substrate to activate the first impurity ions. Second impurity ions of the first conductivity type are implanted into the substrate having the activated first impurity ions. | 01-01-2009 |
20090170265 | Method of Fabricating a Recess Gate Type Transistor - A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween. | 07-02-2009 |
20090170297 | Method of Fabricating Semiconductor Device Having Gate Spacer Layer With Uniform Thickness - A method of fabricating a semiconductor device having a gate spacer layer with a uniform thickness wherein a gate electrode layer pattern is formed on a substrate and ion implantation processes of respectively different doses are formed on side walls of the gate electrode layer patterns in respective first and second regions of the substrate. A first gate spacer layer is formed on the gate electrode layer pattern where the ion implantation process is performed. A second gate spacer layer is formed on the first gate spacer layer. | 07-02-2009 |
20090173996 | Recess Gate Type Transistor - A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween. | 07-09-2009 |
20100041196 | Method for Fabricating a Transistor having a Recess Gate Structure - A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate. | 02-18-2010 |
20100099244 | PARTIAL IMPLANTATION METHOD FOR SEMICONDUCTOR MANUFACTURING - Disclosed herein is a partial implantation method for manufacturing semiconductor devices. The method involves implantation of dopant ions at different densities into a plurality of wafer regions, including first and second regions, defined in a wafer by means of a boundary line. In the method, first, second and third implantation zones are defined. The first implantation zone is the remaining part of the first region except for a specific part of the first region close to the boundary line, the second implantation zone is the remaining part of the second region except for a specific part of the second region close to the boundary line, and the third implantation zone is the remaining part of the wafer except for the first and second implantation zones. Then, dopant ions are implanted into the first implantation zone at a first density, into the second implantation zone at a second density different from the first density, and into the third implantation zone at a third density that is a midway value between the first and second densities. | 04-22-2010 |
20100120240 | METHOD FOR FABRICATING PMOS TRANSISTOR AND METHOD FOR FORMING DUAL GATE USING THE SAME - Provided are a method for fabricating a PMOS transistor and a method for forming a dual gate of a semiconductor device using the same. The method for fabricating a PMOS transistor includes forming a gate insulation layer over a semiconductor substrate; forming a polysilicon layer over the gate insulation layer; and doping the polysilicon layer using a boron (B) containing gas in one of an Atomic Layer Deposition (ALD) chamber and a Chemical Vapor Deposition (CVD) chamber. | 05-13-2010 |
20120280309 | MOS TRANSISTOR SUPPRESSING SHORT CHANNEL EFFECT AND METHOD OF FABRICATING THE SAME - A MOS transistor suppressing a short channel effect includes a substrate, a first diffusion region and a second diffusion region separated from each other by a channel region in an upper portion of the substrate, a gate insulating layer including a first gate insulating layer disposed on a surface of the substrate in the channel region and a second gate insulating layer having a specified depth from the surface of the substrate to be disposed between the first diffusion region and the channel region, and a gate electrode disposed on the first gate insulating layer. | 11-08-2012 |