| Patent application number | Description | Published |
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| 20100157717 | SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF CONTROLLING READ COMMAND - The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode. | 06-24-2010 |
| 20110075502 | BANK ACTIVE SIGNAL GENERATION CIRCUIT - The bank active signal generation circuit comprises a decoded signal generator and an active signal generator. The decoded signal generator generates decoded signals from a first bank access signal, a second bank access signal and a row address signal in response to when a prefetch signal at a first mode. The decoded signal generator also generates decoded signals from the first bank access signal, the second bank access signal, and a third bank access signal in response when the prefetch signal at a second mode. The active signal generator generates bank active signals in response to receiving the decoded signals, an active pulse and a precharge pulse. | 03-31-2011 |
| 20110110176 | ADDRESS CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - An address control circuit is presented for use in reducing a skew in a write operation mode. The address control circuit includes a read column address control circuit and a write column address control circuit. The read column address control circuit is configured to generate a read column address from an address during a first burst period for a read operation mode. The write column address control circuit is configured to generate a write column address from the address during a second burst period for a write operation mode. | 05-12-2011 |
| 20110128811 | INTERNAL COMMAND GENERATION CIRCUIT - The internal command generation circuit includes a burst pulse generation unit and a pulse shifting unit. The burst pulse generation unit is configured to receive a command for a read or write operation, and generate a first burst pulse. The pulse shifting unit is configured to shift the first burst pulse and generate an internal command. | 06-02-2011 |
| Patent application number | Description | Published |
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| 20090003106 | Precharge control circuit - A precharge control circuit includes a precharge control unit and a precharge unit. The precharge control unit controls and outputs a precharge signal in response to a read command signal, a write command signal, and a first signal. The precharge unit precharges local input/output lines in response to a signal output from the precharge control unit. | 01-01-2009 |
| 20090168564 | Strobe signal controlling circuit - A strobe signal controlling circuit is provided which includes an initial write controller configured to outputs a write pulse signal, which is activated in a write command, in synchronization with a clock signal, a DQS signal outputting unit configured to outputs a write DQS signal by synchronizing an output signal of the initial write controller to the clock signal, a control signal generator configured to generates a control signal in response to the output signal of the initial write controller, and a reset signal generator configured to responds to a reset signal and a DQS enable signal to output a reset signal to the DQS signal outputting module in synchronization with the control signal. | 07-02-2009 |
| 20100177590 | Burst mode control circuit - A burst mode control unit includes a burst period signal generation unit for generating a burst period signal which is enabled during a burst mode operation period, a burst pulse generation unit for generating a burst pulse, which is generated at every predetermined number of cycles during the enabled period of the burst period signal, in response to a read command and a write command, and a column access signal generation unit for receiving the burst signal and a clock signal and generating a column access signal which controls input and output of data during the burst mode operation period. | 07-15-2010 |
| 20100202225 | Data input circuit technical field - A data input circuit comprises a sensing control unit which delays an internal write command by a predetermined period and generates a sense amplifier enable signal in response to a first clock signal, and a data sensing unit which senses align data and transfers the sensed data to a global line in response to the sense amplifier enable signal, wherein the sense amplifier enable signal is enabled at a time point when the align data is inputted in the data sensing unit. | 08-12-2010 |
| 20100246310 | Address converting circuit and semiconductor memory device using the same - A semiconductor memory includes an address converting circuit which latches an address and a bank signal and generates a latch address for activating a data access path of a second bank group, and converts the latch address according to a level of the bank signal and generates a variable address for activating a data access path of a first bank group, a first column decoder which decodes the variable address and generates a first output enable signal for activating the data access path of the first bank group, and a second column decoder which decodes the latch address and generates a second output enable signal for activating the data access path of the second bank group. | 09-30-2010 |
